Water mark update need to wait for next VSYNC?

Water mark update need to wait for next VSYNC?

[Xie, William]

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Hi all,
 Can anyone educate me if water mark update need to wait for next VSYNC?
In other words, if we flip a frame to overlay for the first time,
it will be showed in the next VBlank as water mark update needs to wait for that?

Is this true or a bug?

Thanks
William

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Re: Water mark update need to wait for next VSYNC?

[Zhi Wang]

Hi William:
     There is a kind of display register marked as double-buffered. It 
means that HW will *not* latch the value in the register all the time. 
HW will only latch the value on the start of the vertical blank, or the 
time when pipe/plane are enabling.

So you will see some code pieces are waiting for frame count change 
after updating a register.

For WM registers, it should be double-buffered with armed attribute I 
believe. It means after writing the WM registers, you have to write 
another register to let the WM register become into "armed" state. After 
the register is "armed", HW will latch the value on the time point 
mentioned above.

So you should see in some code pieces, they write another register after 
updating the target register, then waits for the frame count change.

i.e update WM register -> update PLANE SURF register -> wait for frame 
count change

于 09/03/15 06:42, Xie, William 写道:
> Hi all,
>
>   Can anyone educate me if water mark update need to wait for next VSYNC?
>
> In other words, if we flip a frame to overlay for the first time,
>
> it will be showed in the next VBlank as water mark update needs to wait
> for that?
>
> Is this true or a bug?
>
> Thanks
>
> William
>
>
>
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> http://lists.freedesktop.org/mailman/listinfo/intel-gfx
>
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Re: Water mark update need to wait for next VSYNC?

[Ville Syrjälä]

On Sun, Sep 06, 2015 at 07:30:26PM +0800, Zhi Wang wrote:
> Hi William:
>      There is a kind of display register marked as double-buffered. It 
> means that HW will *not* latch the value in the register all the time. 
> HW will only latch the value on the start of the vertical blank, or the 
> time when pipe/plane are enabling.
> 
> So you will see some code pieces are waiting for frame count change 
> after updating a register.
> 
> For WM registers, it should be double-buffered with armed attribute I 
> believe.

Only since SKL. Before that WM registers weren't double buffered.

> It means after writing the WM registers, you have to write 
> another register to let the WM register become into "armed" state. After 
> the register is "armed", HW will latch the value on the time point 
> mentioned above.
> 
> So you should see in some code pieces, they write another register after 
> updating the target register, then waits for the frame count change.
> 
> i.e update WM register -> update PLANE SURF register -> wait for frame 
> count change
> 
> 于 09/03/15 06:42, Xie, William 写道:
> > Hi all,
> >
> >   Can anyone educate me if water mark update need to wait for next VSYNC?
> >
> > In other words, if we flip a frame to overlay for the first time,
> >
> > it will be showed in the next VBlank as water mark update needs to wait
> > for that?
> >
> > Is this true or a bug?
> >
> > Thanks
> >
> > William
> >
> >
> >
> > _______________________________________________
> > Intel-gfx mailing list
> > Intel-gfx@lists.freedesktop.org
> > http://lists.freedesktop.org/mailman/listinfo/intel-gfx
> >
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> http://lists.freedesktop.org/mailman/listinfo/intel-gfx

-- 
Ville Syrjälä
Intel OTC
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Re: Water mark update need to wait for next VSYNC?

[Zhi Wang]

Thanks Ville! Learned from you guys. :)

于 09/06/15 19:50, Ville Syrjälä 写道:
> On Sun, Sep 06, 2015 at 07:30:26PM +0800, Zhi Wang wrote:
>> Hi William:
>>       There is a kind of display register marked as double-buffered. It
>> means that HW will *not* latch the value in the register all the time.
>> HW will only latch the value on the start of the vertical blank, or the
>> time when pipe/plane are enabling.
>>
>> So you will see some code pieces are waiting for frame count change
>> after updating a register.
>>
>> For WM registers, it should be double-buffered with armed attribute I
>> believe.
>
> Only since SKL. Before that WM registers weren't double buffered.
>
>> It means after writing the WM registers, you have to write
>> another register to let the WM register become into "armed" state. After
>> the register is "armed", HW will latch the value on the time point
>> mentioned above.
>>
>> So you should see in some code pieces, they write another register after
>> updating the target register, then waits for the frame count change.
>>
>> i.e update WM register -> update PLANE SURF register -> wait for frame
>> count change
>>
>> 于 09/03/15 06:42, Xie, William 写道:
>>> Hi all,
>>>
>>>    Can anyone educate me if water mark update need to wait for next VSYNC?
>>>
>>> In other words, if we flip a frame to overlay for the first time,
>>>
>>> it will be showed in the next VBlank as water mark update needs to wait
>>> for that?
>>>
>>> Is this true or a bug?
>>>
>>> Thanks
>>>
>>> William
>>>
>>>
>>>
>>> _______________________________________________
>>> Intel-gfx mailing list
>>> Intel-gfx@lists.freedesktop.org
>>> http://lists.freedesktop.org/mailman/listinfo/intel-gfx
>>>
>> _______________________________________________
>> Intel-gfx mailing list
>> Intel-gfx@lists.freedesktop.org
>> http://lists.freedesktop.org/mailman/listinfo/intel-gfx
>
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Re: Water mark update need to wait for next VSYNC?

[Xie, William]

What's the difference if double-buffered with armed attribute?

William

-----Original Message-----
From: Ville Syrjälä [mailto:ville.syrjala@linux.intel.com] 
Sent: Sunday, September 06, 2015 7:50 PM
To: Wang, Zhi A
Cc: Xie, William; intel-gfx@lists.freedesktop.org
Subject: Re: [Intel-gfx] Water mark update need to wait for next VSYNC?

On Sun, Sep 06, 2015 at 07:30:26PM +0800, Zhi Wang wrote:
> Hi William:
>      There is a kind of display register marked as double-buffered. It 
> means that HW will *not* latch the value in the register all the time.
> HW will only latch the value on the start of the vertical blank, or 
> the time when pipe/plane are enabling.
> 
> So you will see some code pieces are waiting for frame count change 
> after updating a register.
> 
> For WM registers, it should be double-buffered with armed attribute I 
> believe.

Only since SKL. Before that WM registers weren't double buffered.

> It means after writing the WM registers, you have to write another 
> register to let the WM register become into "armed" state. After the 
> register is "armed", HW will latch the value on the time point 
> mentioned above.
> 
> So you should see in some code pieces, they write another register 
> after updating the target register, then waits for the frame count change.
> 
> i.e update WM register -> update PLANE SURF register -> wait for frame 
> count change
> 
> 于 09/03/15 06:42, Xie, William 写道:
> > Hi all,
> >
> >   Can anyone educate me if water mark update need to wait for next VSYNC?
> >
> > In other words, if we flip a frame to overlay for the first time,
> >
> > it will be showed in the next VBlank as water mark update needs to 
> > wait for that?
> >
> > Is this true or a bug?
> >
> > Thanks
> >
> > William
> >
> >
> >
> > _______________________________________________
> > Intel-gfx mailing list
> > Intel-gfx@lists.freedesktop.org
> > http://lists.freedesktop.org/mailman/listinfo/intel-gfx
> >
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> http://lists.freedesktop.org/mailman/listinfo/intel-gfx

--
Ville Syrjälä
Intel OTC
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