From: f.fainelli@gmail.com (Florian Fainelli)
To: linux-arm-kernel@lists.infradead.org
Subject: [PATCH v2 2/3] soc: brcmstb: Add Bus Interface Unit control setup
Date: Fri, 18 Sep 2015 12:22:56 -0700 [thread overview]
Message-ID: <55FC6490.7000204@gmail.com> (raw)
In-Reply-To: <1442340900-15320-3-git-send-email-f.fainelli@gmail.com>
On 15/09/15 11:14, Florian Fainelli wrote:
> Broadcom STB SoCs (brcmstb) require an early setup of their Bus
> Interface Unit control register, this needs to happen before SMP is
> brought up because it affects how the CPU complex will be interfaced to
> the memory controller.
>
> Add support code which properly initializes the BIU registers based on
> whether "brcm,write-pairing" is present in Device Tree, and take care of
> saving and restoring credit register settings during system-wide
> suspend/resume operations.
>
> Signed-off-by: Florian Fainelli <f.fainelli@gmail.com>
Applied to soc/next with Gregory's tag and the revised function
prototype returning void.
--
Florian
WARNING: multiple messages have this Message-ID (diff)
From: Florian Fainelli <f.fainelli-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org>
To: Florian Fainelli
<f.fainelli-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org>,
linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r@public.gmane.org
Cc: devicetree-u79uwXL29TY76Z2rM5mHXA@public.gmane.org,
robh-DgEjT+Ai2ygdnm+yROfE0A@public.gmane.org,
computersforpeace-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org,
gregory.0xf0-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org,
bcm-kernel-feedback-list-dY08KVG/lbpWk0Htik3J/w@public.gmane.org
Subject: Re: [PATCH v2 2/3] soc: brcmstb: Add Bus Interface Unit control setup
Date: Fri, 18 Sep 2015 12:22:56 -0700 [thread overview]
Message-ID: <55FC6490.7000204@gmail.com> (raw)
In-Reply-To: <1442340900-15320-3-git-send-email-f.fainelli-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org>
On 15/09/15 11:14, Florian Fainelli wrote:
> Broadcom STB SoCs (brcmstb) require an early setup of their Bus
> Interface Unit control register, this needs to happen before SMP is
> brought up because it affects how the CPU complex will be interfaced to
> the memory controller.
>
> Add support code which properly initializes the BIU registers based on
> whether "brcm,write-pairing" is present in Device Tree, and take care of
> saving and restoring credit register settings during system-wide
> suspend/resume operations.
>
> Signed-off-by: Florian Fainelli <f.fainelli-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org>
Applied to soc/next with Gregory's tag and the revised function
prototype returning void.
--
Florian
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next prev parent reply other threads:[~2015-09-18 19:22 UTC|newest]
Thread overview: 24+ messages / expand[flat|nested] mbox.gz Atom feed top
2015-09-15 18:14 [PATCH v2 0/3] ARM: brcmstb: Bus Interface Unit support Florian Fainelli
2015-09-15 18:14 ` Florian Fainelli
2015-09-15 18:14 ` [PATCH v2 1/3] Documentation: bindings: brcmstb: Document write-pairing Florian Fainelli
2015-09-15 18:14 ` Florian Fainelli
2015-09-17 6:09 ` Gregory Fong
2015-09-17 6:09 ` Gregory Fong
2015-09-17 17:28 ` Florian Fainelli
2015-09-17 17:28 ` Florian Fainelli
2015-09-15 18:14 ` [PATCH v2 2/3] soc: brcmstb: Add Bus Interface Unit control setup Florian Fainelli
2015-09-15 18:14 ` Florian Fainelli
2015-09-17 6:08 ` Gregory Fong
2015-09-17 6:08 ` Gregory Fong
2015-09-17 17:42 ` Florian Fainelli
2015-09-17 17:42 ` Florian Fainelli
2015-09-18 13:12 ` Gregory Fong
2015-09-18 13:12 ` Gregory Fong
2015-09-18 19:22 ` Florian Fainelli [this message]
2015-09-18 19:22 ` Florian Fainelli
2015-09-15 18:15 ` [PATCH v2 3/3] ARM: brcmstb: Setup BIU control registers during boot Florian Fainelli
2015-09-15 18:15 ` Florian Fainelli
2015-09-17 6:10 ` Gregory Fong
2015-09-17 6:10 ` Gregory Fong
2015-09-18 19:23 ` Florian Fainelli
2015-09-18 19:23 ` Florian Fainelli
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