Re: [PATCH v2 1/2] x86/cpu: Disable CR pinning during CPU bringup

[Dave Hansen <dave.hansen@intel.com>]

Nikunj, thanks for tracking this down and filling in the last piece of
the puzzle about ALTERNATIVEs patching.

On 3/11/26 03:41, Nikunj A. Dadhania wrote:
> +	/*
> +	 * Enable FSGSBASE if available. Exception entry code (paranoid_entry)
> +	 * is patched to use RDGSBASE/WRGSBASE when this feature is present,
> +	 * and those instructions require CR4.FSGSBASE=1. Secondary CPUs must
> +	 * enable this before any exceptions occur.
> +	 */
> +	if (boot_cpu_has(X86_FEATURE_FSGSBASE))
> +		cr4 |= X86_CR4_FSGSBASE;

But this still double-enables X86_CR4_FSGSBASE. Could we initialize
X86_CR4_FSGSBASE in *one* place, please?

Also, please avoid passive voice in stuff like this. It's just more
efficient to say:

	CPUs that support FSGSBASE may use RDGSBASE/WRGSBASE in
	paranoid_entry(). Enable the feature before any exceptions
	occur.