Re: [PATCH v9 1/5] dt-bindings: Add usb3.0 phy binding for MT65xx SoCs

[Sergei Shtylyov <sergei.shtylyov-M4DtvfQ/ZS1MRgGoP+s0PdBPR1lH4CV8@public.gmane.org>]

Hello.

On 09/29/2015 06:01 AM, Chunfeng Yun wrote:

> add a DT binding documentation of usb3.0 phy for MT65xx
> SoCs from Mediatek.
>
> Acked-by: Rob Herring <robh-DgEjT+Ai2ygdnm+yROfE0A@public.gmane.org>
> Signed-off-by: Chunfeng Yun <chunfeng.yun-NuS5LvNUpcJWk0Htik3J/w@public.gmane.org>
> ---
>   .../devicetree/bindings/phy/phy-mt65xx-usb.txt     | 68 ++++++++++++++++++++++
>   1 file changed, 68 insertions(+)
>   create mode 100644 Documentation/devicetree/bindings/phy/phy-mt65xx-usb.txt
>
> diff --git a/Documentation/devicetree/bindings/phy/phy-mt65xx-usb.txt b/Documentation/devicetree/bindings/phy/phy-mt65xx-usb.txt
> new file mode 100644
> index 0000000..00100cf
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/phy/phy-mt65xx-usb.txt
> @@ -0,0 +1,68 @@
> +mt65xx USB3.0 PHY binding
> +--------------------------
> +
> +This binding describes a usb3.0 phy for mt65xx platforms of Medaitek SoC.
> +
> +Required properties (controller (parent) node):
> + - compatible	: should be "mediatek,mt8173-u3phy"
> + - reg		: offset and length of register for phy, exclude port's
> +		  register.
> + - clocks	: a list of phandle + clock-specifier pairs, one for each
> +		  entry in clock-names
> + - clock-names	: must contain
> +		  "u3phya_ref": for reference clock of usb3.0 analog phy.
> +
> +Required nodes	: a sub-node is required for each port the controller
> +		  provides. Address range information including the usual
> +		  'reg' property is used inside these nodes to describe
> +		  the controller's topology.
> +
> +Required properties (port (child) node):
> +- reg		: address and length of the register set for the port.
> +- #phy-cells	: should be 1 (See second example)
> +		  cell after port phandle is phy type from:
> +			- PHY_TYPE_USB2
> +			- PHY_TYPE_USB3
> +
> +Example:
> +
> +u3phy: usb-phy@11290000 {
> +	compatible = "mediatek,mt8173-u3phy";
> +	reg = <0 0x11290000 0 0x800>;
> +	clocks = <&apmixedsys CLK_APMIXED_REF2USB_TX>;
> +	clock-names = "u3phya_ref";
> +	#address-cells = <2>;
> +	#size-cells = <2>;
> +	ranges;

    You don't describe the above 3 props neither as mandatory nor optional.

[...]
> +Specifying phy control of devices
> +---------------------------------
> +
> +Device nodes should specify the configuration required in their "phys"
> +property, containing a phandle to the phy port node and a device type;
> +phy-names for each port are optional.
> +
> +Example:
> +
> +#include <dt-bindings/phy/phy.h>
> +
> +usb30: usb@11270000 {
> +	...
> +	phys = <&phy_port0 PHY_TYPE_USB3>;
> +	phy-names = "usb3-0";
> +	...
> +};

    Isn't the above already described in 
Documentation/devicetree/bindings/phy/phy-bindings.txt?

MBR, Sergei

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