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From: Mathias Nyman <mathias.nyman@intel.com>
To: chunfeng yun <chunfeng.yun@mediatek.com>
Cc: Mathias Nyman <mathias.nyman@linux.intel.com>,
	Rob Herring <robh+dt@kernel.org>,
	Mark Rutland <mark.rutland@arm.com>,
	Matthias Brugger <matthias.bgg@gmail.com>,
	Felipe Balbi <balbi@ti.com>,
	Sascha Hauer <s.hauer@pengutronix.de>,
	devicetree@vger.kernel.org, linux-kernel@vger.kernel.org,
	linux-arm-kernel@lists.infradead.org,
	Roger Quadros <rogerq@ti.com>,
	linux-usb@vger.kernel.org, linux-mediatek@lists.infradead.org,
	John Crispin <blogic@openwrt.org>,
	Daniel Kurtz <djkurtz@chromium.org>,
	Sergei Shtylyov <sergei.shtylyov@cogentembedded.com>,
	Kishon Vijay Abraham I <kishon@ti.com>,
	Pawel Moll <pawel.moll@arm.com>,
	Ian Campbell <ijc+devicetree@hellion.org.uk>,
	Kumar Gala <galak@codeaurora.org>,
	Greg Kroah-Hartman <gregkh@linuxfoundation.org>
Subject: Re: [PATCH v9 4/5] xhci: mediatek: support MTK xHCI host controller
Date: Tue, 20 Oct 2015 11:25:23 +0300	[thread overview]
Message-ID: <5625FA73.3050309@intel.com> (raw)
In-Reply-To: <1445322554.4858.12.camel@mhfsdcap03>

On 20.10.2015 09:29, chunfeng yun wrote:
> hi,
> On Mon, 2015-10-19 at 14:25 +0300, Mathias Nyman wrote:
>>>>
>>>> So basically we are trying to use as many microframes as possible with as few packets
>>>> per microframe as possible.
>>>>
>>>> Did I understand this correctly?
>>> Yes, you are right.
>>>
>>>> How will devices react if they expect to get 16 packets every 16th microframe,
>>>> but they get one packet every microframe instead?
>>> I think that the synchronous endpoint must specify its period by
>>> bInterval, but can't specify how data should be transfered during the
>>> period by the host, and it just only receives data passively. So the
>>> device can receive data correctly in the case(bInterval is 5).
>>>
>>> quote from usb3_r1.0 section4.4.8 Isochronous Transfers:
>>> "The host can request data from the device or send data to the device at
>>> any time during the service interval for a particular endpoint on that
>>> device"
>>>
>>
>> As I understand the 4.4.8 section it just means the device can't assume a fixed
>> time interval between transfers, meaning that the host can use the last microframe
>> in one esit and the first microframe in the next esit, but still only use 1 microframe
>> per esit.
>>
>> Section 8.12.6.1 describes how a 11 packet isoc transfer is allowed to be split
>> to 1 burst of 11 packets, 2 burst (8 + 3),  3 burst (4+4+3) 6 bursts (2+2+2+2+2+1) or
>> 11 bursts of 1. These are however all within the same microframe. Splitting the
>> transfer into several microframes in a esit kind of makes the whole interval concept pointless.
>>
> It doesn't say that the packets should be transfered within the same
> microframe (bus interval), as I understand it means service interval;
>
> The direct prove resides in figure 8-56/8-57.
>
> Term:
> 1. BI, bus interval, a 125 us period that establishes the internal
> boundary of service interval, aka uframe;
> 2. SSI, Support Smart Isochronous;
> 3. DBI, Data in this Bus Interval is done;
> 4. NBI, Numbers of Bus Interval;
>
> As the figure shows, the service interval = 8 BI, that host distribute 2
> packets @1st uframe, keep U1/U2 state for the next 3uframe, then
> transmit 4 packets @4th uframe, and the remaining 3 packet in the last
> frame.
>
> Please notice that this just is an example illustrated by spec, but we
> can derive the conclusion that the distribution of packet in a service
> interval is completely decided by host, and can split isoc transfers
> across multiple uframes.

So it seems. You're right

>
> PS: as you can see, MTK implementation of schedule algorithms is an
> implementation of Smart Isochronous of which the smart side resides in
> software.

Thanks for the clarification, I now understand how the implementation works

-Mathias  

WARNING: multiple messages have this Message-ID (diff)
From: mathias.nyman@intel.com (Mathias Nyman)
To: linux-arm-kernel@lists.infradead.org
Subject: [PATCH v9 4/5] xhci: mediatek: support MTK xHCI host controller
Date: Tue, 20 Oct 2015 11:25:23 +0300	[thread overview]
Message-ID: <5625FA73.3050309@intel.com> (raw)
In-Reply-To: <1445322554.4858.12.camel@mhfsdcap03>

On 20.10.2015 09:29, chunfeng yun wrote:
> hi,
> On Mon, 2015-10-19 at 14:25 +0300, Mathias Nyman wrote:
>>>>
>>>> So basically we are trying to use as many microframes as possible with as few packets
>>>> per microframe as possible.
>>>>
>>>> Did I understand this correctly?
>>> Yes, you are right.
>>>
>>>> How will devices react if they expect to get 16 packets every 16th microframe,
>>>> but they get one packet every microframe instead?
>>> I think that the synchronous endpoint must specify its period by
>>> bInterval, but can't specify how data should be transfered during the
>>> period by the host, and it just only receives data passively. So the
>>> device can receive data correctly in the case(bInterval is 5).
>>>
>>> quote from usb3_r1.0 section4.4.8 Isochronous Transfers:
>>> "The host can request data from the device or send data to the device at
>>> any time during the service interval for a particular endpoint on that
>>> device"
>>>
>>
>> As I understand the 4.4.8 section it just means the device can't assume a fixed
>> time interval between transfers, meaning that the host can use the last microframe
>> in one esit and the first microframe in the next esit, but still only use 1 microframe
>> per esit.
>>
>> Section 8.12.6.1 describes how a 11 packet isoc transfer is allowed to be split
>> to 1 burst of 11 packets, 2 burst (8 + 3),  3 burst (4+4+3) 6 bursts (2+2+2+2+2+1) or
>> 11 bursts of 1. These are however all within the same microframe. Splitting the
>> transfer into several microframes in a esit kind of makes the whole interval concept pointless.
>>
> It doesn't say that the packets should be transfered within the same
> microframe (bus interval), as I understand it means service interval;
>
> The direct prove resides in figure 8-56/8-57.
>
> Term:
> 1. BI, bus interval, a 125 us period that establishes the internal
> boundary of service interval, aka uframe;
> 2. SSI, Support Smart Isochronous;
> 3. DBI, Data in this Bus Interval is done;
> 4. NBI, Numbers of Bus Interval;
>
> As the figure shows, the service interval = 8 BI, that host distribute 2
> packets @1st uframe, keep U1/U2 state for the next 3uframe, then
> transmit 4 packets @4th uframe, and the remaining 3 packet in the last
> frame.
>
> Please notice that this just is an example illustrated by spec, but we
> can derive the conclusion that the distribution of packet in a service
> interval is completely decided by host, and can split isoc transfers
> across multiple uframes.

So it seems. You're right

>
> PS: as you can see, MTK implementation of schedule algorithms is an
> implementation of Smart Isochronous of which the smart side resides in
> software.

Thanks for the clarification, I now understand how the implementation works

-Mathias  

  reply	other threads:[~2015-10-20  8:25 UTC|newest]

Thread overview: 65+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2015-09-29  3:01 [PATCH v9 0/5] Mediatek xHCI support Chunfeng Yun
2015-09-29  3:01 ` Chunfeng Yun
2015-09-29  3:01 ` Chunfeng Yun
2015-09-29  3:01 ` [PATCH v9 2/5] dt-bindings: Add a binding for Mediatek xHCI host controller Chunfeng Yun
2015-09-29  3:01   ` Chunfeng Yun
2015-09-29  3:01   ` Chunfeng Yun
     [not found]   ` <1443495698-32233-3-git-send-email-chunfeng.yun-NuS5LvNUpcJWk0Htik3J/w@public.gmane.org>
2015-09-29 14:49     ` Sergei Shtylyov
2015-09-29 14:49       ` Sergei Shtylyov
2015-09-29 14:49       ` Sergei Shtylyov
2015-10-08 11:37       ` chunfeng yun
2015-10-08 11:37         ` chunfeng yun
2015-10-08 11:37         ` chunfeng yun
2015-09-29  3:01 ` [PATCH v9 3/5] phy: add usb3.0 phy driver for mt65xx SoCs Chunfeng Yun
2015-09-29  3:01   ` Chunfeng Yun
2015-09-29  3:01   ` Chunfeng Yun
     [not found]   ` <1443495698-32233-4-git-send-email-chunfeng.yun-NuS5LvNUpcJWk0Htik3J/w@public.gmane.org>
2015-10-06 14:20     ` Kishon Vijay Abraham I
2015-10-06 14:20       ` Kishon Vijay Abraham I
2015-10-06 14:20       ` Kishon Vijay Abraham I
2015-10-08 11:45       ` chunfeng yun
2015-10-08 11:45         ` chunfeng yun
2015-10-08 11:45         ` chunfeng yun
2015-09-29  3:01 ` [PATCH v9 4/5] xhci: mediatek: support MTK xHCI host controller Chunfeng Yun
2015-09-29  3:01   ` Chunfeng Yun
2015-09-29  3:01   ` Chunfeng Yun
     [not found]   ` <1443495698-32233-5-git-send-email-chunfeng.yun-NuS5LvNUpcJWk0Htik3J/w@public.gmane.org>
2015-10-01 11:44     ` Daniel Thompson
2015-10-01 11:44       ` Daniel Thompson
2015-10-01 11:44       ` Daniel Thompson
2015-10-08 12:05       ` chunfeng yun
2015-10-08 12:05         ` chunfeng yun
2015-10-08 12:05         ` chunfeng yun
2015-10-08 12:28         ` Daniel Thompson
2015-10-08 12:28           ` Daniel Thompson
     [not found]           ` <5616616D.3080205-QSEj5FYQhm4dnm+yROfE0A@public.gmane.org>
2015-10-08 13:05             ` Mathias Nyman
2015-10-08 13:05               ` Mathias Nyman
2015-10-08 13:05               ` Mathias Nyman
2015-10-08 14:42               ` chunfeng yun
2015-10-08 14:42                 ` chunfeng yun
2015-10-08 14:42                 ` chunfeng yun
2015-10-08 14:38             ` chunfeng yun
2015-10-08 14:38               ` chunfeng yun
2015-10-08 14:38               ` chunfeng yun
2015-10-15 14:46   ` Mathias Nyman
2015-10-15 14:46     ` Mathias Nyman
     [not found]     ` <561FBC40.7020100-VuQAYsv1563Yd54FQh9/CA@public.gmane.org>
2015-10-18  1:25       ` chunfeng yun
2015-10-18  1:25         ` chunfeng yun
2015-10-18  1:25         ` chunfeng yun
2015-10-19 11:25         ` Mathias Nyman
2015-10-19 11:25           ` Mathias Nyman
     [not found]           ` <5624D33D.5090807-ral2JQCrhuEAvxtiuMwx3w@public.gmane.org>
2015-10-20  6:29             ` chunfeng yun
2015-10-20  6:29               ` chunfeng yun
2015-10-20  6:29               ` chunfeng yun
2015-10-20  8:25               ` Mathias Nyman [this message]
2015-10-20  8:25                 ` Mathias Nyman
     [not found] ` <1443495698-32233-1-git-send-email-chunfeng.yun-NuS5LvNUpcJWk0Htik3J/w@public.gmane.org>
2015-09-29  3:01   ` [PATCH v9 1/5] dt-bindings: Add usb3.0 phy binding for MT65xx SoCs Chunfeng Yun
2015-09-29  3:01     ` Chunfeng Yun
2015-09-29  3:01     ` Chunfeng Yun
     [not found]     ` <1443495698-32233-2-git-send-email-chunfeng.yun-NuS5LvNUpcJWk0Htik3J/w@public.gmane.org>
2015-09-29 14:43       ` Sergei Shtylyov
2015-09-29 14:43         ` Sergei Shtylyov
2015-09-29 14:43         ` Sergei Shtylyov
     [not found]         ` <560AA37E.2090106-M4DtvfQ/ZS1MRgGoP+s0PdBPR1lH4CV8@public.gmane.org>
2015-10-08 11:27           ` chunfeng yun
2015-10-08 11:27             ` chunfeng yun
2015-10-08 11:27             ` chunfeng yun
2015-09-29  3:01   ` [PATCH v9 5/5] arm64: dts: mediatek: add xHCI & usb phy for mt8173 Chunfeng Yun
2015-09-29  3:01     ` Chunfeng Yun
2015-09-29  3:01     ` Chunfeng Yun

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