[PATCH 1/2] mmc: dw_mmc: fix the CardThreshold boundary at CardThrCtl register

[PATCH 1/2] mmc: dw_mmc: fix the CardThreshold boundary at CardThrCtl register

[Jaehoon Chung]

According to DesignWare DoC file, CardThreshold bit should be
bit[27:16].
So it's correct to use (0xFFF << 16), not (0x1FFF << 16).

Signed-off-by: Jaehoon Chung <jh80.chung@samsung.com>
---
 drivers/mmc/host/dw_mmc.h | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/mmc/host/dw_mmc.h b/drivers/mmc/host/dw_mmc.h
index f2a88d4..01cdc86 100644
--- a/drivers/mmc/host/dw_mmc.h
+++ b/drivers/mmc/host/dw_mmc.h
@@ -172,7 +172,7 @@
 /* Version ID register define */
 #define SDMMC_GET_VERID(x)		((x) & 0xFFFF)
 /* Card read threshold */
-#define SDMMC_SET_RD_THLD(v, x)		(((v) & 0x1FFF) << 16 | (x))
+#define SDMMC_SET_RD_THLD(v, x)		(((v) & 0xFFF) << 16 | (x))
 #define SDMMC_UHS_18V			BIT(0)
 /* All ctrl reset bits */
 #define SDMMC_CTRL_ALL_RESET_FLAGS \
-- 
1.9.1

[PATCH 2/2] mmc: dw_mmc: fix the wrong setting for UHS-DDR50 mode

[Jaehoon Chung]

When card is running with DDR mode, dwmmc needs to set DDR_REG bit at
UHS_REG register.
Before this patch, dwmmc controller doesn't consider this.
If this patch is not applied, CRC or other error shoulds be occurred.

Signed-off-by: Jaehoon Chung <jh80.chung@samsung.com>
---
 drivers/mmc/host/dw_mmc.c | 1 +
 1 file changed, 1 insertion(+)

diff --git a/drivers/mmc/host/dw_mmc.c b/drivers/mmc/host/dw_mmc.c
index 6e600e8..cb31e8e 100644
--- a/drivers/mmc/host/dw_mmc.c
+++ b/drivers/mmc/host/dw_mmc.c
@@ -1295,6 +1295,7 @@ static void dw_mci_set_ios(struct mmc_host *mmc, struct mmc_ios *ios)
 
 	/* DDR mode set */
 	if (ios->timing == MMC_TIMING_MMC_DDR52 ||
+	    ios->timing == MMC_TIMING_UHS_DDR50 ||
 	    ios->timing == MMC_TIMING_MMC_HS400)
 		regs |= ((0x1 << slot->id) << 16);
 	else
-- 
1.9.1

Re: [2/2] mmc: dw_mmc: fix the wrong setting for UHS-DDR50 mode

[Alim Akhtar]

Hi Jaehoon,

On 10/21/2015 04:19 PM, Jaehoon Chung wrote:
> When card is running with DDR mode, dwmmc needs to set DDR_REG bit at
> UHS_REG register.
> Before this patch, dwmmc controller doesn't consider this.
> If this patch is not applied, CRC or other error shoulds be occurred.
> 
> Signed-off-by: Jaehoon Chung <jh80.chung@samsung.com>
> 
Looks good to me,
Reviewed-by: Alim Akhtar <alim.akhtar@samsung.com>
Tested on peach board with some additional dt changes, works well.
so, Tested-by: Alim Akhtar <alim.akhtar@samsung.com>

> ---
> drivers/mmc/host/dw_mmc.c | 1 +
>   1 file changed, 1 insertion(+)
> 
> diff --git a/drivers/mmc/host/dw_mmc.c b/drivers/mmc/host/dw_mmc.c
> index 6e600e8..cb31e8e 100644
> --- a/drivers/mmc/host/dw_mmc.c
> +++ b/drivers/mmc/host/dw_mmc.c
> @@ -1295,6 +1295,7 @@ static void dw_mci_set_ios(struct mmc_host *mmc, struct mmc_ios *ios)
>   
>   	/* DDR mode set */
>   	if (ios->timing == MMC_TIMING_MMC_DDR52 ||
> +	    ios->timing == MMC_TIMING_UHS_DDR50 ||
>   	    ios->timing == MMC_TIMING_MMC_HS400)
>   		regs |= ((0x1 << slot->id) << 16);
>   	else
> 

Re: [1/2] mmc: dw_mmc: fix the CardThreshold boundary at CardThrCtl register

[Alim Akhtar]

Hi Jaehoon

On 10/21/2015 04:19 PM, Jaehoon Chung wrote:
> According to DesignWare DoC file, CardThreshold bit should be
> bit[27:16].
> So it's correct to use (0xFFF << 16), not (0x1FFF << 16).
> 
> Signed-off-by: Jaehoon Chung <jh80.chung@samsung.com>
> 
Looks good.
Reviewed-by: Alim Akhtar <alim.akhtar@samsung.com>

> ---
> drivers/mmc/host/dw_mmc.h | 2 +-
>   1 file changed, 1 insertion(+), 1 deletion(-)
> 
> diff --git a/drivers/mmc/host/dw_mmc.h b/drivers/mmc/host/dw_mmc.h
> index f2a88d4..01cdc86 100644
> --- a/drivers/mmc/host/dw_mmc.h
> +++ b/drivers/mmc/host/dw_mmc.h
> @@ -172,7 +172,7 @@
>   /* Version ID register define */
>   #define SDMMC_GET_VERID(x)		((x) & 0xFFFF)
>   /* Card read threshold */
> -#define SDMMC_SET_RD_THLD(v, x)		(((v) & 0x1FFF) << 16 | (x))
> +#define SDMMC_SET_RD_THLD(v, x)		(((v) & 0xFFF) << 16 | (x))
>   #define SDMMC_UHS_18V			BIT(0)
>   /* All ctrl reset bits */
>   #define SDMMC_CTRL_ALL_RESET_FLAGS \
>