* [Intel-wired-lan] [PATCH] ixgbe: Wait for 1ms, not 1us, after RST @ 2015-10-27 0:16 ` dan.streetman 0 siblings, 0 replies; 10+ messages in thread From: dan.streetman @ 2015-10-27 0:16 UTC (permalink / raw) To: intel-wired-lan From: Dan Streetman <dan.streetman@canonical.com> The driver currently waits 1us after issuing a RST, but the spec requires it to wait 1ms. Signed-off-by: Dan Streetman <dan.streetman@canonical.com> Signed-off-by: Dan Streetman <ddstreet@ieee.org> --- drivers/net/ethernet/intel/ixgbe/ixgbe_x540.c | 7 ++++++- 1 file changed, 6 insertions(+), 1 deletion(-) diff --git a/drivers/net/ethernet/intel/ixgbe/ixgbe_x540.c b/drivers/net/ethernet/intel/ixgbe/ixgbe_x540.c index 4e75843..147bc65 100644 --- a/drivers/net/ethernet/intel/ixgbe/ixgbe_x540.c +++ b/drivers/net/ethernet/intel/ixgbe/ixgbe_x540.c @@ -113,7 +113,12 @@ mac_reset_top: /* Poll for reset bit to self-clear indicating reset is complete */ for (i = 0; i < 10; i++) { - udelay(1); + /* sec 8.2.4.1.1 : + * programmers must wait approximately 1 ms after setting before + * attempting to check if the bit has cleared or to access (read + * or write) any other device register. + */ + mdelay(1); ctrl = IXGBE_READ_REG(hw, IXGBE_CTRL); if (!(ctrl & IXGBE_CTRL_RST_MASK)) break; -- 2.5.0 ^ permalink raw reply related [flat|nested] 10+ messages in thread
* [PATCH] ixgbe: Wait for 1ms, not 1us, after RST @ 2015-10-27 0:16 ` dan.streetman 0 siblings, 0 replies; 10+ messages in thread From: dan.streetman @ 2015-10-27 0:16 UTC (permalink / raw) To: Jeff Kirsher Cc: Jesse Brandeburg, Shannon Nelson, Carolyn Wyborny, Don Skidmore, Matthew Vick, John Ronciak, Mitch Williams, intel-wired-lan, netdev, linux-kernel, Dan Streetman, Dan Streetman From: Dan Streetman <dan.streetman@canonical.com> The driver currently waits 1us after issuing a RST, but the spec requires it to wait 1ms. Signed-off-by: Dan Streetman <dan.streetman@canonical.com> Signed-off-by: Dan Streetman <ddstreet@ieee.org> --- drivers/net/ethernet/intel/ixgbe/ixgbe_x540.c | 7 ++++++- 1 file changed, 6 insertions(+), 1 deletion(-) diff --git a/drivers/net/ethernet/intel/ixgbe/ixgbe_x540.c b/drivers/net/ethernet/intel/ixgbe/ixgbe_x540.c index 4e75843..147bc65 100644 --- a/drivers/net/ethernet/intel/ixgbe/ixgbe_x540.c +++ b/drivers/net/ethernet/intel/ixgbe/ixgbe_x540.c @@ -113,7 +113,12 @@ mac_reset_top: /* Poll for reset bit to self-clear indicating reset is complete */ for (i = 0; i < 10; i++) { - udelay(1); + /* sec 8.2.4.1.1 : + * programmers must wait approximately 1 ms after setting before + * attempting to check if the bit has cleared or to access (read + * or write) any other device register. + */ + mdelay(1); ctrl = IXGBE_READ_REG(hw, IXGBE_CTRL); if (!(ctrl & IXGBE_CTRL_RST_MASK)) break; -- 2.5.0 ^ permalink raw reply related [flat|nested] 10+ messages in thread
* [Intel-wired-lan] [PATCH] ixgbe: Wait for 1ms, not 1us, after RST 2015-10-27 0:16 ` dan.streetman @ 2015-10-27 17:03 ` Skidmore, Donald C -1 siblings, 0 replies; 10+ messages in thread From: Skidmore, Donald C @ 2015-10-27 17:03 UTC (permalink / raw) To: intel-wired-lan > -----Original Message----- > From: dan.streetman at canonical.com > [mailto:dan.streetman at canonical.com] > Sent: Monday, October 26, 2015 5:16 PM > To: Kirsher, Jeffrey T > Cc: Brandeburg, Jesse; Nelson, Shannon; Wyborny, Carolyn; Skidmore, > Donald C; Vick, Matthew; Ronciak, John; Williams, Mitch A; intel-wired- > lan at lists.osuosl.org; netdev at vger.kernel.org; linux-kernel at vger.kernel.org; > Dan Streetman; Dan Streetman > Subject: [PATCH] ixgbe: Wait for 1ms, not 1us, after RST > > From: Dan Streetman <dan.streetman@canonical.com> > > The driver currently waits 1us after issuing a RST, but the spec requires it to > wait 1ms. > > Signed-off-by: Dan Streetman <dan.streetman@canonical.com> > Signed-off-by: Dan Streetman <ddstreet@ieee.org> > --- > drivers/net/ethernet/intel/ixgbe/ixgbe_x540.c | 7 ++++++- > 1 file changed, 6 insertions(+), 1 deletion(-) > > diff --git a/drivers/net/ethernet/intel/ixgbe/ixgbe_x540.c > b/drivers/net/ethernet/intel/ixgbe/ixgbe_x540.c > index 4e75843..147bc65 100644 > --- a/drivers/net/ethernet/intel/ixgbe/ixgbe_x540.c > +++ b/drivers/net/ethernet/intel/ixgbe/ixgbe_x540.c > @@ -113,7 +113,12 @@ mac_reset_top: > > /* Poll for reset bit to self-clear indicating reset is complete */ > for (i = 0; i < 10; i++) { > - udelay(1); > + /* sec 8.2.4.1.1 : > + * programmers must wait approximately 1 ms after setting > before > + * attempting to check if the bit has cleared or to access > (read > + * or write) any other device register. > + */ > + mdelay(1); > ctrl = IXGBE_READ_REG(hw, IXGBE_CTRL); > if (!(ctrl & IXGBE_CTRL_RST_MASK)) > break; > -- > 2.5.0 While the Data Sheet does mention that this should take ~ 1ms, we are in a busy wait state so it probably isn't that big of a deal to check more frequently for our exit condition. That said there are plenty of other delays later on in the reset path so keeping the udelay really isn't speeding things up much. :) Also normally it isn't a good idea to reference a section number in the data sheet as they do seem to change with updates. We are most likely a bit more safe here as it is one of the first of a list of register descriptions' and thus less like to move. ^ permalink raw reply [flat|nested] 10+ messages in thread
* RE: [PATCH] ixgbe: Wait for 1ms, not 1us, after RST @ 2015-10-27 17:03 ` Skidmore, Donald C 0 siblings, 0 replies; 10+ messages in thread From: Skidmore, Donald C @ 2015-10-27 17:03 UTC (permalink / raw) To: dan.streetman@canonical.com, Kirsher, Jeffrey T Cc: Brandeburg, Jesse, Nelson, Shannon, Wyborny, Carolyn, Vick, Matthew, Ronciak, John, Williams, Mitch A, intel-wired-lan@lists.osuosl.org, netdev@vger.kernel.org, linux-kernel@vger.kernel.org, Dan Streetman > -----Original Message----- > From: dan.streetman@canonical.com > [mailto:dan.streetman@canonical.com] > Sent: Monday, October 26, 2015 5:16 PM > To: Kirsher, Jeffrey T > Cc: Brandeburg, Jesse; Nelson, Shannon; Wyborny, Carolyn; Skidmore, > Donald C; Vick, Matthew; Ronciak, John; Williams, Mitch A; intel-wired- > lan@lists.osuosl.org; netdev@vger.kernel.org; linux-kernel@vger.kernel.org; > Dan Streetman; Dan Streetman > Subject: [PATCH] ixgbe: Wait for 1ms, not 1us, after RST > > From: Dan Streetman <dan.streetman@canonical.com> > > The driver currently waits 1us after issuing a RST, but the spec requires it to > wait 1ms. > > Signed-off-by: Dan Streetman <dan.streetman@canonical.com> > Signed-off-by: Dan Streetman <ddstreet@ieee.org> > --- > drivers/net/ethernet/intel/ixgbe/ixgbe_x540.c | 7 ++++++- > 1 file changed, 6 insertions(+), 1 deletion(-) > > diff --git a/drivers/net/ethernet/intel/ixgbe/ixgbe_x540.c > b/drivers/net/ethernet/intel/ixgbe/ixgbe_x540.c > index 4e75843..147bc65 100644 > --- a/drivers/net/ethernet/intel/ixgbe/ixgbe_x540.c > +++ b/drivers/net/ethernet/intel/ixgbe/ixgbe_x540.c > @@ -113,7 +113,12 @@ mac_reset_top: > > /* Poll for reset bit to self-clear indicating reset is complete */ > for (i = 0; i < 10; i++) { > - udelay(1); > + /* sec 8.2.4.1.1 : > + * programmers must wait approximately 1 ms after setting > before > + * attempting to check if the bit has cleared or to access > (read > + * or write) any other device register. > + */ > + mdelay(1); > ctrl = IXGBE_READ_REG(hw, IXGBE_CTRL); > if (!(ctrl & IXGBE_CTRL_RST_MASK)) > break; > -- > 2.5.0 While the Data Sheet does mention that this should take ~ 1ms, we are in a busy wait state so it probably isn't that big of a deal to check more frequently for our exit condition. That said there are plenty of other delays later on in the reset path so keeping the udelay really isn't speeding things up much. :) Also normally it isn't a good idea to reference a section number in the data sheet as they do seem to change with updates. We are most likely a bit more safe here as it is one of the first of a list of register descriptions' and thus less like to move. ^ permalink raw reply [flat|nested] 10+ messages in thread
* [Intel-wired-lan] [PATCH] ixgbe: Wait for 1ms, not 1us, after RST 2015-10-27 17:03 ` Skidmore, Donald C @ 2015-10-27 17:32 ` Dan Streetman -1 siblings, 0 replies; 10+ messages in thread From: Dan Streetman @ 2015-10-27 17:32 UTC (permalink / raw) To: intel-wired-lan On Tue, Oct 27, 2015 at 1:03 PM, Skidmore, Donald C <donald.c.skidmore@intel.com> wrote: > > >> -----Original Message----- >> From: dan.streetman at canonical.com >> [mailto:dan.streetman at canonical.com] >> Sent: Monday, October 26, 2015 5:16 PM >> To: Kirsher, Jeffrey T >> Cc: Brandeburg, Jesse; Nelson, Shannon; Wyborny, Carolyn; Skidmore, >> Donald C; Vick, Matthew; Ronciak, John; Williams, Mitch A; intel-wired- >> lan at lists.osuosl.org; netdev at vger.kernel.org; linux-kernel at vger.kernel.org; >> Dan Streetman; Dan Streetman >> Subject: [PATCH] ixgbe: Wait for 1ms, not 1us, after RST >> >> From: Dan Streetman <dan.streetman@canonical.com> >> >> The driver currently waits 1us after issuing a RST, but the spec requires it to >> wait 1ms. >> >> Signed-off-by: Dan Streetman <dan.streetman@canonical.com> >> Signed-off-by: Dan Streetman <ddstreet@ieee.org> >> --- >> drivers/net/ethernet/intel/ixgbe/ixgbe_x540.c | 7 ++++++- >> 1 file changed, 6 insertions(+), 1 deletion(-) >> >> diff --git a/drivers/net/ethernet/intel/ixgbe/ixgbe_x540.c >> b/drivers/net/ethernet/intel/ixgbe/ixgbe_x540.c >> index 4e75843..147bc65 100644 >> --- a/drivers/net/ethernet/intel/ixgbe/ixgbe_x540.c >> +++ b/drivers/net/ethernet/intel/ixgbe/ixgbe_x540.c >> @@ -113,7 +113,12 @@ mac_reset_top: >> >> /* Poll for reset bit to self-clear indicating reset is complete */ >> for (i = 0; i < 10; i++) { >> - udelay(1); >> + /* sec 8.2.4.1.1 : >> + * programmers must wait approximately 1 ms after setting >> before >> + * attempting to check if the bit has cleared or to access >> (read >> + * or write) any other device register. >> + */ >> + mdelay(1); >> ctrl = IXGBE_READ_REG(hw, IXGBE_CTRL); >> if (!(ctrl & IXGBE_CTRL_RST_MASK)) >> break; >> -- >> 2.5.0 > > While the Data Sheet does mention that this should take ~ 1ms, we are in a busy wait state so it probably isn't that big of a deal to check more frequently for our exit condition. That said there are plenty of other delays later on in the reset path so keeping the udelay really isn't speeding things up much. :) I don't know the hw details of course, I was just going on the spec's use of "must" when stating how long the driver should wait before talking to the hw. If the hw doesn't actually care, then no need for this patch (although the spec should probably be changed to not use "must"). Thanks! > > Also normally it isn't a good idea to reference a section number in the data sheet as they do seem to change with updates. We are most likely a bit more safe here as it is one of the first of a list of register descriptions' and thus less like to move. > -- > To unsubscribe from this list: send the line "unsubscribe netdev" in > the body of a message to majordomo at vger.kernel.org > More majordomo info at http://vger.kernel.org/majordomo-info.html ^ permalink raw reply [flat|nested] 10+ messages in thread
* Re: [PATCH] ixgbe: Wait for 1ms, not 1us, after RST @ 2015-10-27 17:32 ` Dan Streetman 0 siblings, 0 replies; 10+ messages in thread From: Dan Streetman @ 2015-10-27 17:32 UTC (permalink / raw) To: Skidmore, Donald C Cc: Kirsher, Jeffrey T, Brandeburg, Jesse, Nelson, Shannon, Wyborny, Carolyn, Vick, Matthew, Ronciak, John, Williams, Mitch A, intel-wired-lan@lists.osuosl.org, netdev@vger.kernel.org, linux-kernel@vger.kernel.org, Dan Streetman On Tue, Oct 27, 2015 at 1:03 PM, Skidmore, Donald C <donald.c.skidmore@intel.com> wrote: > > >> -----Original Message----- >> From: dan.streetman@canonical.com >> [mailto:dan.streetman@canonical.com] >> Sent: Monday, October 26, 2015 5:16 PM >> To: Kirsher, Jeffrey T >> Cc: Brandeburg, Jesse; Nelson, Shannon; Wyborny, Carolyn; Skidmore, >> Donald C; Vick, Matthew; Ronciak, John; Williams, Mitch A; intel-wired- >> lan@lists.osuosl.org; netdev@vger.kernel.org; linux-kernel@vger.kernel.org; >> Dan Streetman; Dan Streetman >> Subject: [PATCH] ixgbe: Wait for 1ms, not 1us, after RST >> >> From: Dan Streetman <dan.streetman@canonical.com> >> >> The driver currently waits 1us after issuing a RST, but the spec requires it to >> wait 1ms. >> >> Signed-off-by: Dan Streetman <dan.streetman@canonical.com> >> Signed-off-by: Dan Streetman <ddstreet@ieee.org> >> --- >> drivers/net/ethernet/intel/ixgbe/ixgbe_x540.c | 7 ++++++- >> 1 file changed, 6 insertions(+), 1 deletion(-) >> >> diff --git a/drivers/net/ethernet/intel/ixgbe/ixgbe_x540.c >> b/drivers/net/ethernet/intel/ixgbe/ixgbe_x540.c >> index 4e75843..147bc65 100644 >> --- a/drivers/net/ethernet/intel/ixgbe/ixgbe_x540.c >> +++ b/drivers/net/ethernet/intel/ixgbe/ixgbe_x540.c >> @@ -113,7 +113,12 @@ mac_reset_top: >> >> /* Poll for reset bit to self-clear indicating reset is complete */ >> for (i = 0; i < 10; i++) { >> - udelay(1); >> + /* sec 8.2.4.1.1 : >> + * programmers must wait approximately 1 ms after setting >> before >> + * attempting to check if the bit has cleared or to access >> (read >> + * or write) any other device register. >> + */ >> + mdelay(1); >> ctrl = IXGBE_READ_REG(hw, IXGBE_CTRL); >> if (!(ctrl & IXGBE_CTRL_RST_MASK)) >> break; >> -- >> 2.5.0 > > While the Data Sheet does mention that this should take ~ 1ms, we are in a busy wait state so it probably isn't that big of a deal to check more frequently for our exit condition. That said there are plenty of other delays later on in the reset path so keeping the udelay really isn't speeding things up much. :) I don't know the hw details of course, I was just going on the spec's use of "must" when stating how long the driver should wait before talking to the hw. If the hw doesn't actually care, then no need for this patch (although the spec should probably be changed to not use "must"). Thanks! > > Also normally it isn't a good idea to reference a section number in the data sheet as they do seem to change with updates. We are most likely a bit more safe here as it is one of the first of a list of register descriptions' and thus less like to move. > -- > To unsubscribe from this list: send the line "unsubscribe netdev" in > the body of a message to majordomo@vger.kernel.org > More majordomo info at http://vger.kernel.org/majordomo-info.html ^ permalink raw reply [flat|nested] 10+ messages in thread
* [Intel-wired-lan] [PATCH] ixgbe: Wait for 1ms, not 1us, after RST 2015-10-27 0:16 ` dan.streetman @ 2015-10-27 17:57 ` Peter Hurley -1 siblings, 0 replies; 10+ messages in thread From: Peter Hurley @ 2015-10-27 17:57 UTC (permalink / raw) To: intel-wired-lan Hi Dan, On 10/26/2015 08:16 PM, dan.streetman at canonical.com wrote: > From: Dan Streetman <dan.streetman@canonical.com> > > The driver currently waits 1us after issuing a RST, but the spec > requires it to wait 1ms. > > Signed-off-by: Dan Streetman <dan.streetman@canonical.com> > Signed-off-by: Dan Streetman <ddstreet@ieee.org> > --- > drivers/net/ethernet/intel/ixgbe/ixgbe_x540.c | 7 ++++++- > 1 file changed, 6 insertions(+), 1 deletion(-) > > diff --git a/drivers/net/ethernet/intel/ixgbe/ixgbe_x540.c b/drivers/net/ethernet/intel/ixgbe/ixgbe_x540.c > index 4e75843..147bc65 100644 > --- a/drivers/net/ethernet/intel/ixgbe/ixgbe_x540.c > +++ b/drivers/net/ethernet/intel/ixgbe/ixgbe_x540.c > @@ -113,7 +113,12 @@ mac_reset_top: > > /* Poll for reset bit to self-clear indicating reset is complete */ > for (i = 0; i < 10; i++) { > - udelay(1); > + /* sec 8.2.4.1.1 : > + * programmers must wait approximately 1 ms after setting before > + * attempting to check if the bit has cleared or to access (read > + * or write) any other device register. > + */ > + mdelay(1); Since ixgbe_reset_hw_x540() goes on to msleep(100) immediately after this busy-wait loop, this should instead be: msleep(1); Regards, Peter Hurley > ctrl = IXGBE_READ_REG(hw, IXGBE_CTRL); > if (!(ctrl & IXGBE_CTRL_RST_MASK)) > break; > ^ permalink raw reply [flat|nested] 10+ messages in thread
* Re: [PATCH] ixgbe: Wait for 1ms, not 1us, after RST @ 2015-10-27 17:57 ` Peter Hurley 0 siblings, 0 replies; 10+ messages in thread From: Peter Hurley @ 2015-10-27 17:57 UTC (permalink / raw) To: dan.streetman, Jeff Kirsher Cc: Jesse Brandeburg, Shannon Nelson, Carolyn Wyborny, Don Skidmore, Matthew Vick, John Ronciak, Mitch Williams, intel-wired-lan, netdev, linux-kernel, Dan Streetman Hi Dan, On 10/26/2015 08:16 PM, dan.streetman@canonical.com wrote: > From: Dan Streetman <dan.streetman@canonical.com> > > The driver currently waits 1us after issuing a RST, but the spec > requires it to wait 1ms. > > Signed-off-by: Dan Streetman <dan.streetman@canonical.com> > Signed-off-by: Dan Streetman <ddstreet@ieee.org> > --- > drivers/net/ethernet/intel/ixgbe/ixgbe_x540.c | 7 ++++++- > 1 file changed, 6 insertions(+), 1 deletion(-) > > diff --git a/drivers/net/ethernet/intel/ixgbe/ixgbe_x540.c b/drivers/net/ethernet/intel/ixgbe/ixgbe_x540.c > index 4e75843..147bc65 100644 > --- a/drivers/net/ethernet/intel/ixgbe/ixgbe_x540.c > +++ b/drivers/net/ethernet/intel/ixgbe/ixgbe_x540.c > @@ -113,7 +113,12 @@ mac_reset_top: > > /* Poll for reset bit to self-clear indicating reset is complete */ > for (i = 0; i < 10; i++) { > - udelay(1); > + /* sec 8.2.4.1.1 : > + * programmers must wait approximately 1 ms after setting before > + * attempting to check if the bit has cleared or to access (read > + * or write) any other device register. > + */ > + mdelay(1); Since ixgbe_reset_hw_x540() goes on to msleep(100) immediately after this busy-wait loop, this should instead be: msleep(1); Regards, Peter Hurley > ctrl = IXGBE_READ_REG(hw, IXGBE_CTRL); > if (!(ctrl & IXGBE_CTRL_RST_MASK)) > break; > ^ permalink raw reply [flat|nested] 10+ messages in thread
* [Intel-wired-lan] [PATCHv2] ixgbe: Wait for 1ms, not 1us, after RST 2015-10-27 17:57 ` Peter Hurley @ 2015-10-27 18:27 ` Dan Streetman -1 siblings, 0 replies; 10+ messages in thread From: Dan Streetman @ 2015-10-27 18:27 UTC (permalink / raw) To: intel-wired-lan The driver currently waits 1us after issuing a RST, but the spec requires it to wait 1ms. This adds a msleep(1) before polling the reset bit. Signed-off-by: Dan Streetman <dan.streetman@canonical.com> Signed-off-by: Dan Streetman <ddstreet@ieee.org> --- changes since v1: use msleep(1) instead of mdelay(1), per Peter Hurley move msleep(1) out of for loop - only msleep once, leave udelay(1) inside for loop use spec sec title instead of number, per Don Skidmore drivers/net/ethernet/intel/ixgbe/ixgbe_x540.c | 7 +++++++ 1 file changed, 7 insertions(+) diff --git a/drivers/net/ethernet/intel/ixgbe/ixgbe_x540.c b/drivers/net/ethernet/intel/ixgbe/ixgbe_x540.c index 4e75843..02cfa1e 100644 --- a/drivers/net/ethernet/intel/ixgbe/ixgbe_x540.c +++ b/drivers/net/ethernet/intel/ixgbe/ixgbe_x540.c @@ -111,6 +111,13 @@ mac_reset_top: IXGBE_WRITE_REG(hw, IXGBE_CTRL, ctrl); IXGBE_WRITE_FLUSH(hw); + /* From the spec "General Control Registers - Device Control Register": + * "...programmers must wait approximately 1 ms after setting before + * attempting to check if the bit has cleared or to access (read + * or write) any other device register." + */ + msleep(1); + /* Poll for reset bit to self-clear indicating reset is complete */ for (i = 0; i < 10; i++) { udelay(1); -- 2.5.0 ^ permalink raw reply related [flat|nested] 10+ messages in thread
* [PATCHv2] ixgbe: Wait for 1ms, not 1us, after RST @ 2015-10-27 18:27 ` Dan Streetman 0 siblings, 0 replies; 10+ messages in thread From: Dan Streetman @ 2015-10-27 18:27 UTC (permalink / raw) To: Peter Hurley, Don Skidmore, Jeff Kirsher Cc: Jesse Brandeburg, Shannon Nelson, Carolyn Wyborny, Matthew Vick, John Ronciak, Mitch Williams, intel-wired-lan, netdev, linux-kernel, Dan Streetman, Dan Streetman The driver currently waits 1us after issuing a RST, but the spec requires it to wait 1ms. This adds a msleep(1) before polling the reset bit. Signed-off-by: Dan Streetman <dan.streetman@canonical.com> Signed-off-by: Dan Streetman <ddstreet@ieee.org> --- changes since v1: use msleep(1) instead of mdelay(1), per Peter Hurley move msleep(1) out of for loop - only msleep once, leave udelay(1) inside for loop use spec sec title instead of number, per Don Skidmore drivers/net/ethernet/intel/ixgbe/ixgbe_x540.c | 7 +++++++ 1 file changed, 7 insertions(+) diff --git a/drivers/net/ethernet/intel/ixgbe/ixgbe_x540.c b/drivers/net/ethernet/intel/ixgbe/ixgbe_x540.c index 4e75843..02cfa1e 100644 --- a/drivers/net/ethernet/intel/ixgbe/ixgbe_x540.c +++ b/drivers/net/ethernet/intel/ixgbe/ixgbe_x540.c @@ -111,6 +111,13 @@ mac_reset_top: IXGBE_WRITE_REG(hw, IXGBE_CTRL, ctrl); IXGBE_WRITE_FLUSH(hw); + /* From the spec "General Control Registers - Device Control Register": + * "...programmers must wait approximately 1 ms after setting before + * attempting to check if the bit has cleared or to access (read + * or write) any other device register." + */ + msleep(1); + /* Poll for reset bit to self-clear indicating reset is complete */ for (i = 0; i < 10; i++) { udelay(1); -- 2.5.0 ^ permalink raw reply related [flat|nested] 10+ messages in thread
end of thread, other threads:[~2015-10-27 18:28 UTC | newest] Thread overview: 10+ messages (download: mbox.gz follow: Atom feed -- links below jump to the message on this page -- 2015-10-27 0:16 [Intel-wired-lan] [PATCH] ixgbe: Wait for 1ms, not 1us, after RST dan.streetman 2015-10-27 0:16 ` dan.streetman 2015-10-27 17:03 ` [Intel-wired-lan] " Skidmore, Donald C 2015-10-27 17:03 ` Skidmore, Donald C 2015-10-27 17:32 ` [Intel-wired-lan] " Dan Streetman 2015-10-27 17:32 ` Dan Streetman 2015-10-27 17:57 ` [Intel-wired-lan] " Peter Hurley 2015-10-27 17:57 ` Peter Hurley 2015-10-27 18:27 ` [Intel-wired-lan] [PATCHv2] " Dan Streetman 2015-10-27 18:27 ` Dan Streetman
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