* [PATCH V3 2/2] arm64: bpf: make BPF prologue and epilogue align with ARM64 AAPCS [not found] <CABg9mct-hnEhvT6y9ZgCC8nMan5YbmByQa_ViUWzeea6ToqG4A@mail.gmail.com> @ 2015-11-13 18:09 ` Yang Shi 0 siblings, 0 replies; 19+ messages in thread From: Yang Shi @ 2015-11-13 18:09 UTC (permalink / raw) To: linux-arm-kernel Save and restore FP/LR in BPF prog prologue and epilogue, save SP to FP in prologue in order to get the correct stack backtrace. However, ARM64 JIT used FP (x29) as eBPF fp register, FP is subjected to change during function call so it may cause the BPF prog stack base address change too. Use x25 to replace FP as BPF stack base register (fp). Since x25 is callee saved register, so it will keep intact during function call. It is initialized in BPF prog prologue when BPF prog is started to run everytime. When BPF prog exits, it could be just tossed. So, the BPF stack layout looks like: high original A64_SP => 0:+-----+ BPF prologue |FP/LR| current A64_FP => -16:+-----+ | ... | callee saved registers BPF fp register => -64:+-----+ | | | ... | BPF prog stack | | | | current A64_SP => +-----+ | | | ... | Function call stack | | +-----+ low CC: Zi Shen Lim <zlim.lnx@gmail.com> CC: Xi Wang <xi.wang@gmail.com> Signed-off-by: Yang Shi <yang.shi@linaro.org> --- V3 --> V2: * Make FP point to FP' * Fix a compile warning arch/arm64/net/bpf_jit_comp.c | 37 +++++++++++++++++++++++++++++++------ 1 file changed, 31 insertions(+), 6 deletions(-) diff --git a/arch/arm64/net/bpf_jit_comp.c b/arch/arm64/net/bpf_jit_comp.c index ac8b548..c131e38 100644 --- a/arch/arm64/net/bpf_jit_comp.c +++ b/arch/arm64/net/bpf_jit_comp.c @@ -50,7 +50,7 @@ static const int bpf2a64[] = { [BPF_REG_8] = A64_R(21), [BPF_REG_9] = A64_R(22), /* read-only frame pointer to access stack */ - [BPF_REG_FP] = A64_FP, + [BPF_REG_FP] = A64_R(25), /* temporary register for internal BPF JIT */ [TMP_REG_1] = A64_R(23), [TMP_REG_2] = A64_R(24), @@ -155,16 +155,42 @@ static void build_prologue(struct jit_ctx *ctx) stack_size += 4; /* extra for skb_copy_bits buffer */ stack_size = STACK_ALIGN(stack_size); + /* + * BPF prog stack layout + * + * high + * original A64_SP => 0:+-----+ BPF prologue + * |FP/LR| + * current A64_FP => -16:+-----+ + * | ... | callee saved registers + * BPF fp register => -64:+-----+ + * | | + * | ... | BPF prog stack + * | | + * | | + * current A64_SP => +-----+ + * | | + * | ... | Function call stack + * | | + * +-----+ + * low + * + */ + + /* Save FP and LR registers to stay align with ARM64 AAPCS */ + emit(A64_PUSH(A64_FP, A64_LR, A64_SP), ctx); + emit(A64_MOV(1, A64_FP, A64_SP), ctx); + /* Save callee-saved register */ emit(A64_PUSH(r6, r7, A64_SP), ctx); emit(A64_PUSH(r8, r9, A64_SP), ctx); if (ctx->tmp_used) emit(A64_PUSH(tmp1, tmp2, A64_SP), ctx); - /* Set up frame pointer */ + /* Set up BPF prog stack base register (x25) */ emit(A64_MOV(1, fp, A64_SP), ctx); - /* Set up BPF stack */ + /* Set up function call stack */ emit(A64_SUB_I(1, A64_SP, A64_SP, stack_size), ctx); /* Clear registers A and X */ @@ -179,7 +205,6 @@ static void build_epilogue(struct jit_ctx *ctx) const u8 r7 = bpf2a64[BPF_REG_7]; const u8 r8 = bpf2a64[BPF_REG_8]; const u8 r9 = bpf2a64[BPF_REG_9]; - const u8 fp = bpf2a64[BPF_REG_FP]; const u8 tmp1 = bpf2a64[TMP_REG_1]; const u8 tmp2 = bpf2a64[TMP_REG_2]; int stack_size = MAX_BPF_STACK; @@ -196,8 +221,8 @@ static void build_epilogue(struct jit_ctx *ctx) emit(A64_POP(r8, r9, A64_SP), ctx); emit(A64_POP(r6, r7, A64_SP), ctx); - /* Restore frame pointer */ - emit(A64_MOV(1, fp, A64_SP), ctx); + /* Restore FP/LR registers */ + emit(A64_POP(A64_FP, A64_LR, A64_SP), ctx); /* Set return value */ emit(A64_MOV(1, A64_R(0), r0), ctx); -- 2.0.2 ^ permalink raw reply related [flat|nested] 19+ messages in thread
* [PATCH V3 2/2] arm64: bpf: make BPF prologue and epilogue align with ARM64 AAPCS @ 2015-11-13 18:09 ` Yang Shi 0 siblings, 0 replies; 19+ messages in thread From: Yang Shi @ 2015-11-13 18:09 UTC (permalink / raw) To: ast, daniel, catalin.marinas, will.deacon Cc: zlim.lnx, xi.wang, linux-kernel, netdev, linux-arm-kernel, linaro-kernel, yang.shi Save and restore FP/LR in BPF prog prologue and epilogue, save SP to FP in prologue in order to get the correct stack backtrace. However, ARM64 JIT used FP (x29) as eBPF fp register, FP is subjected to change during function call so it may cause the BPF prog stack base address change too. Use x25 to replace FP as BPF stack base register (fp). Since x25 is callee saved register, so it will keep intact during function call. It is initialized in BPF prog prologue when BPF prog is started to run everytime. When BPF prog exits, it could be just tossed. So, the BPF stack layout looks like: high original A64_SP => 0:+-----+ BPF prologue |FP/LR| current A64_FP => -16:+-----+ | ... | callee saved registers BPF fp register => -64:+-----+ | | | ... | BPF prog stack | | | | current A64_SP => +-----+ | | | ... | Function call stack | | +-----+ low CC: Zi Shen Lim <zlim.lnx@gmail.com> CC: Xi Wang <xi.wang@gmail.com> Signed-off-by: Yang Shi <yang.shi@linaro.org> --- V3 --> V2: * Make FP point to FP' * Fix a compile warning arch/arm64/net/bpf_jit_comp.c | 37 +++++++++++++++++++++++++++++++------ 1 file changed, 31 insertions(+), 6 deletions(-) diff --git a/arch/arm64/net/bpf_jit_comp.c b/arch/arm64/net/bpf_jit_comp.c index ac8b548..c131e38 100644 --- a/arch/arm64/net/bpf_jit_comp.c +++ b/arch/arm64/net/bpf_jit_comp.c @@ -50,7 +50,7 @@ static const int bpf2a64[] = { [BPF_REG_8] = A64_R(21), [BPF_REG_9] = A64_R(22), /* read-only frame pointer to access stack */ - [BPF_REG_FP] = A64_FP, + [BPF_REG_FP] = A64_R(25), /* temporary register for internal BPF JIT */ [TMP_REG_1] = A64_R(23), [TMP_REG_2] = A64_R(24), @@ -155,16 +155,42 @@ static void build_prologue(struct jit_ctx *ctx) stack_size += 4; /* extra for skb_copy_bits buffer */ stack_size = STACK_ALIGN(stack_size); + /* + * BPF prog stack layout + * + * high + * original A64_SP => 0:+-----+ BPF prologue + * |FP/LR| + * current A64_FP => -16:+-----+ + * | ... | callee saved registers + * BPF fp register => -64:+-----+ + * | | + * | ... | BPF prog stack + * | | + * | | + * current A64_SP => +-----+ + * | | + * | ... | Function call stack + * | | + * +-----+ + * low + * + */ + + /* Save FP and LR registers to stay align with ARM64 AAPCS */ + emit(A64_PUSH(A64_FP, A64_LR, A64_SP), ctx); + emit(A64_MOV(1, A64_FP, A64_SP), ctx); + /* Save callee-saved register */ emit(A64_PUSH(r6, r7, A64_SP), ctx); emit(A64_PUSH(r8, r9, A64_SP), ctx); if (ctx->tmp_used) emit(A64_PUSH(tmp1, tmp2, A64_SP), ctx); - /* Set up frame pointer */ + /* Set up BPF prog stack base register (x25) */ emit(A64_MOV(1, fp, A64_SP), ctx); - /* Set up BPF stack */ + /* Set up function call stack */ emit(A64_SUB_I(1, A64_SP, A64_SP, stack_size), ctx); /* Clear registers A and X */ @@ -179,7 +205,6 @@ static void build_epilogue(struct jit_ctx *ctx) const u8 r7 = bpf2a64[BPF_REG_7]; const u8 r8 = bpf2a64[BPF_REG_8]; const u8 r9 = bpf2a64[BPF_REG_9]; - const u8 fp = bpf2a64[BPF_REG_FP]; const u8 tmp1 = bpf2a64[TMP_REG_1]; const u8 tmp2 = bpf2a64[TMP_REG_2]; int stack_size = MAX_BPF_STACK; @@ -196,8 +221,8 @@ static void build_epilogue(struct jit_ctx *ctx) emit(A64_POP(r8, r9, A64_SP), ctx); emit(A64_POP(r6, r7, A64_SP), ctx); - /* Restore frame pointer */ - emit(A64_MOV(1, fp, A64_SP), ctx); + /* Restore FP/LR registers */ + emit(A64_POP(A64_FP, A64_LR, A64_SP), ctx); /* Set return value */ emit(A64_MOV(1, A64_R(0), r0), ctx); -- 2.0.2 ^ permalink raw reply related [flat|nested] 19+ messages in thread
* [PATCH V3 2/2] arm64: bpf: make BPF prologue and epilogue align with ARM64 AAPCS 2015-11-13 18:09 ` Yang Shi (?) @ 2015-11-14 2:39 ` Z Lim -1 siblings, 0 replies; 19+ messages in thread From: Z Lim @ 2015-11-14 2:39 UTC (permalink / raw) To: linux-arm-kernel Yang, I noticed another thing... On Fri, Nov 13, 2015 at 10:09 AM, Yang Shi <yang.shi@linaro.org> wrote: > Save and restore FP/LR in BPF prog prologue and epilogue, save SP to FP > in prologue in order to get the correct stack backtrace. > > However, ARM64 JIT used FP (x29) as eBPF fp register, FP is subjected to > change during function call so it may cause the BPF prog stack base address > change too. > > Use x25 to replace FP as BPF stack base register (fp). Since x25 is callee > saved register, so it will keep intact during function call. Can you please add save/restore for x25 also? :) > It is initialized in BPF prog prologue when BPF prog is started to run > everytime. When BPF prog exits, it could be just tossed. > ^ permalink raw reply [flat|nested] 19+ messages in thread
* Re: [PATCH V3 2/2] arm64: bpf: make BPF prologue and epilogue align with ARM64 AAPCS @ 2015-11-14 2:39 ` Z Lim 0 siblings, 0 replies; 19+ messages in thread From: Z Lim @ 2015-11-14 2:39 UTC (permalink / raw) To: Yang Shi Cc: linaro-kernel, Daniel Borkmann, Catalin Marinas, Will Deacon, Alexei Starovoitov, LKML, linux-arm-kernel@lists.infradead.org, Network Development, Xi Wang Yang, I noticed another thing... On Fri, Nov 13, 2015 at 10:09 AM, Yang Shi <yang.shi@linaro.org> wrote: > Save and restore FP/LR in BPF prog prologue and epilogue, save SP to FP > in prologue in order to get the correct stack backtrace. > > However, ARM64 JIT used FP (x29) as eBPF fp register, FP is subjected to > change during function call so it may cause the BPF prog stack base address > change too. > > Use x25 to replace FP as BPF stack base register (fp). Since x25 is callee > saved register, so it will keep intact during function call. Can you please add save/restore for x25 also? :) > It is initialized in BPF prog prologue when BPF prog is started to run > everytime. When BPF prog exits, it could be just tossed. > ^ permalink raw reply [flat|nested] 19+ messages in thread
* Re: [PATCH V3 2/2] arm64: bpf: make BPF prologue and epilogue align with ARM64 AAPCS @ 2015-11-14 2:39 ` Z Lim 0 siblings, 0 replies; 19+ messages in thread From: Z Lim @ 2015-11-14 2:39 UTC (permalink / raw) To: Yang Shi Cc: Alexei Starovoitov, Daniel Borkmann, Catalin Marinas, Will Deacon, Xi Wang, LKML, Network Development, linux-arm-kernel@lists.infradead.org, linaro-kernel Yang, I noticed another thing... On Fri, Nov 13, 2015 at 10:09 AM, Yang Shi <yang.shi@linaro.org> wrote: > Save and restore FP/LR in BPF prog prologue and epilogue, save SP to FP > in prologue in order to get the correct stack backtrace. > > However, ARM64 JIT used FP (x29) as eBPF fp register, FP is subjected to > change during function call so it may cause the BPF prog stack base address > change too. > > Use x25 to replace FP as BPF stack base register (fp). Since x25 is callee > saved register, so it will keep intact during function call. Can you please add save/restore for x25 also? :) > It is initialized in BPF prog prologue when BPF prog is started to run > everytime. When BPF prog exits, it could be just tossed. > ^ permalink raw reply [flat|nested] 19+ messages in thread
* [PATCH V3 2/2] arm64: bpf: make BPF prologue and epilogue align with ARM64 AAPCS 2015-11-14 2:39 ` Z Lim @ 2015-11-16 19:48 ` Shi, Yang -1 siblings, 0 replies; 19+ messages in thread From: Shi, Yang @ 2015-11-16 19:48 UTC (permalink / raw) To: linux-arm-kernel On 11/13/2015 6:39 PM, Z Lim wrote: > Yang, I noticed another thing... > > On Fri, Nov 13, 2015 at 10:09 AM, Yang Shi <yang.shi@linaro.org> wrote: >> Save and restore FP/LR in BPF prog prologue and epilogue, save SP to FP >> in prologue in order to get the correct stack backtrace. >> >> However, ARM64 JIT used FP (x29) as eBPF fp register, FP is subjected to >> change during function call so it may cause the BPF prog stack base address >> change too. >> >> Use x25 to replace FP as BPF stack base register (fp). Since x25 is callee >> saved register, so it will keep intact during function call. > > Can you please add save/restore for x25 also? :) Sure. BTW, since PUSH invokes stp instruction and SP need 16-bytes alignment, so we have to save x26 with x25 together. Anyway, it won't introduce any harm overhead since one instruction saves two registers. Yang > >> It is initialized in BPF prog prologue when BPF prog is started to run >> everytime. When BPF prog exits, it could be just tossed. >> ^ permalink raw reply [flat|nested] 19+ messages in thread
* Re: [PATCH V3 2/2] arm64: bpf: make BPF prologue and epilogue align with ARM64 AAPCS @ 2015-11-16 19:48 ` Shi, Yang 0 siblings, 0 replies; 19+ messages in thread From: Shi, Yang @ 2015-11-16 19:48 UTC (permalink / raw) To: Z Lim Cc: Alexei Starovoitov, Daniel Borkmann, Catalin Marinas, Will Deacon, Xi Wang, LKML, Network Development, linux-arm-kernel@lists.infradead.org, linaro-kernel On 11/13/2015 6:39 PM, Z Lim wrote: > Yang, I noticed another thing... > > On Fri, Nov 13, 2015 at 10:09 AM, Yang Shi <yang.shi@linaro.org> wrote: >> Save and restore FP/LR in BPF prog prologue and epilogue, save SP to FP >> in prologue in order to get the correct stack backtrace. >> >> However, ARM64 JIT used FP (x29) as eBPF fp register, FP is subjected to >> change during function call so it may cause the BPF prog stack base address >> change too. >> >> Use x25 to replace FP as BPF stack base register (fp). Since x25 is callee >> saved register, so it will keep intact during function call. > > Can you please add save/restore for x25 also? :) Sure. BTW, since PUSH invokes stp instruction and SP need 16-bytes alignment, so we have to save x26 with x25 together. Anyway, it won't introduce any harm overhead since one instruction saves two registers. Yang > >> It is initialized in BPF prog prologue when BPF prog is started to run >> everytime. When BPF prog exits, it could be just tossed. >> ^ permalink raw reply [flat|nested] 19+ messages in thread
* [PATCH V4 2/2] arm64: bpf: make BPF prologue and epilogue align with ARM64 AAPCS 2015-11-14 2:39 ` Z Lim @ 2015-11-16 22:35 ` Yang Shi -1 siblings, 0 replies; 19+ messages in thread From: Yang Shi @ 2015-11-16 22:35 UTC (permalink / raw) To: linux-arm-kernel Save and restore FP/LR in BPF prog prologue and epilogue, save SP to FP in prologue in order to get the correct stack backtrace. However, ARM64 JIT used FP (x29) as eBPF fp register, FP is subjected to change during function call so it may cause the BPF prog stack base address change too. Use x25 to replace FP as BPF stack base register (fp). Since x25 is callee saved register, so it will keep intact during function call. It is initialized in BPF prog prologue when BPF prog is started to run everytime. Save and restore x25/x26 in BPF prologue and epilogue to keep them intact for the outside of BPF. Actually, x26 is unnecessary, but SP requires 16 bytes alignment. So, the BPF stack layout looks like: high original A64_SP => 0:+-----+ BPF prologue |FP/LR| current A64_FP => -16:+-----+ | ... | callee saved registers +-----+ | | x25/x26 BPF fp register => -80:+-----+ | | | ... | BPF prog stack | | | | current A64_SP => +-----+ | | | ... | Function call stack | | +-----+ low CC: Zi Shen Lim <zlim.lnx@gmail.com> CC: Xi Wang <xi.wang@gmail.com> Signed-off-by: Yang Shi <yang.shi@linaro.org> --- V4 --> V3: * Save/restore x25 and x26 V3 --> V2: * Make FP point to FP' * Fix a compile warning arch/arm64/net/bpf_jit_comp.c | 44 ++++++++++++++++++++++++++++++++++++++----- 1 file changed, 39 insertions(+), 5 deletions(-) diff --git a/arch/arm64/net/bpf_jit_comp.c b/arch/arm64/net/bpf_jit_comp.c index ac8b548..86a3253 100644 --- a/arch/arm64/net/bpf_jit_comp.c +++ b/arch/arm64/net/bpf_jit_comp.c @@ -50,7 +50,7 @@ static const int bpf2a64[] = { [BPF_REG_8] = A64_R(21), [BPF_REG_9] = A64_R(22), /* read-only frame pointer to access stack */ - [BPF_REG_FP] = A64_FP, + [BPF_REG_FP] = A64_R(25), /* temporary register for internal BPF JIT */ [TMP_REG_1] = A64_R(23), [TMP_REG_2] = A64_R(24), @@ -155,16 +155,47 @@ static void build_prologue(struct jit_ctx *ctx) stack_size += 4; /* extra for skb_copy_bits buffer */ stack_size = STACK_ALIGN(stack_size); + /* + * BPF prog stack layout + * + * high + * original A64_SP => 0:+-----+ BPF prologue + * |FP/LR| + * current A64_FP => -16:+-----+ + * | ... | callee saved registers + * +-----+ + * | | x25/x26 + * BPF fp register => -80:+-----+ + * | | + * | ... | BPF prog stack + * | | + * | | + * current A64_SP => +-----+ + * | | + * | ... | Function call stack + * | | + * +-----+ + * low + * + */ + + /* Save FP and LR registers to stay align with ARM64 AAPCS */ + emit(A64_PUSH(A64_FP, A64_LR, A64_SP), ctx); + emit(A64_MOV(1, A64_FP, A64_SP), ctx); + /* Save callee-saved register */ emit(A64_PUSH(r6, r7, A64_SP), ctx); emit(A64_PUSH(r8, r9, A64_SP), ctx); if (ctx->tmp_used) emit(A64_PUSH(tmp1, tmp2, A64_SP), ctx); - /* Set up frame pointer */ + /* Save fp (x25) and x26. SP requires 16 bytes alignment */ + emit(A64_PUSH(fp, A64_R(26), A64_SP), ctx); + + /* Set up BPF prog stack base register (x25) */ emit(A64_MOV(1, fp, A64_SP), ctx); - /* Set up BPF stack */ + /* Set up function call stack */ emit(A64_SUB_I(1, A64_SP, A64_SP, stack_size), ctx); /* Clear registers A and X */ @@ -190,14 +221,17 @@ static void build_epilogue(struct jit_ctx *ctx) /* We're done with BPF stack */ emit(A64_ADD_I(1, A64_SP, A64_SP, stack_size), ctx); + /* Restore fs (x25) and x26 */ + emit(A64_POP(fp, A64_R(26), A64_SP), ctx); + /* Restore callee-saved register */ if (ctx->tmp_used) emit(A64_POP(tmp1, tmp2, A64_SP), ctx); emit(A64_POP(r8, r9, A64_SP), ctx); emit(A64_POP(r6, r7, A64_SP), ctx); - /* Restore frame pointer */ - emit(A64_MOV(1, fp, A64_SP), ctx); + /* Restore FP/LR registers */ + emit(A64_POP(A64_FP, A64_LR, A64_SP), ctx); /* Set return value */ emit(A64_MOV(1, A64_R(0), r0), ctx); -- 2.0.2 ^ permalink raw reply related [flat|nested] 19+ messages in thread
* [PATCH V4 2/2] arm64: bpf: make BPF prologue and epilogue align with ARM64 AAPCS @ 2015-11-16 22:35 ` Yang Shi 0 siblings, 0 replies; 19+ messages in thread From: Yang Shi @ 2015-11-16 22:35 UTC (permalink / raw) To: ast, daniel, catalin.marinas, will.deacon, davem Cc: zlim.lnx, xi.wang, linux-kernel, netdev, linux-arm-kernel, linaro-kernel, yang.shi Save and restore FP/LR in BPF prog prologue and epilogue, save SP to FP in prologue in order to get the correct stack backtrace. However, ARM64 JIT used FP (x29) as eBPF fp register, FP is subjected to change during function call so it may cause the BPF prog stack base address change too. Use x25 to replace FP as BPF stack base register (fp). Since x25 is callee saved register, so it will keep intact during function call. It is initialized in BPF prog prologue when BPF prog is started to run everytime. Save and restore x25/x26 in BPF prologue and epilogue to keep them intact for the outside of BPF. Actually, x26 is unnecessary, but SP requires 16 bytes alignment. So, the BPF stack layout looks like: high original A64_SP => 0:+-----+ BPF prologue |FP/LR| current A64_FP => -16:+-----+ | ... | callee saved registers +-----+ | | x25/x26 BPF fp register => -80:+-----+ | | | ... | BPF prog stack | | | | current A64_SP => +-----+ | | | ... | Function call stack | | +-----+ low CC: Zi Shen Lim <zlim.lnx@gmail.com> CC: Xi Wang <xi.wang@gmail.com> Signed-off-by: Yang Shi <yang.shi@linaro.org> --- V4 --> V3: * Save/restore x25 and x26 V3 --> V2: * Make FP point to FP' * Fix a compile warning arch/arm64/net/bpf_jit_comp.c | 44 ++++++++++++++++++++++++++++++++++++++----- 1 file changed, 39 insertions(+), 5 deletions(-) diff --git a/arch/arm64/net/bpf_jit_comp.c b/arch/arm64/net/bpf_jit_comp.c index ac8b548..86a3253 100644 --- a/arch/arm64/net/bpf_jit_comp.c +++ b/arch/arm64/net/bpf_jit_comp.c @@ -50,7 +50,7 @@ static const int bpf2a64[] = { [BPF_REG_8] = A64_R(21), [BPF_REG_9] = A64_R(22), /* read-only frame pointer to access stack */ - [BPF_REG_FP] = A64_FP, + [BPF_REG_FP] = A64_R(25), /* temporary register for internal BPF JIT */ [TMP_REG_1] = A64_R(23), [TMP_REG_2] = A64_R(24), @@ -155,16 +155,47 @@ static void build_prologue(struct jit_ctx *ctx) stack_size += 4; /* extra for skb_copy_bits buffer */ stack_size = STACK_ALIGN(stack_size); + /* + * BPF prog stack layout + * + * high + * original A64_SP => 0:+-----+ BPF prologue + * |FP/LR| + * current A64_FP => -16:+-----+ + * | ... | callee saved registers + * +-----+ + * | | x25/x26 + * BPF fp register => -80:+-----+ + * | | + * | ... | BPF prog stack + * | | + * | | + * current A64_SP => +-----+ + * | | + * | ... | Function call stack + * | | + * +-----+ + * low + * + */ + + /* Save FP and LR registers to stay align with ARM64 AAPCS */ + emit(A64_PUSH(A64_FP, A64_LR, A64_SP), ctx); + emit(A64_MOV(1, A64_FP, A64_SP), ctx); + /* Save callee-saved register */ emit(A64_PUSH(r6, r7, A64_SP), ctx); emit(A64_PUSH(r8, r9, A64_SP), ctx); if (ctx->tmp_used) emit(A64_PUSH(tmp1, tmp2, A64_SP), ctx); - /* Set up frame pointer */ + /* Save fp (x25) and x26. SP requires 16 bytes alignment */ + emit(A64_PUSH(fp, A64_R(26), A64_SP), ctx); + + /* Set up BPF prog stack base register (x25) */ emit(A64_MOV(1, fp, A64_SP), ctx); - /* Set up BPF stack */ + /* Set up function call stack */ emit(A64_SUB_I(1, A64_SP, A64_SP, stack_size), ctx); /* Clear registers A and X */ @@ -190,14 +221,17 @@ static void build_epilogue(struct jit_ctx *ctx) /* We're done with BPF stack */ emit(A64_ADD_I(1, A64_SP, A64_SP, stack_size), ctx); + /* Restore fs (x25) and x26 */ + emit(A64_POP(fp, A64_R(26), A64_SP), ctx); + /* Restore callee-saved register */ if (ctx->tmp_used) emit(A64_POP(tmp1, tmp2, A64_SP), ctx); emit(A64_POP(r8, r9, A64_SP), ctx); emit(A64_POP(r6, r7, A64_SP), ctx); - /* Restore frame pointer */ - emit(A64_MOV(1, fp, A64_SP), ctx); + /* Restore FP/LR registers */ + emit(A64_POP(A64_FP, A64_LR, A64_SP), ctx); /* Set return value */ emit(A64_MOV(1, A64_R(0), r0), ctx); -- 2.0.2 ^ permalink raw reply related [flat|nested] 19+ messages in thread
* [PATCH V4 2/2] arm64: bpf: make BPF prologue and epilogue align with ARM64 AAPCS 2015-11-16 22:35 ` Yang Shi @ 2015-11-17 4:37 ` Z Lim -1 siblings, 0 replies; 19+ messages in thread From: Z Lim @ 2015-11-17 4:37 UTC (permalink / raw) To: linux-arm-kernel On Mon, Nov 16, 2015 at 2:35 PM, Yang Shi <yang.shi@linaro.org> wrote: > Save and restore FP/LR in BPF prog prologue and epilogue, save SP to FP > in prologue in order to get the correct stack backtrace. > > However, ARM64 JIT used FP (x29) as eBPF fp register, FP is subjected to > change during function call so it may cause the BPF prog stack base address > change too. > > Use x25 to replace FP as BPF stack base register (fp). Since x25 is callee > saved register, so it will keep intact during function call. > It is initialized in BPF prog prologue when BPF prog is started to run > everytime. Save and restore x25/x26 in BPF prologue and epilogue to keep > them intact for the outside of BPF. Actually, x26 is unnecessary, but SP > requires 16 bytes alignment. > > So, the BPF stack layout looks like: > > high > original A64_SP => 0:+-----+ BPF prologue > |FP/LR| > current A64_FP => -16:+-----+ > | ... | callee saved registers > +-----+ > | | x25/x26 > BPF fp register => -80:+-----+ > | | > | ... | BPF prog stack > | | > | | > current A64_SP => +-----+ > | | > | ... | Function call stack > | | > +-----+ > low > > CC: Zi Shen Lim <zlim.lnx@gmail.com> > CC: Xi Wang <xi.wang@gmail.com> > Signed-off-by: Yang Shi <yang.shi@linaro.org> Acked-by: Zi Shen Lim <zlim.lnx@gmail.com> ^ permalink raw reply [flat|nested] 19+ messages in thread
* Re: [PATCH V4 2/2] arm64: bpf: make BPF prologue and epilogue align with ARM64 AAPCS @ 2015-11-17 4:37 ` Z Lim 0 siblings, 0 replies; 19+ messages in thread From: Z Lim @ 2015-11-17 4:37 UTC (permalink / raw) To: Yang Shi Cc: Alexei Starovoitov, Daniel Borkmann, Catalin Marinas, Will Deacon, David S. Miller, Xi Wang, LKML, Network Development, linux-arm-kernel@lists.infradead.org, linaro-kernel On Mon, Nov 16, 2015 at 2:35 PM, Yang Shi <yang.shi@linaro.org> wrote: > Save and restore FP/LR in BPF prog prologue and epilogue, save SP to FP > in prologue in order to get the correct stack backtrace. > > However, ARM64 JIT used FP (x29) as eBPF fp register, FP is subjected to > change during function call so it may cause the BPF prog stack base address > change too. > > Use x25 to replace FP as BPF stack base register (fp). Since x25 is callee > saved register, so it will keep intact during function call. > It is initialized in BPF prog prologue when BPF prog is started to run > everytime. Save and restore x25/x26 in BPF prologue and epilogue to keep > them intact for the outside of BPF. Actually, x26 is unnecessary, but SP > requires 16 bytes alignment. > > So, the BPF stack layout looks like: > > high > original A64_SP => 0:+-----+ BPF prologue > |FP/LR| > current A64_FP => -16:+-----+ > | ... | callee saved registers > +-----+ > | | x25/x26 > BPF fp register => -80:+-----+ > | | > | ... | BPF prog stack > | | > | | > current A64_SP => +-----+ > | | > | ... | Function call stack > | | > +-----+ > low > > CC: Zi Shen Lim <zlim.lnx@gmail.com> > CC: Xi Wang <xi.wang@gmail.com> > Signed-off-by: Yang Shi <yang.shi@linaro.org> Acked-by: Zi Shen Lim <zlim.lnx@gmail.com> ^ permalink raw reply [flat|nested] 19+ messages in thread
* [PATCH V4 2/2] arm64: bpf: make BPF prologue and epilogue align with ARM64 AAPCS 2015-11-17 4:37 ` Z Lim @ 2015-11-17 4:41 ` Alexei Starovoitov -1 siblings, 0 replies; 19+ messages in thread From: Alexei Starovoitov @ 2015-11-17 4:41 UTC (permalink / raw) To: linux-arm-kernel On Mon, Nov 16, 2015 at 08:37:11PM -0800, Z Lim wrote: > On Mon, Nov 16, 2015 at 2:35 PM, Yang Shi <yang.shi@linaro.org> wrote: > > Save and restore FP/LR in BPF prog prologue and epilogue, save SP to FP > > in prologue in order to get the correct stack backtrace. ... > > CC: Zi Shen Lim <zlim.lnx@gmail.com> > > CC: Xi Wang <xi.wang@gmail.com> > > Signed-off-by: Yang Shi <yang.shi@linaro.org> > > Acked-by: Zi Shen Lim <zlim.lnx@gmail.com> great that it's finalized. Yang, please resubmit both patches to netdev as fresh submission so it gets picked up by patchwork. ^ permalink raw reply [flat|nested] 19+ messages in thread
* Re: [PATCH V4 2/2] arm64: bpf: make BPF prologue and epilogue align with ARM64 AAPCS @ 2015-11-17 4:41 ` Alexei Starovoitov 0 siblings, 0 replies; 19+ messages in thread From: Alexei Starovoitov @ 2015-11-17 4:41 UTC (permalink / raw) To: Z Lim Cc: Yang Shi, Alexei Starovoitov, Daniel Borkmann, Catalin Marinas, Will Deacon, David S. Miller, Xi Wang, LKML, Network Development, linux-arm-kernel@lists.infradead.org, linaro-kernel On Mon, Nov 16, 2015 at 08:37:11PM -0800, Z Lim wrote: > On Mon, Nov 16, 2015 at 2:35 PM, Yang Shi <yang.shi@linaro.org> wrote: > > Save and restore FP/LR in BPF prog prologue and epilogue, save SP to FP > > in prologue in order to get the correct stack backtrace. ... > > CC: Zi Shen Lim <zlim.lnx@gmail.com> > > CC: Xi Wang <xi.wang@gmail.com> > > Signed-off-by: Yang Shi <yang.shi@linaro.org> > > Acked-by: Zi Shen Lim <zlim.lnx@gmail.com> great that it's finalized. Yang, please resubmit both patches to netdev as fresh submission so it gets picked up by patchwork. ^ permalink raw reply [flat|nested] 19+ messages in thread
* [PATCH V4 2/2] arm64: bpf: make BPF prologue and epilogue align with ARM64 AAPCS 2015-11-17 4:41 ` Alexei Starovoitov @ 2015-11-17 4:43 ` Shi, Yang -1 siblings, 0 replies; 19+ messages in thread From: Shi, Yang @ 2015-11-17 4:43 UTC (permalink / raw) To: linux-arm-kernel On 11/16/2015 8:41 PM, Alexei Starovoitov wrote: > On Mon, Nov 16, 2015 at 08:37:11PM -0800, Z Lim wrote: >> On Mon, Nov 16, 2015 at 2:35 PM, Yang Shi <yang.shi@linaro.org> wrote: >>> Save and restore FP/LR in BPF prog prologue and epilogue, save SP to FP >>> in prologue in order to get the correct stack backtrace. > ... >>> CC: Zi Shen Lim <zlim.lnx@gmail.com> >>> CC: Xi Wang <xi.wang@gmail.com> >>> Signed-off-by: Yang Shi <yang.shi@linaro.org> >> >> Acked-by: Zi Shen Lim <zlim.lnx@gmail.com> > > great that it's finalized. > Yang, please resubmit both patches to netdev as fresh submission so it > gets picked up by patchwork. OK, btw the first one has been applied by David. Yang > ^ permalink raw reply [flat|nested] 19+ messages in thread
* Re: [PATCH V4 2/2] arm64: bpf: make BPF prologue and epilogue align with ARM64 AAPCS @ 2015-11-17 4:43 ` Shi, Yang 0 siblings, 0 replies; 19+ messages in thread From: Shi, Yang @ 2015-11-17 4:43 UTC (permalink / raw) To: Alexei Starovoitov, Z Lim Cc: Alexei Starovoitov, Daniel Borkmann, Catalin Marinas, Will Deacon, David S. Miller, Xi Wang, LKML, Network Development, linux-arm-kernel@lists.infradead.org, linaro-kernel On 11/16/2015 8:41 PM, Alexei Starovoitov wrote: > On Mon, Nov 16, 2015 at 08:37:11PM -0800, Z Lim wrote: >> On Mon, Nov 16, 2015 at 2:35 PM, Yang Shi <yang.shi@linaro.org> wrote: >>> Save and restore FP/LR in BPF prog prologue and epilogue, save SP to FP >>> in prologue in order to get the correct stack backtrace. > ... >>> CC: Zi Shen Lim <zlim.lnx@gmail.com> >>> CC: Xi Wang <xi.wang@gmail.com> >>> Signed-off-by: Yang Shi <yang.shi@linaro.org> >> >> Acked-by: Zi Shen Lim <zlim.lnx@gmail.com> > > great that it's finalized. > Yang, please resubmit both patches to netdev as fresh submission so it > gets picked up by patchwork. OK, btw the first one has been applied by David. Yang > ^ permalink raw reply [flat|nested] 19+ messages in thread
* [PATCH V4 2/2] arm64: bpf: make BPF prologue and epilogue align with ARM64 AAPCS 2015-11-17 4:41 ` Alexei Starovoitov @ 2015-11-17 16:51 ` David Miller -1 siblings, 0 replies; 19+ messages in thread From: David Miller @ 2015-11-17 16:51 UTC (permalink / raw) To: linux-arm-kernel From: Alexei Starovoitov <alexei.starovoitov@gmail.com> Date: Mon, 16 Nov 2015 20:41:46 -0800 > On Mon, Nov 16, 2015 at 08:37:11PM -0800, Z Lim wrote: >> On Mon, Nov 16, 2015 at 2:35 PM, Yang Shi <yang.shi@linaro.org> wrote: >> > Save and restore FP/LR in BPF prog prologue and epilogue, save SP to FP >> > in prologue in order to get the correct stack backtrace. > ... >> > CC: Zi Shen Lim <zlim.lnx@gmail.com> >> > CC: Xi Wang <xi.wang@gmail.com> >> > Signed-off-by: Yang Shi <yang.shi@linaro.org> >> >> Acked-by: Zi Shen Lim <zlim.lnx@gmail.com> > > great that it's finalized. > Yang, please resubmit both patches to netdev as fresh submission so it > gets picked up by patchwork. He doesn't need to, I applied patch #1 independently the other day while the details of #2 were being worked out. ^ permalink raw reply [flat|nested] 19+ messages in thread
* Re: [PATCH V4 2/2] arm64: bpf: make BPF prologue and epilogue align with ARM64 AAPCS @ 2015-11-17 16:51 ` David Miller 0 siblings, 0 replies; 19+ messages in thread From: David Miller @ 2015-11-17 16:51 UTC (permalink / raw) To: alexei.starovoitov Cc: zlim.lnx, yang.shi, ast, daniel, catalin.marinas, will.deacon, xi.wang, linux-kernel, netdev, linux-arm-kernel, linaro-kernel From: Alexei Starovoitov <alexei.starovoitov@gmail.com> Date: Mon, 16 Nov 2015 20:41:46 -0800 > On Mon, Nov 16, 2015 at 08:37:11PM -0800, Z Lim wrote: >> On Mon, Nov 16, 2015 at 2:35 PM, Yang Shi <yang.shi@linaro.org> wrote: >> > Save and restore FP/LR in BPF prog prologue and epilogue, save SP to FP >> > in prologue in order to get the correct stack backtrace. > ... >> > CC: Zi Shen Lim <zlim.lnx@gmail.com> >> > CC: Xi Wang <xi.wang@gmail.com> >> > Signed-off-by: Yang Shi <yang.shi@linaro.org> >> >> Acked-by: Zi Shen Lim <zlim.lnx@gmail.com> > > great that it's finalized. > Yang, please resubmit both patches to netdev as fresh submission so it > gets picked up by patchwork. He doesn't need to, I applied patch #1 independently the other day while the details of #2 were being worked out. ^ permalink raw reply [flat|nested] 19+ messages in thread
* [PATCH V4 2/2] arm64: bpf: make BPF prologue and epilogue align with ARM64 AAPCS 2015-11-16 22:35 ` Yang Shi @ 2015-11-17 19:44 ` David Miller -1 siblings, 0 replies; 19+ messages in thread From: David Miller @ 2015-11-17 19:44 UTC (permalink / raw) To: linux-arm-kernel From: Yang Shi <yang.shi@linaro.org> Date: Mon, 16 Nov 2015 14:35:35 -0800 > Save and restore FP/LR in BPF prog prologue and epilogue, save SP to FP > in prologue in order to get the correct stack backtrace. > > However, ARM64 JIT used FP (x29) as eBPF fp register, FP is subjected to > change during function call so it may cause the BPF prog stack base address > change too. > > Use x25 to replace FP as BPF stack base register (fp). Since x25 is callee > saved register, so it will keep intact during function call. > It is initialized in BPF prog prologue when BPF prog is started to run > everytime. Save and restore x25/x26 in BPF prologue and epilogue to keep > them intact for the outside of BPF. Actually, x26 is unnecessary, but SP > requires 16 bytes alignment. > > So, the BPF stack layout looks like: ... > Signed-off-by: Yang Shi <yang.shi@linaro.org> Applied, thank you. ^ permalink raw reply [flat|nested] 19+ messages in thread
* Re: [PATCH V4 2/2] arm64: bpf: make BPF prologue and epilogue align with ARM64 AAPCS @ 2015-11-17 19:44 ` David Miller 0 siblings, 0 replies; 19+ messages in thread From: David Miller @ 2015-11-17 19:44 UTC (permalink / raw) To: yang.shi Cc: ast, daniel, catalin.marinas, will.deacon, zlim.lnx, xi.wang, linux-kernel, netdev, linux-arm-kernel, linaro-kernel From: Yang Shi <yang.shi@linaro.org> Date: Mon, 16 Nov 2015 14:35:35 -0800 > Save and restore FP/LR in BPF prog prologue and epilogue, save SP to FP > in prologue in order to get the correct stack backtrace. > > However, ARM64 JIT used FP (x29) as eBPF fp register, FP is subjected to > change during function call so it may cause the BPF prog stack base address > change too. > > Use x25 to replace FP as BPF stack base register (fp). Since x25 is callee > saved register, so it will keep intact during function call. > It is initialized in BPF prog prologue when BPF prog is started to run > everytime. Save and restore x25/x26 in BPF prologue and epilogue to keep > them intact for the outside of BPF. Actually, x26 is unnecessary, but SP > requires 16 bytes alignment. > > So, the BPF stack layout looks like: ... > Signed-off-by: Yang Shi <yang.shi@linaro.org> Applied, thank you. ^ permalink raw reply [flat|nested] 19+ messages in thread
end of thread, other threads:[~2015-11-17 19:45 UTC | newest]
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2015-11-13 18:09 ` [PATCH V3 2/2] arm64: bpf: make BPF prologue and epilogue align with ARM64 AAPCS Yang Shi
2015-11-13 18:09 ` Yang Shi
2015-11-14 2:39 ` Z Lim
2015-11-14 2:39 ` Z Lim
2015-11-14 2:39 ` Z Lim
2015-11-16 19:48 ` Shi, Yang
2015-11-16 19:48 ` Shi, Yang
2015-11-16 22:35 ` [PATCH V4 " Yang Shi
2015-11-16 22:35 ` Yang Shi
2015-11-17 4:37 ` Z Lim
2015-11-17 4:37 ` Z Lim
2015-11-17 4:41 ` Alexei Starovoitov
2015-11-17 4:41 ` Alexei Starovoitov
2015-11-17 4:43 ` Shi, Yang
2015-11-17 4:43 ` Shi, Yang
2015-11-17 16:51 ` David Miller
2015-11-17 16:51 ` David Miller
2015-11-17 19:44 ` David Miller
2015-11-17 19:44 ` David Miller
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