Re: [PATCH] i2c: davinci: Increase module clock frequency

[santosh shilimkar <santosh.shilimkar@oracle.com>]

On 11/19/2015 4:21 AM, Alexander Sverdlin wrote:
> I2C controller used in Keystone SoC has an undocumented peculiarity which
> results in SDA-SCL margins being dependent on module clock. Driving high
> capacity bus near its limits can result in STOP condition sometimes being
> understood as REPEATED-START by slaves (or NACK instead of ACK, etc...).
> Driving the module with higher clocks increases the margin between SDA and SCL
> transitions, making the operations with higher bus rates more robust. Therefore,
> target the module clock to 12MHz instead of 7MHz, still staying within
> the specification limits.
>
> Before the change STOP timing looked like this on 400kHz:
>
> SDA   ----------+          +----
>                   \        /
>                    \      /
>                     +----+
>                         (1)
> SCL   --+          +------------
>           \        /
>            \      /
>             +----+
>                 (2)
>
> While only point (1) signals STOP, point (2) could be incorrectly recognized as
> repeated-START (almost no margin between SDA and SCL transitions).
>
> After the change there is at least 600ns margin measured between SCL fall and
> SDA fall during STOP generation:
>
> SDA   ------+          +----
>               \        /
>                \      /
>                 +----+
>
> SCL   --+          +--------
>           \        /
>            \      /
>             +----+
>             ->|    |<- 600ns
>                  ->|   |<- tSUSTO
>
> So called tSUSTO (setup time for STOP condition) is still slightly higher than
> 600ns, so no problem here.
>
> Signed-off-by: Alexander Sverdlin <alexander.sverdlin@nokia.com>
> ---
Nice text artwork.
Acked-by: Santosh Shilimkar <ssantosh@kernel.org>