From: Caesar Wang <wxt@rock-chips.com>
To: Sjoerd Simons <sjoerd.simons@collabora.co.uk>,
Mark Brown <broonie@kernel.org>
Cc: alsa-devel@alsa-project.org, Heiko Stuebner <heiko@sntech.de>,
Liam Girdwood <lgirdwood@gmail.com>,
Takashi Iwai <tiwai@suse.com>,
linux-kernel@vger.kernel.org, linux-rockchip@lists.infradead.org,
Jaroslav Kysela <perex@perex.cz>,
linux-arm-kernel@lists.infradead.org
Subject: Re: [PATCH] ASoC: rockchip: Fix incorrect VDW value for 24 bit
Date: Wed, 25 Nov 2015 17:03:13 +0800 [thread overview]
Message-ID: <56557951.7070401@rock-chips.com> (raw)
In-Reply-To: <1448441651-444-1-git-send-email-sjoerd.simons@collabora.co.uk>
Hi,
在 2015年11月25日 16:54, Sjoerd Simons 写道:
> Correct valid data word register value for 24 bit data width. The
> bit value should be 10 (aka 0x2), not 0x10.
>
> This fixes playback of 24 bit audio.
>
> Signed-off-by: Sjoerd Simons <sjoerd.simons@collabora.co.uk>
>
> ---
>
> sound/soc/rockchip/rockchip_spdif.h | 6 +++---
> 1 file changed, 3 insertions(+), 3 deletions(-)
>
> diff --git a/sound/soc/rockchip/rockchip_spdif.h b/sound/soc/rockchip/rockchip_spdif.h
> index 07f86a2..921b409 100644
> --- a/sound/soc/rockchip/rockchip_spdif.h
> +++ b/sound/soc/rockchip/rockchip_spdif.h
> @@ -28,9 +28,9 @@
> #define SPDIF_CFGR_VDW(x) (x << SPDIF_CFGR_VDW_SHIFT)
> #define SDPIF_CFGR_VDW_MASK (0xf << SPDIF_CFGR_VDW_SHIFT)
>
> -#define SPDIF_CFGR_VDW_16 SPDIF_CFGR_VDW(0x00)
> -#define SPDIF_CFGR_VDW_20 SPDIF_CFGR_VDW(0x01)
> -#define SPDIF_CFGR_VDW_24 SPDIF_CFGR_VDW(0x10)
> +#define SPDIF_CFGR_VDW_16 SPDIF_CFGR_VDW(0x0)
> +#define SPDIF_CFGR_VDW_20 SPDIF_CFGR_VDW(0x1)
> +#define SPDIF_CFGR_VDW_24 SPDIF_CFGR_VDW(0x2)
Yep,
From the TRM says: (RK3288/RK3368...)
VDW
Valid data width
00: 16bit
01: 20bit
10: 24bit
11: reserved
....
So feel free add my tag:
Reviewed-by: Caesar Wang <wxt@rock-chips.com>
>
> /*
> * DMACR
--
caesar wang | software engineer | wxt@rock-chip.com
WARNING: multiple messages have this Message-ID (diff)
From: wxt@rock-chips.com (Caesar Wang)
To: linux-arm-kernel@lists.infradead.org
Subject: [PATCH] ASoC: rockchip: Fix incorrect VDW value for 24 bit
Date: Wed, 25 Nov 2015 17:03:13 +0800 [thread overview]
Message-ID: <56557951.7070401@rock-chips.com> (raw)
In-Reply-To: <1448441651-444-1-git-send-email-sjoerd.simons@collabora.co.uk>
Hi,
? 2015?11?25? 16:54, Sjoerd Simons ??:
> Correct valid data word register value for 24 bit data width. The
> bit value should be 10 (aka 0x2), not 0x10.
>
> This fixes playback of 24 bit audio.
>
> Signed-off-by: Sjoerd Simons <sjoerd.simons@collabora.co.uk>
>
> ---
>
> sound/soc/rockchip/rockchip_spdif.h | 6 +++---
> 1 file changed, 3 insertions(+), 3 deletions(-)
>
> diff --git a/sound/soc/rockchip/rockchip_spdif.h b/sound/soc/rockchip/rockchip_spdif.h
> index 07f86a2..921b409 100644
> --- a/sound/soc/rockchip/rockchip_spdif.h
> +++ b/sound/soc/rockchip/rockchip_spdif.h
> @@ -28,9 +28,9 @@
> #define SPDIF_CFGR_VDW(x) (x << SPDIF_CFGR_VDW_SHIFT)
> #define SDPIF_CFGR_VDW_MASK (0xf << SPDIF_CFGR_VDW_SHIFT)
>
> -#define SPDIF_CFGR_VDW_16 SPDIF_CFGR_VDW(0x00)
> -#define SPDIF_CFGR_VDW_20 SPDIF_CFGR_VDW(0x01)
> -#define SPDIF_CFGR_VDW_24 SPDIF_CFGR_VDW(0x10)
> +#define SPDIF_CFGR_VDW_16 SPDIF_CFGR_VDW(0x0)
> +#define SPDIF_CFGR_VDW_20 SPDIF_CFGR_VDW(0x1)
> +#define SPDIF_CFGR_VDW_24 SPDIF_CFGR_VDW(0x2)
Yep,
From the TRM says: (RK3288/RK3368...)
VDW
Valid data width
00: 16bit
01: 20bit
10: 24bit
11: reserved
....
So feel free add my tag:
Reviewed-by: Caesar Wang <wxt@rock-chips.com>
>
> /*
> * DMACR
--
caesar wang | software engineer | wxt at rock-chip.com
next prev parent reply other threads:[~2015-11-25 9:03 UTC|newest]
Thread overview: 5+ messages / expand[flat|nested] mbox.gz Atom feed top
2015-11-25 8:54 [PATCH] ASoC: rockchip: Fix incorrect VDW value for 24 bit Sjoerd Simons
2015-11-25 8:54 ` Sjoerd Simons
2015-11-25 9:03 ` Caesar Wang [this message]
2015-11-25 9:03 ` Caesar Wang
2015-11-25 12:11 ` Applied "ASoC: rockchip: Fix incorrect VDW value for 24 bit" to the asoc tree Mark Brown
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