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From: Marc Zyngier <marc.zyngier@arm.com>
To: Shannon Zhao <shannon.zhao@linaro.org>,
	Shannon Zhao <zhaoshenglong@huawei.com>,
	kvmarm@lists.cs.columbia.edu, christoffer.dall@linaro.org
Cc: linux-arm-kernel@lists.infradead.org, kvm@vger.kernel.org,
	will.deacon@arm.com, alex.bennee@linaro.org, wei@redhat.com,
	cov@codeaurora.org, peter.huangpeng@huawei.com,
	hangaohuai@huawei.com
Subject: Re: [PATCH v5 03/21] KVM: ARM64: Add offset defines for PMU registers
Date: Mon, 07 Dec 2015 14:55:20 +0000	[thread overview]
Message-ID: <56659DD8.6050109@arm.com> (raw)
In-Reply-To: <5665984F.30102@linaro.org>

On 07/12/15 14:31, Shannon Zhao wrote:
> 
> 
> On 2015/12/7 22:06, Marc Zyngier wrote:
>> On 03/12/15 06:11, Shannon Zhao wrote:
>>> From: Shannon Zhao <shannon.zhao@linaro.org>
>>>
>>> We are about to trap and emulate acccesses to each PMU register
>>
>> s/acccesses/accesses/
>>
>>> individually. This adds the context offsets for the AArch64 PMU
>>> registers and their AArch32 counterparts.
>>>
>>> Signed-off-by: Shannon Zhao <shannon.zhao@linaro.org>
>>> ---
>>>   arch/arm64/include/asm/kvm_asm.h | 55 ++++++++++++++++++++++++++++++++++++----
>>>   1 file changed, 50 insertions(+), 5 deletions(-)
>>>
>>> diff --git a/arch/arm64/include/asm/kvm_asm.h b/arch/arm64/include/asm/kvm_asm.h
>>> index 5e37710..4f804c1 100644
>>> --- a/arch/arm64/include/asm/kvm_asm.h
>>> +++ b/arch/arm64/include/asm/kvm_asm.h
>>> @@ -48,12 +48,34 @@
>>>   #define MDSCR_EL1	22	/* Monitor Debug System Control Register */
>>>   #define MDCCINT_EL1	23	/* Monitor Debug Comms Channel Interrupt Enable Reg */
>>>
>>
>> Coming back to this patch, it gives a clear view of where you have state
>> duplication.
>>
>>> +/* Performance Monitors Registers */
>>> +#define PMCR_EL0	24	/* Control Register */
>>> +#define PMOVSSET_EL0	25	/* Overflow Flag Status Set Register */
>>> +#define PMOVSCLR_EL0	26	/* Overflow Flag Status Clear Register */
>>
>> This should only be a single state. You don't even have to represent it
>> in the sysreg array, to be honest.
>>
> Yeah, I could store the state in one of them and drop one of them here.

Indeed.

>>> +#define PMSELR_EL0	27	/* Event Counter Selection Register */
>>> +#define PMCEID0_EL0	28	/* Common Event Identification Register 0 */
>>> +#define PMCEID1_EL0	29	/* Common Event Identification Register 1 */
>>> +#define PMEVCNTR0_EL0	30	/* Event Counter Register (0-30) */
>>> +#define PMEVCNTR30_EL0	60
>>> +#define PMCCNTR_EL0	61	/* Cycle Counter Register */
>>> +#define PMEVTYPER0_EL0	62	/* Event Type Register (0-30) */
>>> +#define PMEVTYPER30_EL0	92
>>> +#define PMCCFILTR_EL0	93	/* Cycle Count Filter Register */
>>> +#define PMXEVCNTR_EL0	94	/* Selected Event Count Register */
>>> +#define PMXEVTYPER_EL0	95	/* Selected Event Type Register */
>>
>> These "select" registers aren't real ones, but just a way to pick the
>> real register. They should be removed.
>>
> I think these two could be retained, since it's convenient to handle the 
> guest accessing by using "case PMXEVCNTR_EL0"

Not really. This is just occupying pointless space is the register file,
and it would be clearer to have a couple of helpers called directly from
the sys_reg trap table.

Please get rid of it.

Thanks,

	M.
-- 
Jazz is not dead. It just smells funny...

WARNING: multiple messages have this Message-ID (diff)
From: marc.zyngier@arm.com (Marc Zyngier)
To: linux-arm-kernel@lists.infradead.org
Subject: [PATCH v5 03/21] KVM: ARM64: Add offset defines for PMU registers
Date: Mon, 07 Dec 2015 14:55:20 +0000	[thread overview]
Message-ID: <56659DD8.6050109@arm.com> (raw)
In-Reply-To: <5665984F.30102@linaro.org>

On 07/12/15 14:31, Shannon Zhao wrote:
> 
> 
> On 2015/12/7 22:06, Marc Zyngier wrote:
>> On 03/12/15 06:11, Shannon Zhao wrote:
>>> From: Shannon Zhao <shannon.zhao@linaro.org>
>>>
>>> We are about to trap and emulate acccesses to each PMU register
>>
>> s/acccesses/accesses/
>>
>>> individually. This adds the context offsets for the AArch64 PMU
>>> registers and their AArch32 counterparts.
>>>
>>> Signed-off-by: Shannon Zhao <shannon.zhao@linaro.org>
>>> ---
>>>   arch/arm64/include/asm/kvm_asm.h | 55 ++++++++++++++++++++++++++++++++++++----
>>>   1 file changed, 50 insertions(+), 5 deletions(-)
>>>
>>> diff --git a/arch/arm64/include/asm/kvm_asm.h b/arch/arm64/include/asm/kvm_asm.h
>>> index 5e37710..4f804c1 100644
>>> --- a/arch/arm64/include/asm/kvm_asm.h
>>> +++ b/arch/arm64/include/asm/kvm_asm.h
>>> @@ -48,12 +48,34 @@
>>>   #define MDSCR_EL1	22	/* Monitor Debug System Control Register */
>>>   #define MDCCINT_EL1	23	/* Monitor Debug Comms Channel Interrupt Enable Reg */
>>>
>>
>> Coming back to this patch, it gives a clear view of where you have state
>> duplication.
>>
>>> +/* Performance Monitors Registers */
>>> +#define PMCR_EL0	24	/* Control Register */
>>> +#define PMOVSSET_EL0	25	/* Overflow Flag Status Set Register */
>>> +#define PMOVSCLR_EL0	26	/* Overflow Flag Status Clear Register */
>>
>> This should only be a single state. You don't even have to represent it
>> in the sysreg array, to be honest.
>>
> Yeah, I could store the state in one of them and drop one of them here.

Indeed.

>>> +#define PMSELR_EL0	27	/* Event Counter Selection Register */
>>> +#define PMCEID0_EL0	28	/* Common Event Identification Register 0 */
>>> +#define PMCEID1_EL0	29	/* Common Event Identification Register 1 */
>>> +#define PMEVCNTR0_EL0	30	/* Event Counter Register (0-30) */
>>> +#define PMEVCNTR30_EL0	60
>>> +#define PMCCNTR_EL0	61	/* Cycle Counter Register */
>>> +#define PMEVTYPER0_EL0	62	/* Event Type Register (0-30) */
>>> +#define PMEVTYPER30_EL0	92
>>> +#define PMCCFILTR_EL0	93	/* Cycle Count Filter Register */
>>> +#define PMXEVCNTR_EL0	94	/* Selected Event Count Register */
>>> +#define PMXEVTYPER_EL0	95	/* Selected Event Type Register */
>>
>> These "select" registers aren't real ones, but just a way to pick the
>> real register. They should be removed.
>>
> I think these two could be retained, since it's convenient to handle the 
> guest accessing by using "case PMXEVCNTR_EL0"

Not really. This is just occupying pointless space is the register file,
and it would be clearer to have a couple of helpers called directly from
the sys_reg trap table.

Please get rid of it.

Thanks,

	M.
-- 
Jazz is not dead. It just smells funny...

  reply	other threads:[~2015-12-07 14:55 UTC|newest]

Thread overview: 99+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2015-12-03  6:11 [PATCH v5 00/21] KVM: ARM64: Add guest PMU support Shannon Zhao
2015-12-03  6:11 ` Shannon Zhao
2015-12-03  6:11 ` Shannon Zhao
2015-12-03  6:11 ` [PATCH v5 01/21] ARM64: Move PMU register related defines to asm/pmu.h Shannon Zhao
2015-12-03  6:11   ` Shannon Zhao
2015-12-03  6:11   ` Shannon Zhao
2015-12-03  6:11 ` [PATCH v5 02/21] KVM: ARM64: Define PMU data structure for each vcpu Shannon Zhao
2015-12-03  6:11   ` Shannon Zhao
2015-12-03  6:11   ` Shannon Zhao
2015-12-07 15:05   ` Marc Zyngier
2015-12-07 15:05     ` Marc Zyngier
2015-12-07 16:42     ` Marc Zyngier
2015-12-07 16:42       ` Marc Zyngier
2015-12-03  6:11 ` [PATCH v5 03/21] KVM: ARM64: Add offset defines for PMU registers Shannon Zhao
2015-12-03  6:11   ` Shannon Zhao
2015-12-03  6:11   ` Shannon Zhao
2015-12-07 14:06   ` Marc Zyngier
2015-12-07 14:06     ` Marc Zyngier
2015-12-07 14:31     ` Shannon Zhao
2015-12-07 14:31       ` Shannon Zhao
2015-12-07 14:55       ` Marc Zyngier [this message]
2015-12-07 14:55         ` Marc Zyngier
2015-12-08  8:09         ` Shannon Zhao
2015-12-08  8:09           ` Shannon Zhao
2015-12-08  8:09           ` Shannon Zhao
2015-12-08  9:02           ` Marc Zyngier
2015-12-08  9:02             ` Marc Zyngier
2015-12-03  6:11 ` [PATCH v5 04/21] KVM: ARM64: Add reset and access handlers for PMCR_EL0 register Shannon Zhao
2015-12-03  6:11   ` Shannon Zhao
2015-12-03  6:11   ` Shannon Zhao
2015-12-07 13:28   ` Marc Zyngier
2015-12-07 13:28     ` Marc Zyngier
2015-12-03  6:11 ` [PATCH v5 05/21] KVM: ARM64: Add reset and access handlers for PMSELR register Shannon Zhao
2015-12-03  6:11   ` Shannon Zhao
2015-12-03  6:11   ` Shannon Zhao
2015-12-03  6:11 ` [PATCH v5 06/21] KVM: ARM64: Add reset and access handlers for PMCEID0 and PMCEID1 register Shannon Zhao
2015-12-03  6:11   ` Shannon Zhao
2015-12-03  6:11   ` Shannon Zhao
2015-12-03  6:11 ` [PATCH v5 07/21] KVM: ARM64: PMU: Add perf event map and introduce perf event creating function Shannon Zhao
2015-12-03  6:11   ` Shannon Zhao
2015-12-03  6:11   ` Shannon Zhao
2015-12-03  6:11 ` [PATCH v5 08/21] KVM: ARM64: Add reset and access handlers for PMXEVTYPER register Shannon Zhao
2015-12-03  6:11   ` Shannon Zhao
2015-12-03  6:11   ` Shannon Zhao
2015-12-07 13:38   ` Marc Zyngier
2015-12-07 13:38     ` Marc Zyngier
2015-12-03  6:11 ` [PATCH v5 09/21] KVM: ARM64: Add reset and access handlers for PMXEVCNTR register Shannon Zhao
2015-12-03  6:11   ` Shannon Zhao
2015-12-03  6:11   ` Shannon Zhao
2015-12-03  6:11 ` [PATCH v5 10/21] KVM: ARM64: Add reset and access handlers for PMCCNTR register Shannon Zhao
2015-12-03  6:11   ` Shannon Zhao
2015-12-03  6:11   ` Shannon Zhao
2015-12-03  6:11 ` [PATCH v5 11/21] KVM: ARM64: Add reset and access handlers for PMCNTENSET and PMCNTENCLR register Shannon Zhao
2015-12-03  6:11   ` Shannon Zhao
2015-12-03  6:11   ` Shannon Zhao
2015-12-07 13:42   ` Marc Zyngier
2015-12-07 13:42     ` Marc Zyngier
2015-12-03  6:11 ` [PATCH v5 12/21] KVM: ARM64: Add reset and access handlers for PMINTENSET and PMINTENCLR register Shannon Zhao
2015-12-03  6:11   ` Shannon Zhao
2015-12-03  6:11   ` Shannon Zhao
2015-12-03  6:11 ` [PATCH v5 13/21] KVM: ARM64: Add reset and access handlers for PMOVSSET and PMOVSCLR register Shannon Zhao
2015-12-03  6:11   ` Shannon Zhao
2015-12-03  6:11   ` Shannon Zhao
2015-12-03  6:11 ` [PATCH v5 14/21] KVM: ARM64: Add reset and access handlers for PMUSERENR register Shannon Zhao
2015-12-03  6:11   ` Shannon Zhao
2015-12-03  6:11   ` Shannon Zhao
2015-12-03  6:11 ` [PATCH v5 15/21] KVM: ARM64: Add reset and access handlers for PMSWINC register Shannon Zhao
2015-12-03  6:11   ` Shannon Zhao
2015-12-03  6:11   ` Shannon Zhao
2015-12-03  6:11 ` [PATCH v5 16/21] KVM: ARM64: Add access handlers for PMEVCNTRn and PMEVTYPERn register Shannon Zhao
2015-12-03  6:11   ` Shannon Zhao
2015-12-03  6:11   ` Shannon Zhao
2015-12-03  6:11 ` [PATCH v5 17/21] KVM: ARM64: Add helper to handle PMCR register bits Shannon Zhao
2015-12-03  6:11   ` Shannon Zhao
2015-12-03  6:11   ` Shannon Zhao
2015-12-03  6:11 ` [PATCH v5 18/21] KVM: ARM64: Add PMU overflow interrupt routing Shannon Zhao
2015-12-03  6:11   ` Shannon Zhao
2015-12-03  6:11   ` Shannon Zhao
2015-12-03  6:11 ` [PATCH v5 19/21] KVM: ARM64: Reset PMU state when resetting vcpu Shannon Zhao
2015-12-03  6:11   ` Shannon Zhao
2015-12-03  6:11   ` Shannon Zhao
2015-12-03  6:11 ` [PATCH v5 20/21] KVM: ARM64: Free perf event of PMU when destroying vcpu Shannon Zhao
2015-12-03  6:11   ` Shannon Zhao
2015-12-03  6:11   ` Shannon Zhao
2015-12-03  6:11 ` [PATCH v5 21/21] KVM: ARM64: Add a new kvm ARM PMU device Shannon Zhao
2015-12-03  6:11   ` Shannon Zhao
2015-12-03  6:11   ` Shannon Zhao
2015-12-07 13:56   ` Marc Zyngier
2015-12-07 13:56     ` Marc Zyngier
2015-12-07 14:37     ` Shannon Zhao
2015-12-07 14:37       ` Shannon Zhao
2015-12-07 15:06       ` Marc Zyngier
2015-12-07 15:06         ` Marc Zyngier
2015-12-07 14:11 ` [PATCH v5 00/21] KVM: ARM64: Add guest PMU support Marc Zyngier
2015-12-07 14:11   ` Marc Zyngier
2015-12-07 14:47   ` Shannon Zhao
2015-12-07 14:47     ` Shannon Zhao
2015-12-07 15:09     ` Marc Zyngier
2015-12-07 15:09       ` Marc Zyngier

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