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From: Michael Davidsaver <mdavidsaver@gmail.com>
To: Peter Maydell <peter.maydell@linaro.org>
Cc: Peter Crosthwaite <crosthwaitepeter@gmail.com>,
	qemu-arm <qemu-arm@nongnu.org>,
	QEMU Developers <qemu-devel@nongnu.org>
Subject: Re: [Qemu-arm] [PATCH v2 05/26] armv7m: add armv7m_excp_running_prio()
Date: Sun, 27 Dec 2015 15:56:13 -0500	[thread overview]
Message-ID: <5680506D.9050402@gmail.com> (raw)
In-Reply-To: <CAFEAcA-0Z=rhtvO0o=WoAE4pBQ0Zqrj1n_OtcdW+2FAOd0FH9A@mail.gmail.com>

On 12/17/2015 09:36 AM, Peter Maydell wrote:
> On 3 December 2015 at 00:18, Michael Davidsaver <mdavidsaver@gmail.com> wrote:
>> Implements v7m exception priority algorithm
>> using FAULTMASK, PRIMASK, BASEPRI, and the highest
>> priority active exception.
>>
>> The number returned is the current execution priority
>> which may be in the range [-2,0x7f] when an exception is active
>> or 0x100 when no exception is active.
>> ---
>>  hw/intc/armv7m_nvic.c | 25 +++++++++++++++++++++++++
>>  target-arm/cpu.h      |  1 +
>>  2 files changed, 26 insertions(+)
>>
>> diff --git a/hw/intc/armv7m_nvic.c b/hw/intc/armv7m_nvic.c
>> index 6fc167e..0145ca7 100644
>> --- a/hw/intc/armv7m_nvic.c
>> +++ b/hw/intc/armv7m_nvic.c
>> @@ -18,6 +18,8 @@
>>
>>  typedef struct {
>>      GICState gic;
>> +    uint8_t prigroup;
>> +
>>      struct {
>>          uint32_t control;
>>          uint32_t reload;
>> @@ -116,6 +118,29 @@ static void systick_reset(nvic_state *s)
>>      timer_del(s->systick.timer);
>>  }
>>
>> +/* @returns the active (running) exception priority.
>> + *    only a higher (numerically lower) priority can preempt.
>> + */
>> +int armv7m_excp_running_prio(ARMCPU *cpu)
>> +{
>> +    CPUARMState *env = &cpu->env;
>> +    nvic_state *s = env->nvic;
>> +    int running;
>> +
>> +    if (env->daif & PSTATE_F) { /* FAULTMASK */
>> +        running = -1;
>> +    } else if (env->daif & PSTATE_I) { /* PRIMASK */
>> +        running = 0;
>> +    } else if (env->v7m.basepri > 0) {
>> +        /* BASEPRI==1 -> masks [1,255] (not same as PRIMASK==1) */
>> +        running = env->v7m.basepri >> (s->prigroup+1);
> This isn't right -- the effect of PRIGROUP is that we mask
> out the lower (subgroup) bits, but the upper group bits stay
> where they are rather than shifting down.
>
> So you want env->v7m.basepri & ~((1 << (s->prigroup + 1)) - 1);
>
> (the same mask you need to get the group priority for
> an interrupt).

I don't know about "right", but it is consistent with how the
.prio_group field is now handled in the nvic.  So I think the final
behavior is as specified.

There is no functional reason that I do this.  I just think it makes the
DPRINTF messages easier to interpret.  If you feel strongly I can change
this.


WARNING: multiple messages have this Message-ID (diff)
From: Michael Davidsaver <mdavidsaver@gmail.com>
To: Peter Maydell <peter.maydell@linaro.org>
Cc: Peter Crosthwaite <crosthwaitepeter@gmail.com>,
	qemu-arm <qemu-arm@nongnu.org>,
	QEMU Developers <qemu-devel@nongnu.org>
Subject: Re: [Qemu-devel] [PATCH v2 05/26] armv7m: add armv7m_excp_running_prio()
Date: Sun, 27 Dec 2015 15:56:13 -0500	[thread overview]
Message-ID: <5680506D.9050402@gmail.com> (raw)
In-Reply-To: <CAFEAcA-0Z=rhtvO0o=WoAE4pBQ0Zqrj1n_OtcdW+2FAOd0FH9A@mail.gmail.com>

On 12/17/2015 09:36 AM, Peter Maydell wrote:
> On 3 December 2015 at 00:18, Michael Davidsaver <mdavidsaver@gmail.com> wrote:
>> Implements v7m exception priority algorithm
>> using FAULTMASK, PRIMASK, BASEPRI, and the highest
>> priority active exception.
>>
>> The number returned is the current execution priority
>> which may be in the range [-2,0x7f] when an exception is active
>> or 0x100 when no exception is active.
>> ---
>>  hw/intc/armv7m_nvic.c | 25 +++++++++++++++++++++++++
>>  target-arm/cpu.h      |  1 +
>>  2 files changed, 26 insertions(+)
>>
>> diff --git a/hw/intc/armv7m_nvic.c b/hw/intc/armv7m_nvic.c
>> index 6fc167e..0145ca7 100644
>> --- a/hw/intc/armv7m_nvic.c
>> +++ b/hw/intc/armv7m_nvic.c
>> @@ -18,6 +18,8 @@
>>
>>  typedef struct {
>>      GICState gic;
>> +    uint8_t prigroup;
>> +
>>      struct {
>>          uint32_t control;
>>          uint32_t reload;
>> @@ -116,6 +118,29 @@ static void systick_reset(nvic_state *s)
>>      timer_del(s->systick.timer);
>>  }
>>
>> +/* @returns the active (running) exception priority.
>> + *    only a higher (numerically lower) priority can preempt.
>> + */
>> +int armv7m_excp_running_prio(ARMCPU *cpu)
>> +{
>> +    CPUARMState *env = &cpu->env;
>> +    nvic_state *s = env->nvic;
>> +    int running;
>> +
>> +    if (env->daif & PSTATE_F) { /* FAULTMASK */
>> +        running = -1;
>> +    } else if (env->daif & PSTATE_I) { /* PRIMASK */
>> +        running = 0;
>> +    } else if (env->v7m.basepri > 0) {
>> +        /* BASEPRI==1 -> masks [1,255] (not same as PRIMASK==1) */
>> +        running = env->v7m.basepri >> (s->prigroup+1);
> This isn't right -- the effect of PRIGROUP is that we mask
> out the lower (subgroup) bits, but the upper group bits stay
> where they are rather than shifting down.
>
> So you want env->v7m.basepri & ~((1 << (s->prigroup + 1)) - 1);
>
> (the same mask you need to get the group priority for
> an interrupt).

I don't know about "right", but it is consistent with how the
.prio_group field is now handled in the nvic.  So I think the final
behavior is as specified.

There is no functional reason that I do this.  I just think it makes the
DPRINTF messages easier to interpret.  If you feel strongly I can change
this.

  reply	other threads:[~2015-12-27 20:56 UTC|newest]

Thread overview: 84+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2015-12-03  0:18 [Qemu-devel] [PATCH v2 00/26] armv7m: exception handling, MPU, and more Michael Davidsaver
2015-12-03  0:18 ` [Qemu-arm] [PATCH v2 01/26] armv7m: MRS/MSR handle unprivileged access Michael Davidsaver
2015-12-03  0:18   ` [Qemu-devel] " Michael Davidsaver
2015-12-17 13:10   ` [Qemu-arm] " Peter Maydell
2015-12-17 13:10     ` [Qemu-devel] " Peter Maydell
2017-01-12 14:14     ` [Qemu-arm] " Peter Maydell
2017-01-12 14:14       ` [Qemu-devel] " Peter Maydell
2017-01-12 16:33       ` [Qemu-arm] " Michael Davidsaver
2017-01-12 16:33         ` [Qemu-devel] " Michael Davidsaver
2015-12-03  0:18 ` [Qemu-devel] [PATCH v2 02/26] armv7m: Undo armv7m.hack Michael Davidsaver
2015-12-17 15:38   ` [Qemu-arm] " Peter Maydell
2015-12-17 15:38     ` [Qemu-devel] " Peter Maydell
2015-12-27 20:22     ` [Qemu-arm] " Michael Davidsaver
2015-12-27 20:22       ` [Qemu-devel] " Michael Davidsaver
2015-12-28 18:36       ` [Qemu-arm] " Peter Maydell
2015-12-28 18:36         ` [Qemu-devel] " Peter Maydell
2015-12-28  1:55     ` [Qemu-arm] " Michael Davidsaver
2015-12-28  1:55       ` [Qemu-devel] " Michael Davidsaver
2015-12-28 18:27       ` [Qemu-arm] " Peter Maydell
2015-12-28 18:27         ` [Qemu-devel] " Peter Maydell
2015-12-03  0:18 ` [Qemu-devel] [PATCH v2 03/26] armv7m: Explicit error for bad vector table Michael Davidsaver
2015-12-17 13:25   ` [Qemu-arm] " Peter Maydell
2015-12-17 13:25     ` [Qemu-devel] " Peter Maydell
2015-12-27 20:43     ` [Qemu-arm] " Michael Davidsaver
2015-12-27 20:43       ` [Qemu-devel] " Michael Davidsaver
2015-12-28 18:38       ` [Qemu-arm] " Peter Maydell
2015-12-28 18:38         ` [Qemu-devel] " Peter Maydell
2015-12-03  0:18 ` [Qemu-devel] [PATCH v2 04/26] armv7m: additional cpu state for exception handling Michael Davidsaver
2015-12-03  0:18 ` [Qemu-devel] [PATCH v2 05/26] armv7m: add armv7m_excp_running_prio() Michael Davidsaver
2015-12-17 14:36   ` [Qemu-arm] " Peter Maydell
2015-12-17 14:36     ` [Qemu-devel] " Peter Maydell
2015-12-27 20:56     ` Michael Davidsaver [this message]
2015-12-27 20:56       ` Michael Davidsaver
2015-12-28 18:41       ` Peter Maydell
2015-12-03  0:18 ` [Qemu-arm] [PATCH v2 06/26] armv7m: fix I and F flag handling Michael Davidsaver
2015-12-03  0:18   ` [Qemu-devel] " Michael Davidsaver
2015-12-17 14:39   ` [Qemu-arm] " Peter Maydell
2015-12-17 14:39     ` [Qemu-devel] " Peter Maydell
2015-12-17 15:18     ` [Qemu-arm] " Peter Maydell
2015-12-17 15:18       ` [Qemu-devel] " Peter Maydell
2015-12-28  1:59       ` [Qemu-arm] " Michael Davidsaver
2015-12-28  1:59         ` [Qemu-devel] " Michael Davidsaver
2015-12-28 18:43         ` [Qemu-arm] " Peter Maydell
2015-12-28 18:43           ` [Qemu-devel] " Peter Maydell
2015-12-03  0:18 ` [Qemu-devel] [PATCH v2 07/26] armv7m: simpler/faster exception start Michael Davidsaver
2015-12-17 15:39   ` [Qemu-arm] " Peter Maydell
2015-12-17 15:39     ` [Qemu-devel] " Peter Maydell
2015-12-03  0:18 ` [Qemu-devel] [PATCH v2 08/26] armv7m: rewrite NVIC Michael Davidsaver
2015-12-17 18:49   ` [Qemu-arm] " Peter Maydell
2015-12-17 18:49     ` [Qemu-devel] " Peter Maydell
2015-12-19 19:08   ` Christopher Friedt
2015-12-19 19:45     ` Christopher Friedt
2015-12-03  0:18 ` [Qemu-devel] [PATCH v2 09/26] armv7m: implement CFSR, HFSR, BFAR, and MMFAR Michael Davidsaver
2015-12-17 19:04   ` [Qemu-arm] " Peter Maydell
2015-12-17 19:04     ` [Qemu-devel] " Peter Maydell
2015-12-03  0:18 ` [Qemu-devel] [PATCH v2 10/26] armv7m: auto-clear FAULTMASK Michael Davidsaver
2015-12-17 19:07   ` [Qemu-arm] " Peter Maydell
2015-12-17 19:07     ` [Qemu-devel] " Peter Maydell
2015-12-03  0:18 ` [Qemu-devel] [PATCH v2 11/26] arm: gic: Remove references to NVIC Michael Davidsaver
2015-12-17 19:08   ` [Qemu-arm] " Peter Maydell
2015-12-17 19:08     ` [Qemu-devel] " Peter Maydell
2015-12-03  0:18 ` [Qemu-devel] [PATCH v2 12/26] armv7m: check exception return consistency Michael Davidsaver
2015-12-17 19:26   ` [Qemu-arm] " Peter Maydell
2015-12-17 19:26     ` [Qemu-devel] " Peter Maydell
2015-12-03  0:18 ` [Qemu-devel] [PATCH v2 13/26] armv7m: implement CCR Michael Davidsaver
2015-12-17 19:31   ` [Qemu-arm] " Peter Maydell
2015-12-17 19:31     ` [Qemu-devel] " Peter Maydell
2015-12-03  0:18 ` [Qemu-devel] [PATCH v2 14/26] armv7m: prevent unprivileged write to STIR Michael Davidsaver
2015-12-17 19:33   ` [Qemu-arm] " Peter Maydell
2015-12-17 19:33     ` [Qemu-devel] " Peter Maydell
2015-12-03  0:18 ` [Qemu-devel] [PATCH v2 15/26] armv7m: add MPU to cortex-m3 and cortex-m4 Michael Davidsaver
2015-12-03  0:18 ` [Qemu-devel] [PATCH v2 16/26] armv7m: add some mpu debugging prints Michael Davidsaver
2015-12-03  0:18 ` [Qemu-devel] [PATCH v2 17/26] armv7m: mpu background miss is perm fault Michael Davidsaver
2015-12-03  0:18 ` [Qemu-devel] [PATCH v2 18/26] armv7m: update base region policy Michael Davidsaver
2015-12-03  0:18 ` [Qemu-devel] [PATCH v2 19/26] armv7m: mpu not allowed to map exception return codes Michael Davidsaver
2015-12-03  0:18 ` [Qemu-devel] [PATCH v2 20/26] armv7m: observable initial register state Michael Davidsaver
2015-12-03  0:18 ` [Qemu-devel] [PATCH v2 21/26] armv7m: CONTROL<1> handling Michael Davidsaver
2015-12-03  0:18 ` [Qemu-devel] [PATCH v2 22/26] armv7m: priority field mask Michael Davidsaver
2015-12-03  0:18 ` [Qemu-devel] [PATCH v2 23/26] qom: add cpu_generic_init_unrealized() Michael Davidsaver
2015-12-03  0:18 ` [Qemu-devel] [PATCH v2 24/26] armv7m: split armv7m_init in two parts Michael Davidsaver
2015-12-03  0:18 ` [Qemu-devel] [PATCH v2 25/26] armv7m: remove extra cpu_reset() Michael Davidsaver
2015-12-03  0:18 ` [Qemu-arm] [PATCH v2 26/26] armv7m: decide whether faults are MemManage or BusFault Michael Davidsaver
2015-12-03  0:18   ` [Qemu-devel] " Michael Davidsaver
2015-12-17 19:38 ` [Qemu-devel] [PATCH v2 00/26] armv7m: exception handling, MPU, and more Peter Maydell

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