* [PATCH] mips: scache: fix scache init with invalid line size.
@ 2016-01-18 14:18 ` Govindraj Raja
0 siblings, 0 replies; 6+ messages in thread
From: Govindraj Raja @ 2016-01-18 14:18 UTC (permalink / raw)
To: linux-mips, Ralf Baechle
Cc: Markos Chandras, Paul Burton, Leonid Yegoshin, James Hogan,
James Hartley
In current scache init cache line_size is determined from
cpu config register, however if there there no scache
then mips_sc_probe_cm3 function populates a invalid line_size of 2.
The invalid line_size can cause a NULL pointer deference
during r4k_dma_cache_inv as r4k_blast_scache is populated based on
line_size. Scache line_size of 2 is invalid option in r4k_blast_scache_setup.
This issue was faced during a MIPS I6400 based virtual platform bring up
where scache was not available in virtual platform model.
Signed-off-by: Govindraj Raja <Govindraj.Raja@imgtec.com>
---
arch/mips/mm/sc-mips.c | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/arch/mips/mm/sc-mips.c b/arch/mips/mm/sc-mips.c
index 3bd0597..6e422bc 100644
--- a/arch/mips/mm/sc-mips.c
+++ b/arch/mips/mm/sc-mips.c
@@ -168,7 +168,8 @@ static int __init mips_sc_probe_cm3(void)
line_sz = cfg & CM_GCR_L2_CONFIG_LINE_SIZE_MSK;
line_sz >>= CM_GCR_L2_CONFIG_LINE_SIZE_SHF;
- c->scache.linesz = 2 << line_sz;
+ if (line_sz)
+ c->scache.linesz = 2 << line_sz;
assoc = cfg & CM_GCR_L2_CONFIG_ASSOC_MSK;
assoc >>= CM_GCR_L2_CONFIG_ASSOC_SHF;
--
2.5.0
^ permalink raw reply related [flat|nested] 6+ messages in thread
* [PATCH] mips: scache: fix scache init with invalid line size.
@ 2016-01-18 14:18 ` Govindraj Raja
0 siblings, 0 replies; 6+ messages in thread
From: Govindraj Raja @ 2016-01-18 14:18 UTC (permalink / raw)
To: linux-mips, Ralf Baechle
Cc: Markos Chandras, Paul Burton, Leonid Yegoshin, James Hogan,
James Hartley
In current scache init cache line_size is determined from
cpu config register, however if there there no scache
then mips_sc_probe_cm3 function populates a invalid line_size of 2.
The invalid line_size can cause a NULL pointer deference
during r4k_dma_cache_inv as r4k_blast_scache is populated based on
line_size. Scache line_size of 2 is invalid option in r4k_blast_scache_setup.
This issue was faced during a MIPS I6400 based virtual platform bring up
where scache was not available in virtual platform model.
Signed-off-by: Govindraj Raja <Govindraj.Raja@imgtec.com>
---
arch/mips/mm/sc-mips.c | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/arch/mips/mm/sc-mips.c b/arch/mips/mm/sc-mips.c
index 3bd0597..6e422bc 100644
--- a/arch/mips/mm/sc-mips.c
+++ b/arch/mips/mm/sc-mips.c
@@ -168,7 +168,8 @@ static int __init mips_sc_probe_cm3(void)
line_sz = cfg & CM_GCR_L2_CONFIG_LINE_SIZE_MSK;
line_sz >>= CM_GCR_L2_CONFIG_LINE_SIZE_SHF;
- c->scache.linesz = 2 << line_sz;
+ if (line_sz)
+ c->scache.linesz = 2 << line_sz;
assoc = cfg & CM_GCR_L2_CONFIG_ASSOC_MSK;
assoc >>= CM_GCR_L2_CONFIG_ASSOC_SHF;
--
2.5.0
^ permalink raw reply related [flat|nested] 6+ messages in thread
* Re: [PATCH] mips: scache: fix scache init with invalid line size.
@ 2016-01-18 15:05 ` James Hogan
0 siblings, 0 replies; 6+ messages in thread
From: James Hogan @ 2016-01-18 15:05 UTC (permalink / raw)
To: Govindraj Raja
Cc: linux-mips, Ralf Baechle, Markos Chandras, Paul Burton,
Leonid Yegoshin, James Hartley
[-- Attachment #1: Type: text/plain, Size: 1451 bytes --]
Hi Govindraj,
On Mon, Jan 18, 2016 at 02:18:26PM +0000, Govindraj Raja wrote:
> In current scache init cache line_size is determined from
> cpu config register, however if there there no scache
> then mips_sc_probe_cm3 function populates a invalid line_size of 2.
>
> The invalid line_size can cause a NULL pointer deference
> during r4k_dma_cache_inv as r4k_blast_scache is populated based on
> line_size. Scache line_size of 2 is invalid option in r4k_blast_scache_setup.
>
> This issue was faced during a MIPS I6400 based virtual platform bring up
> where scache was not available in virtual platform model.
>
> Signed-off-by: Govindraj Raja <Govindraj.Raja@imgtec.com>
> ---
> arch/mips/mm/sc-mips.c | 3 ++-
> 1 file changed, 2 insertions(+), 1 deletion(-)
>
> diff --git a/arch/mips/mm/sc-mips.c b/arch/mips/mm/sc-mips.c
> index 3bd0597..6e422bc 100644
> --- a/arch/mips/mm/sc-mips.c
> +++ b/arch/mips/mm/sc-mips.c
> @@ -168,7 +168,8 @@ static int __init mips_sc_probe_cm3(void)
>
> line_sz = cfg & CM_GCR_L2_CONFIG_LINE_SIZE_MSK;
> line_sz >>= CM_GCR_L2_CONFIG_LINE_SIZE_SHF;
> - c->scache.linesz = 2 << line_sz;
> + if (line_sz)
> + c->scache.linesz = 2 << line_sz;
It seems wrong to clear MIPS_CACHE_NOT_PRESENT if we know there isn't a
cache actually present.
Cheers
James
>
> assoc = cfg & CM_GCR_L2_CONFIG_ASSOC_MSK;
> assoc >>= CM_GCR_L2_CONFIG_ASSOC_SHF;
> --
> 2.5.0
>
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^ permalink raw reply [flat|nested] 6+ messages in thread
* Re: [PATCH] mips: scache: fix scache init with invalid line size.
@ 2016-01-18 15:05 ` James Hogan
0 siblings, 0 replies; 6+ messages in thread
From: James Hogan @ 2016-01-18 15:05 UTC (permalink / raw)
To: Govindraj Raja
Cc: linux-mips, Ralf Baechle, Markos Chandras, Paul Burton,
Leonid Yegoshin, James Hartley
[-- Attachment #1: Type: text/plain, Size: 1451 bytes --]
Hi Govindraj,
On Mon, Jan 18, 2016 at 02:18:26PM +0000, Govindraj Raja wrote:
> In current scache init cache line_size is determined from
> cpu config register, however if there there no scache
> then mips_sc_probe_cm3 function populates a invalid line_size of 2.
>
> The invalid line_size can cause a NULL pointer deference
> during r4k_dma_cache_inv as r4k_blast_scache is populated based on
> line_size. Scache line_size of 2 is invalid option in r4k_blast_scache_setup.
>
> This issue was faced during a MIPS I6400 based virtual platform bring up
> where scache was not available in virtual platform model.
>
> Signed-off-by: Govindraj Raja <Govindraj.Raja@imgtec.com>
> ---
> arch/mips/mm/sc-mips.c | 3 ++-
> 1 file changed, 2 insertions(+), 1 deletion(-)
>
> diff --git a/arch/mips/mm/sc-mips.c b/arch/mips/mm/sc-mips.c
> index 3bd0597..6e422bc 100644
> --- a/arch/mips/mm/sc-mips.c
> +++ b/arch/mips/mm/sc-mips.c
> @@ -168,7 +168,8 @@ static int __init mips_sc_probe_cm3(void)
>
> line_sz = cfg & CM_GCR_L2_CONFIG_LINE_SIZE_MSK;
> line_sz >>= CM_GCR_L2_CONFIG_LINE_SIZE_SHF;
> - c->scache.linesz = 2 << line_sz;
> + if (line_sz)
> + c->scache.linesz = 2 << line_sz;
It seems wrong to clear MIPS_CACHE_NOT_PRESENT if we know there isn't a
cache actually present.
Cheers
James
>
> assoc = cfg & CM_GCR_L2_CONFIG_ASSOC_MSK;
> assoc >>= CM_GCR_L2_CONFIG_ASSOC_SHF;
> --
> 2.5.0
>
[-- Attachment #2: Digital signature --]
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^ permalink raw reply [flat|nested] 6+ messages in thread
* Re: [PATCH] mips: scache: fix scache init with invalid line size.
@ 2016-01-19 15:34 ` Govindraj Raja
0 siblings, 0 replies; 6+ messages in thread
From: Govindraj Raja @ 2016-01-19 15:34 UTC (permalink / raw)
To: James Hogan
Cc: linux-mips, Ralf Baechle, Markos Chandras, Paul Burton,
Leonid Yegoshin, James Hartley
Hi James,
On 18/01/16 15:05, James Hogan wrote:
> Hi Govindraj,
>
> On Mon, Jan 18, 2016 at 02:18:26PM +0000, Govindraj Raja wrote:
>> In current scache init cache line_size is determined from
>> cpu config register, however if there there no scache
>> then mips_sc_probe_cm3 function populates a invalid line_size of 2.
>>
>> The invalid line_size can cause a NULL pointer deference
>> during r4k_dma_cache_inv as r4k_blast_scache is populated based on
>> line_size. Scache line_size of 2 is invalid option in r4k_blast_scache_setup.
>>
>> This issue was faced during a MIPS I6400 based virtual platform bring up
>> where scache was not available in virtual platform model.
>>
>> Signed-off-by: Govindraj Raja <Govindraj.Raja@imgtec.com>
>> ---
>> arch/mips/mm/sc-mips.c | 3 ++-
>> 1 file changed, 2 insertions(+), 1 deletion(-)
>>
>> diff --git a/arch/mips/mm/sc-mips.c b/arch/mips/mm/sc-mips.c
>> index 3bd0597..6e422bc 100644
>> --- a/arch/mips/mm/sc-mips.c
>> +++ b/arch/mips/mm/sc-mips.c
>> @@ -168,7 +168,8 @@ static int __init mips_sc_probe_cm3(void)
>>
>> line_sz = cfg & CM_GCR_L2_CONFIG_LINE_SIZE_MSK;
>> line_sz >>= CM_GCR_L2_CONFIG_LINE_SIZE_SHF;
>> - c->scache.linesz = 2 << line_sz;
>> + if (line_sz)
>> + c->scache.linesz = 2 << line_sz;
> It seems wrong to clear MIPS_CACHE_NOT_PRESENT if we know there isn't a
> cache actually present.
>
> Cheers
> James
>
>
Does this patch[1] makes sense?
I will repost v2 is its ok?
--
Thanks,
Govindraj.R
[1]:
diff --git a/arch/mips/mm/sc-mips.c b/arch/mips/mm/sc-mips.c
index 3bd0597..68c48f4 100644
--- a/arch/mips/mm/sc-mips.c
+++ b/arch/mips/mm/sc-mips.c
@@ -164,11 +164,13 @@ static int __init mips_sc_probe_cm3(void)
sets = cfg & CM_GCR_L2_CONFIG_SET_SIZE_MSK;
sets >>= CM_GCR_L2_CONFIG_SET_SIZE_SHF;
- c->scache.sets = 64 << sets;
+ if (sets)
+ c->scache.sets = 64 << sets;
line_sz = cfg & CM_GCR_L2_CONFIG_LINE_SIZE_MSK;
line_sz >>= CM_GCR_L2_CONFIG_LINE_SIZE_SHF;
- c->scache.linesz = 2 << line_sz;
+ if (line_sz)
+ c->scache.linesz = 2 << line_sz;
assoc = cfg & CM_GCR_L2_CONFIG_ASSOC_MSK;
assoc >>= CM_GCR_L2_CONFIG_ASSOC_SHF;
@@ -176,7 +178,8 @@ static int __init mips_sc_probe_cm3(void)
c->scache.waysize = c->scache.sets * c->scache.linesz;
c->scache.waybit = __ffs(c->scache.waysize);
- c->scache.flags &= ~MIPS_CACHE_NOT_PRESENT;
+ if (c->scache.linesz)
+ c->scache.flags &= ~MIPS_CACHE_NOT_PRESENT;
return 1;
}
^ permalink raw reply related [flat|nested] 6+ messages in thread* Re: [PATCH] mips: scache: fix scache init with invalid line size.
@ 2016-01-19 15:34 ` Govindraj Raja
0 siblings, 0 replies; 6+ messages in thread
From: Govindraj Raja @ 2016-01-19 15:34 UTC (permalink / raw)
To: James Hogan
Cc: linux-mips, Ralf Baechle, Markos Chandras, Paul Burton,
Leonid Yegoshin, James Hartley
Hi James,
On 18/01/16 15:05, James Hogan wrote:
> Hi Govindraj,
>
> On Mon, Jan 18, 2016 at 02:18:26PM +0000, Govindraj Raja wrote:
>> In current scache init cache line_size is determined from
>> cpu config register, however if there there no scache
>> then mips_sc_probe_cm3 function populates a invalid line_size of 2.
>>
>> The invalid line_size can cause a NULL pointer deference
>> during r4k_dma_cache_inv as r4k_blast_scache is populated based on
>> line_size. Scache line_size of 2 is invalid option in r4k_blast_scache_setup.
>>
>> This issue was faced during a MIPS I6400 based virtual platform bring up
>> where scache was not available in virtual platform model.
>>
>> Signed-off-by: Govindraj Raja <Govindraj.Raja@imgtec.com>
>> ---
>> arch/mips/mm/sc-mips.c | 3 ++-
>> 1 file changed, 2 insertions(+), 1 deletion(-)
>>
>> diff --git a/arch/mips/mm/sc-mips.c b/arch/mips/mm/sc-mips.c
>> index 3bd0597..6e422bc 100644
>> --- a/arch/mips/mm/sc-mips.c
>> +++ b/arch/mips/mm/sc-mips.c
>> @@ -168,7 +168,8 @@ static int __init mips_sc_probe_cm3(void)
>>
>> line_sz = cfg & CM_GCR_L2_CONFIG_LINE_SIZE_MSK;
>> line_sz >>= CM_GCR_L2_CONFIG_LINE_SIZE_SHF;
>> - c->scache.linesz = 2 << line_sz;
>> + if (line_sz)
>> + c->scache.linesz = 2 << line_sz;
> It seems wrong to clear MIPS_CACHE_NOT_PRESENT if we know there isn't a
> cache actually present.
>
> Cheers
> James
>
>
Does this patch[1] makes sense?
I will repost v2 is its ok?
--
Thanks,
Govindraj.R
[1]:
diff --git a/arch/mips/mm/sc-mips.c b/arch/mips/mm/sc-mips.c
index 3bd0597..68c48f4 100644
--- a/arch/mips/mm/sc-mips.c
+++ b/arch/mips/mm/sc-mips.c
@@ -164,11 +164,13 @@ static int __init mips_sc_probe_cm3(void)
sets = cfg & CM_GCR_L2_CONFIG_SET_SIZE_MSK;
sets >>= CM_GCR_L2_CONFIG_SET_SIZE_SHF;
- c->scache.sets = 64 << sets;
+ if (sets)
+ c->scache.sets = 64 << sets;
line_sz = cfg & CM_GCR_L2_CONFIG_LINE_SIZE_MSK;
line_sz >>= CM_GCR_L2_CONFIG_LINE_SIZE_SHF;
- c->scache.linesz = 2 << line_sz;
+ if (line_sz)
+ c->scache.linesz = 2 << line_sz;
assoc = cfg & CM_GCR_L2_CONFIG_ASSOC_MSK;
assoc >>= CM_GCR_L2_CONFIG_ASSOC_SHF;
@@ -176,7 +178,8 @@ static int __init mips_sc_probe_cm3(void)
c->scache.waysize = c->scache.sets * c->scache.linesz;
c->scache.waybit = __ffs(c->scache.waysize);
- c->scache.flags &= ~MIPS_CACHE_NOT_PRESENT;
+ if (c->scache.linesz)
+ c->scache.flags &= ~MIPS_CACHE_NOT_PRESENT;
return 1;
}
^ permalink raw reply related [flat|nested] 6+ messages in thread
end of thread, other threads:[~2016-01-19 15:34 UTC | newest]
Thread overview: 6+ messages (download: mbox.gz follow: Atom feed
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2016-01-18 14:18 [PATCH] mips: scache: fix scache init with invalid line size Govindraj Raja
2016-01-18 14:18 ` Govindraj Raja
2016-01-18 15:05 ` James Hogan
2016-01-18 15:05 ` James Hogan
2016-01-19 15:34 ` Govindraj Raja
2016-01-19 15:34 ` Govindraj Raja
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