From: Sergey Fedorov <serge.fdrv@gmail.com>
To: Peter Maydell <peter.maydell@linaro.org>, qemu-devel@nongnu.org
Cc: qemu-arm@nongnu.org, patches@linaro.org
Subject: Re: [Qemu-arm] [Qemu-devel] [PATCH 1/6] target-arm: correct CNTFRQ access rights
Date: Mon, 8 Feb 2016 18:25:26 +0300 [thread overview]
Message-ID: <56B8B366.1040203@gmail.com> (raw)
In-Reply-To: <1454690704-16233-2-git-send-email-peter.maydell@linaro.org>
On 05.02.2016 19:44, Peter Maydell wrote:
> Correct some corner cases we were getting wrong for
> CNTFRQ access rights:
> * should UNDEF from 32-bit Secure EL1
> * only writable from the highest implemented exception level,
> which might not be EL1 now
>
> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
> ---
> target-arm/helper.c | 31 ++++++++++++++++++++++++++++---
> 1 file changed, 28 insertions(+), 3 deletions(-)
>
> diff --git a/target-arm/helper.c b/target-arm/helper.c
> index 7a8881a..082701a 100644
> --- a/target-arm/helper.c
> +++ b/target-arm/helper.c
> @@ -1217,9 +1217,34 @@ static const ARMCPRegInfo v6k_cp_reginfo[] = {
> static CPAccessResult gt_cntfrq_access(CPUARMState *env, const ARMCPRegInfo *ri,
> bool isread)
> {
> - /* CNTFRQ: not visible from PL0 if both PL0PCTEN and PL0VCTEN are zero */
> - if (arm_current_el(env) == 0 && !extract32(env->cp15.c14_cntkctl, 0, 2)) {
> - return CP_ACCESS_TRAP;
> + /* CNTFRQ: not visible from PL0 if both PL0PCTEN and PL0VCTEN are zero.
> + * Writable only at the highest implemented exception level.
> + */
> + switch (arm_current_el(env)) {
> + case 0:
> + if (!extract32(env->cp15.c14_cntkctl, 0, 2)) {
> + return CP_ACCESS_TRAP;
> + }
> + /* EL0 reads are forbidden by the .access fields */
s/reads/writes/ ?
> + break;
> + case 1:
> + if (!isread && (arm_feature(env, ARM_FEATURE_EL2)
> + || arm_feature(env, ARM_FEATURE_EL3))) {
> + return CP_ACCESS_TRAP_UNCATEGORIZED;
> + }
> + if (!isread && ri->state == ARM_CP_STATE_AA32 &&
> + arm_is_secure_below_el3(env)) {
> + /* Accesses from 32-bit Secure EL1 UNDEF (*not* trap to EL3!) */
> + return CP_ACCESS_TRAP_UNCATEGORIZED;
> + }
> + break;
> + case 2:
> + if (!isread && arm_feature(env, ARM_FEATURE_EL3)) {
> + return CP_ACCESS_TRAP_UNCATEGORIZED;
> + }
> + break;
> + case 3:
> + break;
> }
> return CP_ACCESS_OK;
> }
Maybe calculating "the highest implemented exception level" could
simplify reading of the code a bit? E.g.:
int highest_el = arm_feature(env, ARM_FEATURE_EL3) ? 3 :
arm_feature(env, ARM_FEATURE_EL2) ? 2 : 1;
We would probably want to have a dedicated static inline function for
this similar to HighestEL() from ARMv8 ARM pseudocode.
Kind regards,
Sergey
WARNING: multiple messages have this Message-ID (diff)
From: Sergey Fedorov <serge.fdrv@gmail.com>
To: Peter Maydell <peter.maydell@linaro.org>, qemu-devel@nongnu.org
Cc: "Edgar E. Iglesias" <edgar.iglesias@gmail.com>,
qemu-arm@nongnu.org, patches@linaro.org
Subject: Re: [Qemu-devel] [PATCH 1/6] target-arm: correct CNTFRQ access rights
Date: Mon, 8 Feb 2016 18:25:26 +0300 [thread overview]
Message-ID: <56B8B366.1040203@gmail.com> (raw)
In-Reply-To: <1454690704-16233-2-git-send-email-peter.maydell@linaro.org>
On 05.02.2016 19:44, Peter Maydell wrote:
> Correct some corner cases we were getting wrong for
> CNTFRQ access rights:
> * should UNDEF from 32-bit Secure EL1
> * only writable from the highest implemented exception level,
> which might not be EL1 now
>
> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
> ---
> target-arm/helper.c | 31 ++++++++++++++++++++++++++++---
> 1 file changed, 28 insertions(+), 3 deletions(-)
>
> diff --git a/target-arm/helper.c b/target-arm/helper.c
> index 7a8881a..082701a 100644
> --- a/target-arm/helper.c
> +++ b/target-arm/helper.c
> @@ -1217,9 +1217,34 @@ static const ARMCPRegInfo v6k_cp_reginfo[] = {
> static CPAccessResult gt_cntfrq_access(CPUARMState *env, const ARMCPRegInfo *ri,
> bool isread)
> {
> - /* CNTFRQ: not visible from PL0 if both PL0PCTEN and PL0VCTEN are zero */
> - if (arm_current_el(env) == 0 && !extract32(env->cp15.c14_cntkctl, 0, 2)) {
> - return CP_ACCESS_TRAP;
> + /* CNTFRQ: not visible from PL0 if both PL0PCTEN and PL0VCTEN are zero.
> + * Writable only at the highest implemented exception level.
> + */
> + switch (arm_current_el(env)) {
> + case 0:
> + if (!extract32(env->cp15.c14_cntkctl, 0, 2)) {
> + return CP_ACCESS_TRAP;
> + }
> + /* EL0 reads are forbidden by the .access fields */
s/reads/writes/ ?
> + break;
> + case 1:
> + if (!isread && (arm_feature(env, ARM_FEATURE_EL2)
> + || arm_feature(env, ARM_FEATURE_EL3))) {
> + return CP_ACCESS_TRAP_UNCATEGORIZED;
> + }
> + if (!isread && ri->state == ARM_CP_STATE_AA32 &&
> + arm_is_secure_below_el3(env)) {
> + /* Accesses from 32-bit Secure EL1 UNDEF (*not* trap to EL3!) */
> + return CP_ACCESS_TRAP_UNCATEGORIZED;
> + }
> + break;
> + case 2:
> + if (!isread && arm_feature(env, ARM_FEATURE_EL3)) {
> + return CP_ACCESS_TRAP_UNCATEGORIZED;
> + }
> + break;
> + case 3:
> + break;
> }
> return CP_ACCESS_OK;
> }
Maybe calculating "the highest implemented exception level" could
simplify reading of the code a bit? E.g.:
int highest_el = arm_feature(env, ARM_FEATURE_EL3) ? 3 :
arm_feature(env, ARM_FEATURE_EL2) ? 2 : 1;
We would probably want to have a dedicated static inline function for
this similar to HighestEL() from ARMv8 ARM pseudocode.
Kind regards,
Sergey
next prev parent reply other threads:[~2016-02-08 15:27 UTC|newest]
Thread overview: 27+ messages / expand[flat|nested] mbox.gz Atom feed top
2016-02-05 16:44 [Qemu-devel] [PATCH 0/6] target-arm: Implement various EL3 traps Peter Maydell
2016-02-05 16:44 ` [Qemu-devel] [PATCH 1/6] target-arm: correct CNTFRQ access rights Peter Maydell
2016-02-08 15:25 ` Sergey Fedorov [this message]
2016-02-08 15:25 ` Sergey Fedorov
2016-02-08 15:30 ` [Qemu-arm] " Peter Maydell
2016-02-08 15:30 ` Peter Maydell
2016-02-05 16:45 ` [Qemu-arm] [PATCH 2/6] target-arm: Fix handling of SCR.SMD Peter Maydell
2016-02-05 16:45 ` [Qemu-devel] " Peter Maydell
2016-02-08 15:40 ` [Qemu-arm] " Sergey Fedorov
2016-02-08 15:40 ` [Qemu-devel] " Sergey Fedorov
2016-02-05 16:45 ` [Qemu-arm] [PATCH 3/6] target-arm: Implement MDCR_EL3.TDOSA and MDCR_EL2.TDOSA traps Peter Maydell
2016-02-05 16:45 ` [Qemu-devel] " Peter Maydell
2016-02-08 15:49 ` [Qemu-arm] " Sergey Fedorov
2016-02-08 15:49 ` [Qemu-devel] " Sergey Fedorov
2016-02-05 16:45 ` [Qemu-devel] [PATCH 4/6] target-arm: Implement MDCR_EL2.TDRA traps Peter Maydell
2016-02-08 15:56 ` [Qemu-arm] " Sergey Fedorov
2016-02-08 15:56 ` Sergey Fedorov
2016-02-05 16:45 ` [Qemu-devel] [PATCH 5/6] target-arm: Implement MDCR_EL2.TDA and MDCR_EL2.TDA traps Peter Maydell
2016-02-08 16:31 ` [Qemu-arm] " Sergey Fedorov
2016-02-08 16:31 ` Sergey Fedorov
2016-02-08 16:38 ` [Qemu-arm] " Peter Maydell
2016-02-08 16:38 ` Peter Maydell
2016-02-08 16:44 ` [Qemu-arm] " Sergey Fedorov
2016-02-08 16:44 ` Sergey Fedorov
2016-02-05 16:45 ` [Qemu-devel] [PATCH 6/6] target-arm: Report correct syndrome for FPEXC32_EL2 traps Peter Maydell
2016-02-08 16:40 ` [Qemu-arm] " Sergey Fedorov
2016-02-08 16:40 ` Sergey Fedorov
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