From: Sergey Fedorov <serge.fdrv@gmail.com>
To: Peter Maydell <peter.maydell@linaro.org>, qemu-devel@nongnu.org
Cc: qemu-arm@nongnu.org, patches@linaro.org
Subject: Re: [Qemu-arm] [PATCH 4/4] target-arm: UNDEF in the UNPREDICTABLE SRS-from-System case
Date: Fri, 12 Feb 2016 12:34:46 +0300 [thread overview]
Message-ID: <56BDA736.3070008@gmail.com> (raw)
In-Reply-To: <1455217909-28317-5-git-send-email-peter.maydell@linaro.org>
On 11.02.2016 22:11, Peter Maydell wrote:
> Make get_r13_banked() raise an exception at runtime for the
> corner case of SRS from System mode, so that we can UNDEF it;
> this brings us in to line with the ARM ARM's set of permitted
> CONSTRAINED UNPREDICTABLE choices.
>
> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
It's a bit misleading that the name "get_r13_banked" says nothing about
SRS instruction but raises an SRS-specific exception. Though, it's only
used for SRS and there seems to be no other candidate to use it; so
Reviewed-by: Sergey Fedorov <serge.fdrv@gmail.com>
> ---
> target-arm/op_helper.c | 8 ++++++++
> target-arm/translate.c | 9 +++++----
> 2 files changed, 13 insertions(+), 4 deletions(-)
>
> diff --git a/target-arm/op_helper.c b/target-arm/op_helper.c
> index 05f97a7..8183108 100644
> --- a/target-arm/op_helper.c
> +++ b/target-arm/op_helper.c
> @@ -474,6 +474,14 @@ uint32_t HELPER(get_r13_banked)(CPUARMState *env, uint32_t mode)
> #if defined(CONFIG_USER_ONLY)
> g_assert_not_reached();
> #endif
> + if ((env->uncached_cpsr & CPSR_M) == ARM_CPU_MODE_SYS) {
> + /* SRS instruction is UNPREDICTABLE from System mode; we UNDEF.
> + * Other UNPREDICTABLE and UNDEF cases were caught at translate time.
> + */
> + raise_exception(env, EXCP_UDEF, syn_uncategorized(),
> + exception_target_el(env));
> + }
> +
> if ((env->uncached_cpsr & CPSR_M) == mode) {
> return env->regs[13];
> } else {
> diff --git a/target-arm/translate.c b/target-arm/translate.c
> index 7bceb05..e69145d 100644
> --- a/target-arm/translate.c
> +++ b/target-arm/translate.c
> @@ -7590,10 +7590,7 @@ static void gen_srs(DisasContext *s,
> * -- not a valid mode number
> * -- a mode that's at a higher exception level
> * -- Monitor, if we are Non-secure
> - * For the UNPREDICTABLE cases we choose to UNDEF, except that for
> - * "current mode is System" we will write a garbage SPSR.
> - * (This is because we don't have access to our current mode here
> - * and would have to do a runtime check to UNDEF for System.)
> + * For the UNPREDICTABLE cases we choose to UNDEF.
> */
> if (s->current_el == 1 && !s->ns) {
> gen_exception_insn(s, 4, EXCP_UDEF, syn_uncategorized(), 3);
> @@ -7639,6 +7636,9 @@ static void gen_srs(DisasContext *s,
>
> addr = tcg_temp_new_i32();
> tmp = tcg_const_i32(mode);
> + /* get_r13_banked() will raise an exception if called from System mode */
> + gen_set_condexec(s);
> + gen_set_pc_im(s, s->pc - 4);
> gen_helper_get_r13_banked(addr, cpu_env, tmp);
> tcg_temp_free_i32(tmp);
> switch (amode) {
> @@ -7688,6 +7688,7 @@ static void gen_srs(DisasContext *s,
> tcg_temp_free_i32(tmp);
> }
> tcg_temp_free_i32(addr);
> + s->is_jmp = DISAS_UPDATE;
> }
>
> static void disas_arm_insn(DisasContext *s, unsigned int insn)
WARNING: multiple messages have this Message-ID (diff)
From: Sergey Fedorov <serge.fdrv@gmail.com>
To: Peter Maydell <peter.maydell@linaro.org>, qemu-devel@nongnu.org
Cc: "Edgar E. Iglesias" <edgar.iglesias@gmail.com>,
qemu-arm@nongnu.org, patches@linaro.org
Subject: Re: [Qemu-devel] [PATCH 4/4] target-arm: UNDEF in the UNPREDICTABLE SRS-from-System case
Date: Fri, 12 Feb 2016 12:34:46 +0300 [thread overview]
Message-ID: <56BDA736.3070008@gmail.com> (raw)
In-Reply-To: <1455217909-28317-5-git-send-email-peter.maydell@linaro.org>
On 11.02.2016 22:11, Peter Maydell wrote:
> Make get_r13_banked() raise an exception at runtime for the
> corner case of SRS from System mode, so that we can UNDEF it;
> this brings us in to line with the ARM ARM's set of permitted
> CONSTRAINED UNPREDICTABLE choices.
>
> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
It's a bit misleading that the name "get_r13_banked" says nothing about
SRS instruction but raises an SRS-specific exception. Though, it's only
used for SRS and there seems to be no other candidate to use it; so
Reviewed-by: Sergey Fedorov <serge.fdrv@gmail.com>
> ---
> target-arm/op_helper.c | 8 ++++++++
> target-arm/translate.c | 9 +++++----
> 2 files changed, 13 insertions(+), 4 deletions(-)
>
> diff --git a/target-arm/op_helper.c b/target-arm/op_helper.c
> index 05f97a7..8183108 100644
> --- a/target-arm/op_helper.c
> +++ b/target-arm/op_helper.c
> @@ -474,6 +474,14 @@ uint32_t HELPER(get_r13_banked)(CPUARMState *env, uint32_t mode)
> #if defined(CONFIG_USER_ONLY)
> g_assert_not_reached();
> #endif
> + if ((env->uncached_cpsr & CPSR_M) == ARM_CPU_MODE_SYS) {
> + /* SRS instruction is UNPREDICTABLE from System mode; we UNDEF.
> + * Other UNPREDICTABLE and UNDEF cases were caught at translate time.
> + */
> + raise_exception(env, EXCP_UDEF, syn_uncategorized(),
> + exception_target_el(env));
> + }
> +
> if ((env->uncached_cpsr & CPSR_M) == mode) {
> return env->regs[13];
> } else {
> diff --git a/target-arm/translate.c b/target-arm/translate.c
> index 7bceb05..e69145d 100644
> --- a/target-arm/translate.c
> +++ b/target-arm/translate.c
> @@ -7590,10 +7590,7 @@ static void gen_srs(DisasContext *s,
> * -- not a valid mode number
> * -- a mode that's at a higher exception level
> * -- Monitor, if we are Non-secure
> - * For the UNPREDICTABLE cases we choose to UNDEF, except that for
> - * "current mode is System" we will write a garbage SPSR.
> - * (This is because we don't have access to our current mode here
> - * and would have to do a runtime check to UNDEF for System.)
> + * For the UNPREDICTABLE cases we choose to UNDEF.
> */
> if (s->current_el == 1 && !s->ns) {
> gen_exception_insn(s, 4, EXCP_UDEF, syn_uncategorized(), 3);
> @@ -7639,6 +7636,9 @@ static void gen_srs(DisasContext *s,
>
> addr = tcg_temp_new_i32();
> tmp = tcg_const_i32(mode);
> + /* get_r13_banked() will raise an exception if called from System mode */
> + gen_set_condexec(s);
> + gen_set_pc_im(s, s->pc - 4);
> gen_helper_get_r13_banked(addr, cpu_env, tmp);
> tcg_temp_free_i32(tmp);
> switch (amode) {
> @@ -7688,6 +7688,7 @@ static void gen_srs(DisasContext *s,
> tcg_temp_free_i32(tmp);
> }
> tcg_temp_free_i32(addr);
> + s->is_jmp = DISAS_UPDATE;
> }
>
> static void disas_arm_insn(DisasContext *s, unsigned int insn)
next prev parent reply other threads:[~2016-02-12 9:34 UTC|newest]
Thread overview: 34+ messages / expand[flat|nested] mbox.gz Atom feed top
2016-02-11 19:11 [Qemu-arm] [PATCH 0/4] target-arm: Clean up trap/undef handling of SRS Peter Maydell
2016-02-11 19:11 ` [Qemu-devel] " Peter Maydell
2016-02-11 19:11 ` [Qemu-arm] [PATCH 1/4] " Peter Maydell
2016-02-11 19:11 ` [Qemu-devel] " Peter Maydell
2016-02-12 8:48 ` [Qemu-arm] " Sergey Fedorov
2016-02-12 8:48 ` [Qemu-devel] " Sergey Fedorov
2016-02-12 14:56 ` Edgar E. Iglesias
2016-02-11 19:11 ` [Qemu-arm] [PATCH 2/4] target-arm: Move get/set_r13_banked() to op_helper.c Peter Maydell
2016-02-11 19:11 ` [Qemu-devel] " Peter Maydell
2016-02-12 8:56 ` [Qemu-arm] " Sergey Fedorov
2016-02-12 8:56 ` [Qemu-devel] " Sergey Fedorov
2016-02-12 15:05 ` [Qemu-arm] " Edgar E. Iglesias
2016-02-12 15:05 ` [Qemu-devel] " Edgar E. Iglesias
2016-02-11 19:11 ` [Qemu-arm] [PATCH 3/4] target-arm: Combine user-only and softmmu get/set_r13_banked() Peter Maydell
2016-02-11 19:11 ` [Qemu-devel] " Peter Maydell
2016-02-12 8:58 ` [Qemu-arm] " Sergey Fedorov
2016-02-12 8:58 ` [Qemu-devel] " Sergey Fedorov
2016-02-12 15:12 ` [Qemu-arm] " Edgar E. Iglesias
2016-02-12 15:12 ` [Qemu-devel] " Edgar E. Iglesias
2016-02-12 15:15 ` [Qemu-arm] " Peter Maydell
2016-02-12 15:15 ` [Qemu-devel] " Peter Maydell
2016-02-12 15:16 ` Edgar E. Iglesias
2016-02-12 15:48 ` [Qemu-arm] " Sergey Fedorov
2016-02-12 15:48 ` [Qemu-devel] " Sergey Fedorov
2016-02-12 15:49 ` [Qemu-arm] " Peter Maydell
2016-02-12 15:49 ` [Qemu-devel] " Peter Maydell
2016-02-12 15:15 ` [Qemu-arm] " Edgar E. Iglesias
2016-02-12 15:15 ` [Qemu-devel] " Edgar E. Iglesias
2016-02-11 19:11 ` [Qemu-arm] [PATCH 4/4] target-arm: UNDEF in the UNPREDICTABLE SRS-from-System case Peter Maydell
2016-02-11 19:11 ` [Qemu-devel] " Peter Maydell
2016-02-12 9:34 ` Sergey Fedorov [this message]
2016-02-12 9:34 ` Sergey Fedorov
2016-02-12 15:17 ` [Qemu-arm] " Edgar E. Iglesias
2016-02-12 15:17 ` [Qemu-devel] " Edgar E. Iglesias
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