From: Xing Zheng <zhengxing-TNX95d0MmH7DzftRWevZcw@public.gmane.org>
To: Heiko Stuebner <heiko-4mtYJXux2i+zQB+pC5nmwQ@public.gmane.org>
Cc: linux-rockchip-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r@public.gmane.org,
huangtao-TNX95d0MmH7DzftRWevZcw@public.gmane.org,
jay.xu-TNX95d0MmH7DzftRWevZcw@public.gmane.org,
elaine.zhang-TNX95d0MmH7DzftRWevZcw@public.gmane.org,
dianders-F7+t8E8rja9g9hUCZPvPmw@public.gmane.org,
Rob Herring <robh+dt-DgEjT+Ai2ygdnm+yROfE0A@public.gmane.org>,
Pawel Moll <pawel.moll-5wv7dgnIgG8@public.gmane.org>,
Mark Rutland <mark.rutland-5wv7dgnIgG8@public.gmane.org>,
Ian Campbell
<ijc+devicetree-KcIKpvwj1kUDXYZnReoRVg@public.gmane.org>,
Kumar Gala <galak-sgV2jX0FEOL9JmXXK+q4OQ@public.gmane.org>,
Stephen Boyd <sboyd-sgV2jX0FEOL9JmXXK+q4OQ@public.gmane.org>,
devicetree-u79uwXL29TY76Z2rM5mHXA@public.gmane.org,
linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r@public.gmane.org,
linux-kernel-u79uwXL29TY76Z2rM5mHXA@public.gmane.org
Subject: Re: [PATCH v5 2/4] dt-bindings: add bindings for rk3399 clock controller
Date: Mon, 28 Mar 2016 11:24:47 +0800 [thread overview]
Message-ID: <56F8A3FF.6090800@rock-chips.com> (raw)
In-Reply-To: <3689505.b0IKY6iWOt@phil>
Hi Heiko,
On 2016年03月28日 08:07, Heiko Stuebner wrote:
> Hi Xing,
>
> Am Montag, 28. März 2016, 01:52:12 schrieb Heiko Stübner:
>> Am Samstag, 26. März 2016, 14:37:54 schrieb Xing Zheng:
>>> Add devicetree bindings for Rockchip cru which found on
>>> Rockchip SoCs.
>>>
>>> Signed-off-by: Xing Zheng<zhengxing-TNX95d0MmH7DzftRWevZcw@public.gmane.org>
>>> Signed-off-by: Jianqun Xu<jay.xu-TNX95d0MmH7DzftRWevZcw@public.gmane.org>
>>> Acked-by: Rob Herring<robh-DgEjT+Ai2ygdnm+yROfE0A@public.gmane.org>
>>> ---
>>>
>>> Changes in v5: None
>>> Changes in v3: None
>>> Changes in v2: None
>>>
>>> .../bindings/clock/rockchip,rk3399-cru.txt | 83
>>>
>>> ++++++++++++++++++++ 1 file changed, 83 insertions(+)
>>>
>>> create mode 100644
>>>
>>> Documentation/devicetree/bindings/clock/rockchip,rk3399-cru.txt
>>>
>>> diff --git a/Documentation/devicetree/bindings/clock/rockchip,rk3399-
>> cru.txt
>>
>>> b/Documentation/devicetree/bindings/clock/rockchip,rk3399-cru.txt new
>>> file mode 100644
>>> index 0000000..9427caa
>>> --- /dev/null
>>> +++ b/Documentation/devicetree/bindings/clock/rockchip,rk3399-cru.txt
>>> @@ -0,0 +1,83 @@
>>> +* Rockchip RK3399 Clock and Reset Unit
>>> +
>>> +The RK3399 clock controller generates and supplies clock to various
>>> +controllers within the SoC and also implements a reset controller for
>>> SoC +peripherals.
>>> +
>>> +Required Properties:
>>> +
>>> +- compatible: PMU for CRU should be "rockchip,rk3399-pmucru"
>>> +- compatible: CRU should be "rockchip,rk3399-cru"
>>> +- reg: physical base address of the controller and length of memory
>> mapped
>>
>>> + region.
>>> +- #clock-cells: should be 1.
>>> +- #reset-cells: should be 1.
>>> +
>>> +Optional Properties:
>>> +
>>> +- rockchip,grf: phandle to the syscon managing the "general register
>> files"
>>
>>> + If missing, pll rates are not changeable, due to the missing pll lock
>>> status. +
>> the rk3399 doesn't need the GRF, so we should drop this block for now
> actually, I just saw that the GRF is needed for the static settings during
> init. So the rockchip,grf should stay but also move up to required
> properties?
>
> Same for the grf-comment in the examples-section.
>
>
I check the setting of the pclk_alive and pclk_pmu_src are not gating
default on the PMUGRF_SOC_CON0,
so I think that we don't need to do the static settings to re-enable
them in the clock driver any more.
Thanks.
--
- Xing Zheng
--
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WARNING: multiple messages have this Message-ID (diff)
From: zhengxing@rock-chips.com (Xing Zheng)
To: linux-arm-kernel@lists.infradead.org
Subject: [PATCH v5 2/4] dt-bindings: add bindings for rk3399 clock controller
Date: Mon, 28 Mar 2016 11:24:47 +0800 [thread overview]
Message-ID: <56F8A3FF.6090800@rock-chips.com> (raw)
In-Reply-To: <3689505.b0IKY6iWOt@phil>
Hi Heiko,
On 2016?03?28? 08:07, Heiko Stuebner wrote:
> Hi Xing,
>
> Am Montag, 28. M?rz 2016, 01:52:12 schrieb Heiko St?bner:
>> Am Samstag, 26. M?rz 2016, 14:37:54 schrieb Xing Zheng:
>>> Add devicetree bindings for Rockchip cru which found on
>>> Rockchip SoCs.
>>>
>>> Signed-off-by: Xing Zheng<zhengxing@rock-chips.com>
>>> Signed-off-by: Jianqun Xu<jay.xu@rock-chips.com>
>>> Acked-by: Rob Herring<robh@kernel.org>
>>> ---
>>>
>>> Changes in v5: None
>>> Changes in v3: None
>>> Changes in v2: None
>>>
>>> .../bindings/clock/rockchip,rk3399-cru.txt | 83
>>>
>>> ++++++++++++++++++++ 1 file changed, 83 insertions(+)
>>>
>>> create mode 100644
>>>
>>> Documentation/devicetree/bindings/clock/rockchip,rk3399-cru.txt
>>>
>>> diff --git a/Documentation/devicetree/bindings/clock/rockchip,rk3399-
>> cru.txt
>>
>>> b/Documentation/devicetree/bindings/clock/rockchip,rk3399-cru.txt new
>>> file mode 100644
>>> index 0000000..9427caa
>>> --- /dev/null
>>> +++ b/Documentation/devicetree/bindings/clock/rockchip,rk3399-cru.txt
>>> @@ -0,0 +1,83 @@
>>> +* Rockchip RK3399 Clock and Reset Unit
>>> +
>>> +The RK3399 clock controller generates and supplies clock to various
>>> +controllers within the SoC and also implements a reset controller for
>>> SoC +peripherals.
>>> +
>>> +Required Properties:
>>> +
>>> +- compatible: PMU for CRU should be "rockchip,rk3399-pmucru"
>>> +- compatible: CRU should be "rockchip,rk3399-cru"
>>> +- reg: physical base address of the controller and length of memory
>> mapped
>>
>>> + region.
>>> +- #clock-cells: should be 1.
>>> +- #reset-cells: should be 1.
>>> +
>>> +Optional Properties:
>>> +
>>> +- rockchip,grf: phandle to the syscon managing the "general register
>> files"
>>
>>> + If missing, pll rates are not changeable, due to the missing pll lock
>>> status. +
>> the rk3399 doesn't need the GRF, so we should drop this block for now
> actually, I just saw that the GRF is needed for the static settings during
> init. So the rockchip,grf should stay but also move up to required
> properties?
>
> Same for the grf-comment in the examples-section.
>
>
I check the setting of the pclk_alive and pclk_pmu_src are not gating
default on the PMUGRF_SOC_CON0,
so I think that we don't need to do the static settings to re-enable
them in the clock driver any more.
Thanks.
--
- Xing Zheng
WARNING: multiple messages have this Message-ID (diff)
From: Xing Zheng <zhengxing@rock-chips.com>
To: Heiko Stuebner <heiko@sntech.de>
Cc: linux-rockchip@lists.infradead.org, huangtao@rock-chips.com,
jay.xu@rock-chips.com, elaine.zhang@rock-chips.com,
dianders@chromium.org, Rob Herring <robh+dt@kernel.org>,
Pawel Moll <pawel.moll@arm.com>,
Mark Rutland <mark.rutland@arm.com>,
Ian Campbell <ijc+devicetree@hellion.org.uk>,
Kumar Gala <galak@codeaurora.org>,
Stephen Boyd <sboyd@codeaurora.org>,
devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org,
linux-kernel@vger.kernel.org
Subject: Re: [PATCH v5 2/4] dt-bindings: add bindings for rk3399 clock controller
Date: Mon, 28 Mar 2016 11:24:47 +0800 [thread overview]
Message-ID: <56F8A3FF.6090800@rock-chips.com> (raw)
In-Reply-To: <3689505.b0IKY6iWOt@phil>
Hi Heiko,
On 2016年03月28日 08:07, Heiko Stuebner wrote:
> Hi Xing,
>
> Am Montag, 28. März 2016, 01:52:12 schrieb Heiko Stübner:
>> Am Samstag, 26. März 2016, 14:37:54 schrieb Xing Zheng:
>>> Add devicetree bindings for Rockchip cru which found on
>>> Rockchip SoCs.
>>>
>>> Signed-off-by: Xing Zheng<zhengxing@rock-chips.com>
>>> Signed-off-by: Jianqun Xu<jay.xu@rock-chips.com>
>>> Acked-by: Rob Herring<robh@kernel.org>
>>> ---
>>>
>>> Changes in v5: None
>>> Changes in v3: None
>>> Changes in v2: None
>>>
>>> .../bindings/clock/rockchip,rk3399-cru.txt | 83
>>>
>>> ++++++++++++++++++++ 1 file changed, 83 insertions(+)
>>>
>>> create mode 100644
>>>
>>> Documentation/devicetree/bindings/clock/rockchip,rk3399-cru.txt
>>>
>>> diff --git a/Documentation/devicetree/bindings/clock/rockchip,rk3399-
>> cru.txt
>>
>>> b/Documentation/devicetree/bindings/clock/rockchip,rk3399-cru.txt new
>>> file mode 100644
>>> index 0000000..9427caa
>>> --- /dev/null
>>> +++ b/Documentation/devicetree/bindings/clock/rockchip,rk3399-cru.txt
>>> @@ -0,0 +1,83 @@
>>> +* Rockchip RK3399 Clock and Reset Unit
>>> +
>>> +The RK3399 clock controller generates and supplies clock to various
>>> +controllers within the SoC and also implements a reset controller for
>>> SoC +peripherals.
>>> +
>>> +Required Properties:
>>> +
>>> +- compatible: PMU for CRU should be "rockchip,rk3399-pmucru"
>>> +- compatible: CRU should be "rockchip,rk3399-cru"
>>> +- reg: physical base address of the controller and length of memory
>> mapped
>>
>>> + region.
>>> +- #clock-cells: should be 1.
>>> +- #reset-cells: should be 1.
>>> +
>>> +Optional Properties:
>>> +
>>> +- rockchip,grf: phandle to the syscon managing the "general register
>> files"
>>
>>> + If missing, pll rates are not changeable, due to the missing pll lock
>>> status. +
>> the rk3399 doesn't need the GRF, so we should drop this block for now
> actually, I just saw that the GRF is needed for the static settings during
> init. So the rockchip,grf should stay but also move up to required
> properties?
>
> Same for the grf-comment in the examples-section.
>
>
I check the setting of the pclk_alive and pclk_pmu_src are not gating
default on the PMUGRF_SOC_CON0,
so I think that we don't need to do the static settings to re-enable
them in the clock driver any more.
Thanks.
--
- Xing Zheng
next prev parent reply other threads:[~2016-03-28 3:24 UTC|newest]
Thread overview: 35+ messages / expand[flat|nested] mbox.gz Atom feed top
2016-03-26 6:37 [PATCH v5 0/4] Add more clock compatible features and support the RK3399 clock Xing Zheng
2016-03-26 6:37 ` Xing Zheng
2016-03-26 6:37 ` [PATCH v5 1/4] clk: rockchip: fix big.LITTLE cores alternate reparent failed Xing Zheng
2016-03-26 6:37 ` Xing Zheng
2016-03-26 8:26 ` kbuild test robot
2016-03-26 8:26 ` kbuild test robot
2016-03-26 8:26 ` kbuild test robot
2016-03-27 21:26 ` Heiko Stübner
2016-03-27 21:26 ` Heiko Stübner
2016-03-27 21:26 ` Heiko Stübner
[not found] ` <1458974276-10325-1-git-send-email-zhengxing-TNX95d0MmH7DzftRWevZcw@public.gmane.org>
2016-03-26 6:37 ` [PATCH v5 2/4] dt-bindings: add bindings for rk3399 clock controller Xing Zheng
2016-03-26 6:37 ` Xing Zheng
2016-03-26 6:37 ` Xing Zheng
[not found] ` <1458974276-10325-3-git-send-email-zhengxing-TNX95d0MmH7DzftRWevZcw@public.gmane.org>
2016-03-27 23:52 ` Heiko Stübner
2016-03-27 23:52 ` Heiko Stübner
2016-03-27 23:52 ` Heiko Stübner
2016-03-28 0:07 ` Heiko Stuebner
2016-03-28 0:07 ` Heiko Stuebner
2016-03-28 3:24 ` Xing Zheng [this message]
2016-03-28 3:24 ` Xing Zheng
2016-03-28 3:24 ` Xing Zheng
2016-03-28 2:51 ` Xing Zheng
2016-03-28 2:51 ` Xing Zheng
2016-03-26 6:37 ` [PATCH v5 3/4] clk: rockchip: add dt-binding header for rk3399 Xing Zheng
2016-03-26 6:37 ` Xing Zheng
2016-03-26 6:37 ` [PATCH v5 4/4] clk: rockchip: add clock controller for the RK3399 Xing Zheng
2016-03-26 6:37 ` Xing Zheng
2016-03-26 8:41 ` kbuild test robot
2016-03-26 8:41 ` kbuild test robot
2016-03-26 8:41 ` kbuild test robot
2016-03-28 0:13 ` Heiko Stuebner
2016-03-28 0:13 ` Heiko Stuebner
2016-03-28 0:13 ` Heiko Stuebner
2016-03-28 6:11 ` Xing Zheng
2016-03-28 6:11 ` Xing Zheng
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