Re: [PATCH v5 4/4] clk: rockchip: add clock controller for the RK3399

[Heiko Stuebner <heiko@sntech.de>]

Hi Xing,

Am Samstag, 26. M=E4rz 2016, 14:37:56 schrieb Xing Zheng:
> Add the clock tree definition for the new RK3399 SoC.
>=20
> Signed-off-by: Xing Zheng <zhengxing@rock-chips.com>
> ---

[...]

> +=09/*
> +=09 * We use pclkin_cifinv by default GRF_SOC_CON20[9] (GSC20_9) set=
ting in
> system, +=09 * so we ignore the mux and make clocks nodes as followin=
g,
> +=09 *
> +=09 * pclkin_cifinv --|-------\
> +=09 *                 |GSC20_9|-- pclkin_cifmux
> +=09 * pclkin_cif    --|-------/
> +=09 */
> +=09GATE(PCLK_ISP1_WRAPPER, "pclkin_isp1_wrapper", "pclkin_cifmux",

please name that source clock pclkin_cif as in the TRM.
pclkin_cif is the actual input clock - if I'm reading the TRM correctly=
 and=20
the inverter is part of the soc or so?

That we currently hide / hardcode the phase-handling should not be part=
 of=20
our outside connection - which should be stable even if we implement th=
is=20
later.


Heiko