Re: [Qemu-arm] [PATCH 3/4] target-arm: Make the 64-bit version of VTCR do the migration

[Sergey Fedorov <sergey.fedorov@linaro.org>]

On 31/03/16 17:49, Peter Maydell wrote:
> Move the ALIAS tag from VTCR_EL2 to VTCR so that we migrate the
> 64-bit version, as is usual. (This has no particular effect now
> unless the guest wrote to the high RES0 bits of VTCR_EL2.)
> Add a comment about why it's OK that we don't have the various
> accessor functions that the EL1 TCR regdefs do.
>
> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>

Reviewed-by: Sergey Fedorov <sergey.fedorov@linaro.org>

> ---
>  target-arm/helper.c | 6 +++++-
>  1 file changed, 5 insertions(+), 1 deletion(-)
>
> diff --git a/target-arm/helper.c b/target-arm/helper.c
> index 0e54d90..09638b2 100644
> --- a/target-arm/helper.c
> +++ b/target-arm/helper.c
> @@ -3564,11 +3564,15 @@ static const ARMCPRegInfo el2_cp_reginfo[] = {
>        .fieldoffset = offsetof(CPUARMState, cp15.tcr_el[2]) },
>      { .name = "VTCR", .state = ARM_CP_STATE_AA32,
>        .cp = 15, .opc1 = 4, .crn = 2, .crm = 1, .opc2 = 2,
> +      .type = ARM_CP_ALIAS,
>        .access = PL2_RW, .accessfn = access_el3_aa32ns,
>        .fieldoffset = offsetof(CPUARMState, cp15.vtcr_el2) },
>      { .name = "VTCR_EL2", .state = ARM_CP_STATE_AA64,
>        .opc0 = 3, .opc1 = 4, .crn = 2, .crm = 1, .opc2 = 2,
> -      .access = PL2_RW, .type = ARM_CP_ALIAS,
> +      .access = PL2_RW,
> +      /* no .writefn needed as this can't cause an ASID change;
> +       * no .raw_writefn or .resetfn needed as we never use mask/base_mask
> +       */
>        .fieldoffset = offsetof(CPUARMState, cp15.vtcr_el2) },
>      { .name = "VTTBR", .state = ARM_CP_STATE_AA32,
>        .cp = 15, .opc1 = 6, .crm = 2,