[PATCH 0/3] advsync: Typo fix and vertical spacing tweaks

[PATCH 0/3] advsync: Typo fix and vertical spacing tweaks

[Akira Yokosawa]

From e9f9f2126a24841bb19970292716819f0300872b Mon Sep 17 00:00:00 2001
From: Akira Yokosawa <akiysw@gmail.com>
Date: Sat, 16 Apr 2016 16:48:19 +0900
Subject: [PATCH 0/3] advsync: Typo fix and vertical spacing tweaks

As I mentioned earlier, I tweaked vertical spacings in the
`Guarantees` subsection. This series also fixes a typo I made
in the previous patch. It also adds necessary blank lines in the
latex source of the `What Can You Trust?` subsection.

Akira Yokosawa (3):
  advsync: Fix a trivial typo
  advsync: Add necessary blank lines around minipages
  advsync: Tweak vertical spacing around code snippets

 advsync/memorybarriers.tex | 44 ++++++++++++++------------------------------
 1 file changed, 14 insertions(+), 30 deletions(-)

-- 
1.9.1

[PATCH 1/3] advsync: Fix a trivial typo

[Akira Yokosawa]

From dd4bfd425504ccef4226bc782394255c3dc4777a Mon Sep 17 00:00:00 2001
From: Akira Yokosawa <akiysw@gmail.com>
Date: Fri, 15 Apr 2016 21:59:40 +0900
Subject: [PATCH 1/3] advsync: Fix a trivial typo

In commit 5795796caa89 ("advsync: Another fix to use latex reference
feature consistently"), I made a typo. This commit fixes it.

Signed-off-by: Akira Yokosawa <akiyks@gmail.com>
---
 advsync/memorybarriers.tex | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/advsync/memorybarriers.tex b/advsync/memorybarriers.tex
index e527def..965718c 100644
--- a/advsync/memorybarriers.tex
+++ b/advsync/memorybarriers.tex
@@ -1508,7 +1508,7 @@ Read memory barriers imply data dependency barriers, and so can substitute
 for them.

 $\dagger$ Note that read barriers should normally be paired with write barriers;
-see Secton~\ref{sec:advsync:SMP Barrier Pairing}.
+see Section~\ref{sec:advsync:SMP Barrier Pairing}.

 \paragraph{General Memory Barriers}

-- 
1.9.1

[PATCH 2/3] advsync: Add necessary blank lines around minipages

[Akira Yokosawa]

From 9aac20a120daf460b1046cb234e8eddd1171271b Mon Sep 17 00:00:00 2001
From: Akira Yokosawa <akiysw@gmail.com>
Date: Fri, 15 Apr 2016 23:20:36 +0900
Subject: [PATCH 2/3] advsync: Add necessary blank lines around minipages

In the `Pair-Wise Memory Barriers: Portable Combinations`
subsubsection, we need blank lines before and after minipages
that embody code snippet tables. Without them, minipages are
forced to be placed in strange ways. This commit adds those
necessary blank lines.
Also it adds "\scriptsize" commands to the minipages for their
consistency with the one in the previous subsubsection.

Signed-off-by: Akira Yokosawa <akiyks@gmail.com>
---
 advsync/memorybarriers.tex | 10 ++++++++++
 1 file changed, 10 insertions(+)

diff --git a/advsync/memorybarriers.tex b/advsync/memorybarriers.tex
index 965718c..0ef020f 100644
--- a/advsync/memorybarriers.tex
+++ b/advsync/memorybarriers.tex
@@ -565,9 +565,11 @@ pairings that portable software may depend on.
 	by a memory barrier, while a second CPU executes a pair
 	of stores also separated by a memory barrier, as follows
 	(both A and B are initially equal to zero):
+
 	\vspace{5pt}
 	\begin{minipage}[t]{\columnwidth}
 	\tt
+	\scriptsize
 	\begin{tabular}{l|l}
 		CPU 1 &			CPU 2 \\
 		\hline
@@ -577,6 +579,7 @@ pairings that portable software may depend on.
 	\end{tabular}
 	\end{minipage}
 	\vspace{5pt}
+
 	After both CPUs have completed executing these code sequences,
 	if \co{Y==1}, then we must also have \co{X==1}.
 	In this case, the fact that \co{Y==1} means that
@@ -594,9 +597,11 @@ pairings that portable software may depend on.
 	In this pairing, each CPU executes a load followed by a
 	memory barrier followed by a store, as follows
 	(both A and B are initially equal to zero):
+
 	\vspace{5pt}
 	\begin{minipage}[t]{\columnwidth}
 	\tt
+	\scriptsize
 	\begin{tabular}{l|l}
 		CPU 1 &			CPU 2 \\
 		\hline
@@ -606,6 +611,7 @@ pairings that portable software may depend on.
 	\end{tabular}
 	\end{minipage}
 	\vspace{5pt}
+
 	After both CPUs have completed executing these code sequences,
 	if \co{X==1}, then we must also have \co{Y==0}.
 	In this case, the fact that \co{X==1} means that
@@ -628,9 +634,11 @@ pairings that portable software may depend on.
 	memory barrier followed by a store, while the other CPU
 	executes a pair of stores separated by a memory barrier,
 	as follows (both A and B are initially equal to zero):
+
 	\vspace{5pt}
 	\begin{minipage}[t]{\columnwidth}
 	\tt
+	\scriptsize
 	\begin{tabular}{l|l}
 		CPU 1 &			CPU 2 \\
 		\hline
@@ -640,6 +648,7 @@ pairings that portable software may depend on.
 	\end{tabular}
 	\end{minipage}
 	\vspace{5pt}
+
 	After both CPUs have completed executing these code sequences,
 	if \co{X==1}, then we must also have \co{B==1}.
 	In this case, the fact that \co{X==1} means that
@@ -710,6 +719,7 @@ keep in mind that they used to be a \emph{lot} harder on some systems!
 	\vspace{5pt}
 	\begin{minipage}[t]{\columnwidth}
 	\tt
+	\scriptsize
 	\begin{tabular}{l|l}
 		CPU 1 &			CPU 2 \\
 		\hline
-- 
1.9.1

[PATCH 3/3] advsync: Tweak vertical spacing around code snippets

[Akira Yokosawa]

From e9f9f2126a24841bb19970292716819f0300872b Mon Sep 17 00:00:00 2001
From: Akira Yokosawa <akiysw@gmail.com>
Date: Sat, 16 Apr 2016 12:50:54 +0900
Subject: [PATCH 3/3] advsync: Tweak vertical spacing around code snippets

In the `Guarantees` subsection, code snippets have wider
vertical spacings around them than other code snippets in the
section.
This is supposedly caused by the interaction between the
'enumerate' tag and the 'minipage' tag.
This commit removes \vspace{} commands around minipages within
enumerations. Some \vspace{} commands which break sentences
are reduced in width and moved into minipages to stabilize the
resulting vertical spacings.

Signed-off-by: Akira Yokosawa <akiyks@gmail.com>
---
 advsync/memorybarriers.tex | 32 +++-----------------------------
 1 file changed, 3 insertions(+), 29 deletions(-)

diff --git a/advsync/memorybarriers.tex b/advsync/memorybarriers.tex
index 0ef020f..505adc0 100644
--- a/advsync/memorybarriers.tex
+++ b/advsync/memorybarriers.tex
@@ -1236,72 +1236,61 @@ There are some minimal guarantees that may be expected of a CPU:
 \item	On any given CPU, dependent memory accesses will be issued in order,
 	with respect to itself.  This means that for:

-\vspace{5pt}
 \begin{minipage}[t]{\columnwidth}
 \scriptsize
 \begin{verbatim}
 Q = P; D = *Q;
 \end{verbatim}
 \end{minipage}
-\vspace{5pt}

 	the CPU will issue the following memory operations:

-\vspace{5pt}
 \begin{minipage}[t]{\columnwidth}
 \scriptsize
 \begin{verbatim}
 Q = LOAD P, D = LOAD *Q
 \end{verbatim}
 \end{minipage}
-\vspace{5pt}

 	and always in that order.

 \item	Overlapping loads and stores within a particular CPU will appear to be
 	ordered within that CPU.  This means that for:

-\vspace{5pt}
 \begin{minipage}[t]{\columnwidth}
 \scriptsize
 \begin{verbatim}
 a = *X; *X = b;
 \end{verbatim}
 \end{minipage}
-\vspace{5pt}

 	the CPU will only issue the following sequence of memory operations:

-\vspace{5pt}
 \begin{minipage}[t]{\columnwidth}
 \scriptsize
 \begin{verbatim}
 a = LOAD *X, STORE *X = b
 \end{verbatim}
+\vspace{1pt}
 \end{minipage}
-\vspace{5pt}

 	And for:

-\vspace{5pt}
 \begin{minipage}[t]{\columnwidth}
 \scriptsize
 \begin{verbatim}
 *X = c; d = *X;
 \end{verbatim}
 \end{minipage}
-\vspace{5pt}

 	the CPU will only issue:

-\vspace{5pt}
 \begin{minipage}[t]{\columnwidth}
 \scriptsize
 \begin{verbatim}
 STORE *X = c, d = LOAD *X
 \end{verbatim}
 \end{minipage}
-\vspace{5pt}

 	(Loads and stores overlap if they are targeted at overlapping pieces of
 	memory).
@@ -1317,19 +1306,15 @@ And there are a number of things that \emph{must} or \emph{must not} be assumed:
 \item	It \emph{must not} be assumed that independent loads and stores will
 	be issued in the order given.  This means that for:

-\vspace{5pt}
 \begin{minipage}[t]{\columnwidth}
 \scriptsize
 \begin{verbatim}
 X = *A; Y = *B; *D = Z;
 \end{verbatim}
 \end{minipage}
-\vspace{5pt}

 	we may get any of the following sequences:

-
-\vspace{5pt}
 \begin{minipage}[t]{\columnwidth}
 \scriptsize
 \begin{verbatim}
@@ -1341,23 +1326,19 @@ STORE *D = Z,  X = LOAD *A,  Y = LOAD *B
 STORE *D = Z,  Y = LOAD *B,  X = LOAD *A
 \end{verbatim}
 \end{minipage}
-\vspace{5pt}

 \item	It \emph{must} be assumed that overlapping memory accesses may
 	be merged or discarded.  This means that for:

-\vspace{5pt}
 \begin{minipage}[t]{\columnwidth}
 \scriptsize
 \begin{verbatim}
 X = *A; Y = *(A + 4);
 \end{verbatim}
 \end{minipage}
-\vspace{5pt}

 	we may get any one of the following sequences:

-\vspace{5pt}
 \begin{minipage}[t]{\columnwidth}
 \scriptsize
 \begin{verbatim}
@@ -1365,23 +1346,20 @@ X = LOAD *A; Y = LOAD *(A + 4);
 Y = LOAD *(A + 4); X = LOAD *A;
 {X, Y} = LOAD {*A, *(A + 4) };
 \end{verbatim}
+\vspace{1pt}
 \end{minipage}
-\vspace{5pt}

 	And for:

-\vspace{5pt}
 \begin{minipage}[t]{\columnwidth}
 \scriptsize
 \begin{verbatim}
 *A = X; *(A + 4) = Y;
 \end{verbatim}
 \end{minipage}
-\vspace{5pt}

 	we may get any of:

-\vspace{5pt}
 \begin{minipage}[t]{\columnwidth}
 \scriptsize
 \begin{verbatim}
@@ -1389,23 +1367,20 @@ STORE *A = X; STORE *(A + 4) = Y;
 STORE *(A + 4) = Y; STORE *A = X;
 STORE {*A, *(A + 4) } = {X, Y};
 \end{verbatim}
+\vspace{1pt}
 \end{minipage}
-\vspace{5pt}

 	Finally, for:

-\vspace{5pt}
 \begin{minipage}[t]{\columnwidth}
 \scriptsize
 \begin{verbatim}
 *A = X; *A = Y;
 \end{verbatim}
 \end{minipage}
-\vspace{5pt}

 	we may get either of:

-\vspace{5pt}
 \begin{minipage}[t]{\columnwidth}
 \scriptsize
 \begin{verbatim}
@@ -1413,7 +1388,6 @@ STORE *A = X; STORE *A = Y;
 STORE *A = Y;
 \end{verbatim}
 \end{minipage}
-\vspace{5pt}

 \end{enumerate}

-- 
1.9.1

Re: [PATCH 0/3] advsync: Typo fix and vertical spacing tweaks

[Paul E. McKenney]

On Sat, Apr 16, 2016 at 05:07:43PM +0900, Akira Yokosawa wrote:
> >From e9f9f2126a24841bb19970292716819f0300872b Mon Sep 17 00:00:00 2001
> From: Akira Yokosawa <akiysw@gmail.com>
> Date: Sat, 16 Apr 2016 16:48:19 +0900
> Subject: [PATCH 0/3] advsync: Typo fix and vertical spacing tweaks
> 
> As I mentioned earlier, I tweaked vertical spacings in the
> `Guarantees` subsection. This series also fixes a typo I made
> in the previous patch. It also adds necessary blank lines in the
> latex source of the `What Can You Trust?` subsection.
> 
> Akira Yokosawa (3):
>   advsync: Fix a trivial typo
>   advsync: Add necessary blank lines around minipages
>   advsync: Tweak vertical spacing around code snippets
> 
>  advsync/memorybarriers.tex | 44 ++++++++++++++------------------------------
>  1 file changed, 14 insertions(+), 30 deletions(-)

Nice!

Queued and pushed.

							Thanx, Paul