From: Stephen Warren <swarren@wwwdotorg.org>
To: Stephen Boyd <sboyd@codeaurora.org>,
Thierry Reding <thierry.reding@gmail.com>
Cc: Penny Chiu <pchiu@nvidia.com>,
gnurou@gmail.com, pdeschrijver@nvidia.com, pgaikwad@nvidia.com,
rjw@rjwysocki.net, viresh.kumar@linaro.org,
mturquette@baylibre.com, linux-tegra@vger.kernel.org,
linux-clk@vger.kernel.org, linux-pwm@vger.kernel.org,
linux-pm@vger.kernel.org, linux-arm-kernel@lists.infradead.org,
linux-kernel@vger.kernel.org
Subject: Re: [PATCH 05/11] pwm: tegra-dfll: Add driver for Tegra DFLL PWM controller
Date: Fri, 6 May 2016 17:21:11 -0600 [thread overview]
Message-ID: <572D26E7.2060406@wwwdotorg.org> (raw)
In-Reply-To: <20160506231532.GK3492@codeaurora.org>
On 05/06/2016 05:15 PM, Stephen Boyd wrote:
> On 04/22, Thierry Reding wrote:
>> On Fri, Apr 22, 2016 at 06:31:05PM +0800, Penny Chiu wrote:
>>> diff --git a/Documentation/devicetree/bindings/pwm/nvidia,tegra-dfll-pwm.txt b/Documentation/devicetree/bindings/pwm/nvidia,tegra-dfll-pwm.txt
>>> new file mode 100644
>>> index 0000000..bd0d247
>>> --- /dev/null
>>> +++ b/Documentation/devicetree/bindings/pwm/nvidia,tegra-dfll-pwm.txt
>>> @@ -0,0 +1,48 @@
>>> +Tegra SoC DFLL PWM controller
>>
>> Stephen, we have in the past used tegra124 in names, even if the IP was
>> already included in tegra114, but we never supported it on Tegra114 and
>> hence couldn't even verify that the binding was valid. Any preference as
>> to the name in this particular case?
>
> You meant Stephen Warren right? I don't care either way.
Sorry, I wasn't really paying attention to patches.
Yes, using "124" seems to make sense; we can always expand the binding
to cover "114" later if there's any demand.
WARNING: multiple messages have this Message-ID (diff)
From: swarren@wwwdotorg.org (Stephen Warren)
To: linux-arm-kernel@lists.infradead.org
Subject: [PATCH 05/11] pwm: tegra-dfll: Add driver for Tegra DFLL PWM controller
Date: Fri, 6 May 2016 17:21:11 -0600 [thread overview]
Message-ID: <572D26E7.2060406@wwwdotorg.org> (raw)
In-Reply-To: <20160506231532.GK3492@codeaurora.org>
On 05/06/2016 05:15 PM, Stephen Boyd wrote:
> On 04/22, Thierry Reding wrote:
>> On Fri, Apr 22, 2016 at 06:31:05PM +0800, Penny Chiu wrote:
>>> diff --git a/Documentation/devicetree/bindings/pwm/nvidia,tegra-dfll-pwm.txt b/Documentation/devicetree/bindings/pwm/nvidia,tegra-dfll-pwm.txt
>>> new file mode 100644
>>> index 0000000..bd0d247
>>> --- /dev/null
>>> +++ b/Documentation/devicetree/bindings/pwm/nvidia,tegra-dfll-pwm.txt
>>> @@ -0,0 +1,48 @@
>>> +Tegra SoC DFLL PWM controller
>>
>> Stephen, we have in the past used tegra124 in names, even if the IP was
>> already included in tegra114, but we never supported it on Tegra114 and
>> hence couldn't even verify that the binding was valid. Any preference as
>> to the name in this particular case?
>
> You meant Stephen Warren right? I don't care either way.
Sorry, I wasn't really paying attention to patches.
Yes, using "124" seems to make sense; we can always expand the binding
to cover "114" later if there's any demand.
next prev parent reply other threads:[~2016-05-06 23:21 UTC|newest]
Thread overview: 62+ messages / expand[flat|nested] mbox.gz Atom feed top
2016-04-22 10:31 [PATCH 00/11] arm64: tegra: Add Tegra DFLL for Tegra210 Jetson TX1 Penny Chiu
2016-04-22 10:31 ` Penny Chiu
2016-04-22 10:31 ` Penny Chiu
2016-04-22 10:31 ` [PATCH 01/11] clk: tegra: dfll: Fix voltage comparison Penny Chiu
2016-04-22 10:31 ` Penny Chiu
2016-04-22 10:31 ` Penny Chiu
2016-04-22 10:31 ` [PATCH 02/11] clk: tegra: dfll: Move SoC specific data into of_device_id Penny Chiu
2016-04-22 10:31 ` Penny Chiu
2016-04-22 10:31 ` Penny Chiu
2016-04-22 13:04 ` Thierry Reding
2016-04-22 13:04 ` Thierry Reding
2016-04-22 10:31 ` [PATCH 03/11] clk: tegra: Add DFLL DVCO reset control for Tegra210 Penny Chiu
2016-04-22 10:31 ` Penny Chiu
2016-04-22 10:31 ` Penny Chiu
2016-04-22 13:11 ` Thierry Reding
2016-04-22 13:11 ` Thierry Reding
2016-04-22 10:31 ` [PATCH 04/11] clk: tegra: Add Tegra210 support in DFLL driver Penny Chiu
2016-04-22 10:31 ` Penny Chiu
2016-04-22 10:31 ` Penny Chiu
2016-04-22 13:16 ` Thierry Reding
2016-04-22 13:16 ` Thierry Reding
2016-04-22 10:31 ` [PATCH 05/11] pwm: tegra-dfll: Add driver for Tegra DFLL PWM controller Penny Chiu
2016-04-22 10:31 ` Penny Chiu
2016-04-22 10:31 ` Penny Chiu
2016-04-22 12:55 ` Thierry Reding
2016-04-22 12:55 ` Thierry Reding
2016-05-06 23:15 ` Stephen Boyd
2016-05-06 23:15 ` Stephen Boyd
2016-05-06 23:21 ` Stephen Warren [this message]
2016-05-06 23:21 ` Stephen Warren
2016-04-22 10:31 ` [PATCH 06/11] clk: tegra: dfll: Add PWM inferface Penny Chiu
2016-04-22 10:31 ` Penny Chiu
2016-04-22 10:31 ` Penny Chiu
2016-04-22 10:31 ` [PATCH 07/11] cpufreq: tegra124: Add Tegra210 support Penny Chiu
2016-04-22 10:31 ` Penny Chiu
2016-04-22 10:31 ` Penny Chiu
2016-04-22 11:00 ` Viresh Kumar
2016-04-22 11:00 ` Viresh Kumar
2016-04-22 11:00 ` Viresh Kumar
2016-04-22 10:31 ` [PATCH 08/11] arm64: tegra: Add PWM regulator for CPU rail on Jetson TX1 Penny Chiu
2016-04-22 10:31 ` Penny Chiu
2016-04-22 10:31 ` Penny Chiu
2016-04-22 10:31 ` [PATCH 09/11] arm64: tegra: Add DFLL clock node " Penny Chiu
2016-04-22 10:31 ` Penny Chiu
2016-04-22 10:31 ` Penny Chiu
2016-04-22 13:28 ` Thierry Reding
2016-04-22 13:28 ` Thierry Reding
2016-04-22 13:28 ` Thierry Reding
2016-04-22 10:31 ` [PATCH 10/11] arm64: tegra: Add clock properties on cpu0 for Tegra210 Penny Chiu
2016-04-22 10:31 ` Penny Chiu
2016-04-22 10:31 ` Penny Chiu
2016-04-22 11:44 ` Jon Hunter
2016-04-22 11:44 ` Jon Hunter
2016-04-22 11:44 ` Jon Hunter
2016-04-22 13:23 ` Thierry Reding
2016-04-22 13:23 ` Thierry Reding
2016-04-22 13:36 ` Jon Hunter
2016-04-22 13:36 ` Jon Hunter
2016-04-22 13:36 ` Jon Hunter
2016-04-22 10:31 ` [PATCH 11/11] arm64: config: Enable CPUFreq-DT, Tegra DFLL PWM, and PWM regulator Penny Chiu
2016-04-22 10:31 ` Penny Chiu
2016-04-22 10:31 ` Penny Chiu
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