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From: Marc Zyngier <marc.zyngier@arm.com>
To: Andre Przywara <andre.przywara@arm.com>,
	Christoffer Dall <christoffer.dall@linaro.org>
Cc: linux-arm-kernel@lists.infradead.org,
	kvmarm@lists.cs.columbia.edu, kvm@vger.kernel.org
Subject: Re: [PATCH v4 22/56] KVM: arm/arm64: vgic-new: Add MMIO handling framework
Date: Tue, 17 May 2016 14:33:36 +0100	[thread overview]
Message-ID: <573B1DB0.7030901@arm.com> (raw)
In-Reply-To: <1463392481-26583-23-git-send-email-andre.przywara@arm.com>

On 16/05/16 10:53, Andre Przywara wrote:
> From: Marc Zyngier <marc.zyngier@arm.com>
> 
> Add an MMIO handling framework to the VGIC emulation:
> Each register is described by its offset, size (or number of bits per
> IRQ, if applicable) and the read/write handler functions. We provide
> initialization macros to describe each GIC register later easily.
> 
> Separate dispatch functions for read and write accesses are connected
> to the kvm_io_bus framework and binary-search for the responsible
> register handler based on the offset address within the region.
> We convert the incoming data (referenced by a pointer) to the host's
> endianess and use pass-by-value to hand the data over to the actual
> handler functions.
> 
> The register handler prototype and the endianess conversion are
> courtesy of Christoffer Dall.
> 
> Signed-off-by: Marc Zyngier <marc.zyngier@arm.com>
> Signed-off-by: Christoffer Dall <christoffer.dall@linaro.org>
> Signed-off-by: Andre Przywara <andre.przywara@arm.com>
> ---
> Changelog RFC..v1:
> - rework MMIO dispatching to use only one kvm_io_bus device
> - document purpose of register region macros
> - rename "this" parameter to "dev"
> - change IGROUPR to be RAO (returning 1 => Group1 IRQs)
> 
> Changelog v1 .. v2:
> * MASSIVE rework:
> - store register_region pointer in kvm_io_bus linked struct
> - replace write_mask_xxx functions with extract_bytes() implementation
> - change handler functions' prototypes to take and return unsigned long
> - use binary search to find matching register handler
> - convert endianess of input data in dispatch_mmio_xxx functions
> - improve readability of register initializer macros
> - remove any GICv2/GICv3 specific functions from vgic-mmio.c
> - rename file from vgic_mmio.c to vgic-mmio.c
> 
> Changelog v2 .. v3:
> - replace inclusion of vgic/vgic.h with arm_vgic.h
> 
> Changelog v3 .. v4:
> - add IRQ number accessor macro
> - check access width in dispatcher
> - treat non-covered MMIO addresses as RAZ/WI
> - remove extract_bytes() (re-introduced as static later in the series)
> 
>  include/kvm/vgic/vgic.h       |  13 +++
>  virt/kvm/arm/vgic/vgic-mmio.c | 184 ++++++++++++++++++++++++++++++++++++++++++
>  virt/kvm/arm/vgic/vgic-mmio.h |  87 ++++++++++++++++++++
>  3 files changed, 284 insertions(+)
>  create mode 100644 virt/kvm/arm/vgic/vgic-mmio.c
>  create mode 100644 virt/kvm/arm/vgic/vgic-mmio.h
> 
> diff --git a/include/kvm/vgic/vgic.h b/include/kvm/vgic/vgic.h
> index f663288..ff3f9c2 100644
> --- a/include/kvm/vgic/vgic.h
> +++ b/include/kvm/vgic/vgic.h
> @@ -106,6 +106,16 @@ struct vgic_irq {
>  	enum vgic_irq_config config;	/* Level or edge */
>  };
>  
> +struct vgic_register_region;
> +
> +struct vgic_io_device {
> +	gpa_t base_addr;
> +	struct kvm_vcpu *redist_vcpu;
> +	const struct vgic_register_region *regions;
> +	int nr_regions;
> +	struct kvm_io_device dev;
> +};
> +
>  struct vgic_dist {
>  	bool			in_kernel;
>  	bool			ready;
> @@ -132,6 +142,9 @@ struct vgic_dist {
>  	bool			enabled;
>  
>  	struct vgic_irq		*spis;
> +
> +	struct vgic_io_device	dist_iodev;
> +	struct vgic_io_device	*redist_iodevs;
>  };
>  
>  struct vgic_v2_cpu_if {
> diff --git a/virt/kvm/arm/vgic/vgic-mmio.c b/virt/kvm/arm/vgic/vgic-mmio.c
> new file mode 100644
> index 0000000..012b82b
> --- /dev/null
> +++ b/virt/kvm/arm/vgic/vgic-mmio.c
> @@ -0,0 +1,184 @@
> +/*
> + * VGIC MMIO handling functions
> + *
> + * This program is free software; you can redistribute it and/or modify
> + * it under the terms of the GNU General Public License version 2 as
> + * published by the Free Software Foundation.
> + *
> + * This program is distributed in the hope that it will be useful,
> + * but WITHOUT ANY WARRANTY; without even the implied warranty of
> + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
> + * GNU General Public License for more details.
> + */
> +
> +#include <linux/bitops.h>
> +#include <linux/bsearch.h>
> +#include <linux/kvm.h>
> +#include <linux/kvm_host.h>
> +#include <kvm/iodev.h>
> +#include <kvm/arm_vgic.h>
> +
> +#include "vgic.h"
> +#include "vgic-mmio.h"
> +
> +unsigned long vgic_mmio_read_raz(struct kvm_vcpu *vcpu,
> +				 gpa_t addr, unsigned int len)
> +{
> +	return 0;
> +}
> +
> +unsigned long vgic_mmio_read_rao(struct kvm_vcpu *vcpu,
> +				 gpa_t addr, unsigned int len)
> +{
> +	return -1UL;
> +}
> +
> +void vgic_mmio_write_wi(struct kvm_vcpu *vcpu, gpa_t addr,
> +			unsigned int len, unsigned long val)
> +{
> +	/* Ignore */
> +}
> +
> +static int match_region(const void *key, const void *elt)
> +{
> +	const unsigned int offset = (unsigned long)key;
> +	const struct vgic_register_region *region = elt;
> +
> +	if (offset < region->reg_offset)
> +		return -1;
> +
> +	if (offset >= region->reg_offset + region->len)
> +		return 1;
> +
> +	return 0;
> +}
> +
> +/* Find the proper register handler entry given a certain address offset. */
> +static const struct vgic_register_region *
> +vgic_find_mmio_region(const struct vgic_register_region *region, int nr_regions,
> +		      unsigned int offset)
> +{
> +	return bsearch((void *)(uintptr_t)offset, region, nr_regions,
> +		       sizeof(region[0]), match_region);
> +}
> +
> +/*
> + * kvm_mmio_read_buf() returns a value in a format where it can be converted
> + * to a byte array and be directly observed as the guest wanted it to appear
> + * in memory if it had done the store itself, which is LE for the GIC, as the
> + * guest knows the GIC is always LE.
> + *
> + * We convert this value to the CPUs native format to deal with it as a data
> + * value.
> + */
> +unsigned long vgic_data_mmio_bus_to_host(const void *val, unsigned int len)
> +{
> +	unsigned long data = kvm_mmio_read_buf(val, len);
> +
> +	switch (len) {
> +	case 1:
> +		return data;
> +	case 2:
> +		return le16_to_cpu(data);
> +	case 4:
> +		return le32_to_cpu(data);
> +	default:
> +		return le64_to_cpu(data);
> +	}
> +}
> +
> +/*
> + * kvm_mmio_write_buf() expects a value in a format such that if converted to
> + * a byte array it is observed as the guest would see it if it could perform
> + * the load directly.  Since the GIC is LE, and the guest knows this, the
> + * guest expects a value in little endian format.
> + *
> + * We convert the data value from the CPUs native format to LE so that the
> + * value is returned in the proper format.
> + */
> +void vgic_data_host_to_mmio_bus(void *buf, unsigned int len,
> +				unsigned long data)
> +{
> +	switch (len) {
> +	case 1:
> +		break;
> +	case 2:
> +		data = cpu_to_le16(data);
> +		break;
> +	case 4:
> +		data = cpu_to_le32(data);
> +		break;
> +	default:
> +		data = cpu_to_le64(data);
> +	}
> +
> +	kvm_mmio_write_buf(buf, len, data);
> +}
> +
> +static
> +struct vgic_io_device *kvm_to_vgic_iodev(const struct kvm_io_device *dev)
> +{
> +	return container_of(dev, struct vgic_io_device, dev);
> +}
> +
> +static bool check_region(const struct vgic_register_region *region,
> +			 gpa_t addr, int len)
> +{
> +	if ((region->access_flags & VGIC_ACCESS_8bit) && len == 1)
> +		return true;
> +	if ((region->access_flags & VGIC_ACCESS_32bit) &&
> +	    len == sizeof(u32) && !(addr & 3))
> +		return true;
> +	if ((region->access_flags & VGIC_ACCESS_64bit) &&
> +	    len == sizeof(u64) && !(addr & 7))
> +		return true;
> +
> +	return false;
> +}
> +
> +static int dispatch_mmio_read(struct kvm_vcpu *vcpu, struct kvm_io_device *dev,
> +			      gpa_t addr, int len, void *val)
> +{
> +	struct vgic_io_device *iodev = kvm_to_vgic_iodev(dev);
> +	const struct vgic_register_region *region;
> +	struct kvm_vcpu *r_vcpu;
> +	unsigned long data;
> +
> +	region = vgic_find_mmio_region(iodev->regions, iodev->nr_regions,
> +				       addr - iodev->base_addr);
> +	if (!region || !check_region(region, addr, len)) {
> +		memset(val, 0, len);
> +		return 0;
> +	}
> +
> +	r_vcpu = iodev->redist_vcpu ? iodev->redist_vcpu : vcpu;
> +	data = region->read(r_vcpu, addr, len);
> +	vgic_data_host_to_mmio_bus(val, len, data);
> +	return 0;
> +}
> +
> +static int dispatch_mmio_write(struct kvm_vcpu *vcpu, struct kvm_io_device *dev,
> +			       gpa_t addr, int len, const void *val)
> +{
> +	struct vgic_io_device *iodev = kvm_to_vgic_iodev(dev);
> +	const struct vgic_register_region *region;
> +	struct kvm_vcpu *r_vcpu;
> +	unsigned long data = vgic_data_mmio_bus_to_host(val, len);
> +
> +	region = vgic_find_mmio_region(iodev->regions, iodev->nr_regions,
> +				       addr - iodev->base_addr);
> +	if (!region)
> +		return 0;
> +
> +	if (!check_region(region, addr, len))
> +		return 0;
> +
> +	r_vcpu = iodev->redist_vcpu ? iodev->redist_vcpu : vcpu;
> +	region->write(r_vcpu, addr, len, data);
> +	return 0;
> +}
> +
> +struct kvm_io_device_ops kvm_io_gic_ops = {
> +	.read = dispatch_mmio_read,
> +	.write = dispatch_mmio_write,
> +};
> diff --git a/virt/kvm/arm/vgic/vgic-mmio.h b/virt/kvm/arm/vgic/vgic-mmio.h
> new file mode 100644
> index 0000000..855b1db
> --- /dev/null
> +++ b/virt/kvm/arm/vgic/vgic-mmio.h
> @@ -0,0 +1,87 @@
> +/*
> + * Copyright (C) 2015, 2016 ARM Ltd.
> + *
> + * This program is free software; you can redistribute it and/or modify
> + * it under the terms of the GNU General Public License version 2 as
> + * published by the Free Software Foundation.
> + *
> + * This program is distributed in the hope that it will be useful,
> + * but WITHOUT ANY WARRANTY; without even the implied warranty of
> + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
> + * GNU General Public License for more details.
> + *
> + * You should have received a copy of the GNU General Public License
> + * along with this program.  If not, see <http://www.gnu.org/licenses/>.
> + */
> +#ifndef __KVM_ARM_VGIC_MMIO_H__
> +#define __KVM_ARM_VGIC_MMIO_H__
> +
> +struct vgic_register_region {
> +	unsigned int reg_offset;
> +	unsigned int len;
> +	unsigned int bits_per_irq;
> +	unsigned int access_flags;
> +	unsigned long (*read)(struct kvm_vcpu *vcpu, gpa_t addr,
> +			      unsigned int len);
> +	void (*write)(struct kvm_vcpu *vcpu, gpa_t addr, unsigned int len,
> +		      unsigned long val);
> +};
> +
> +extern struct kvm_io_device_ops kvm_io_gic_ops;
> +
> +#define VGIC_ACCESS_8bit	1
> +#define VGIC_ACCESS_32bit	2
> +#define VGIC_ACCESS_64bit	4
> +
> +/* generate a mask that covers 1024 interrupts with <b> bits per IRQ */

Hmmm. I'd appreciate some additional comments, specially when it comes
to the various restrictions. May I'd suggest something like:

/*
 * Generate a mask that covers the number of bytes required to address
 * up to 1024 interrupts, each represented by <b> bits. This assumes
 * that <b> is a power of two.
 *
 * ilog2(b) + ilog2(1024) is the number of bits required to bit-address
 * 1024 interrupts, each represented by b bits. Minus ilog2(8) converts
 * this to a byte address.
 */

> +#define VGIC_ADDR_IRQ_MASK(b) GENMASK_ULL(ilog2(b) + ilog2(1024) - \
> +					  ilog2(BITS_PER_BYTE) - 1, 0)

/*
 * Convert a base address into a base interrupt (each interrupt
 * represented by <bits> bits. This assumes that <bits> is a power
 * of two, that <addr> both part of a memory region aligned on a
 * <b> bits boundary, and itself aligned on that same boundary
 * (for regions that describe an interrupt with more than a single
 * byte of data).
 */

> +#define VGIC_ADDR_TO_INTID(addr, bits)  (((addr) & VGIC_ADDR_IRQ_MASK(bits)) * \
> +					64 / (bits) / 8)
> +
> +/*
> + * Some VGIC registers store per-IRQ information, with a different number
> + * of bits per IRQ. For those registers this macro is used.
> + * The _WITH_LENGTH version instantiates registers with a fixed length
> + * and is mutually exclusive with the _PER_IRQ version.
> + */
> +#define REGISTER_DESC_WITH_BITS_PER_IRQ(off, rd, wr, bpi, acc)		\
> +	{								\
> +		.reg_offset = off,					\
> +		.bits_per_irq = bpi,					\
> +		.len = bpi * 1024 / 8,					\
> +		.access_flags = acc,					\
> +		.read = rd,						\
> +		.write = wr,						\
> +	}
> +
> +#define REGISTER_DESC_WITH_LENGTH(off, rd, wr, length, acc)		\
> +	{								\
> +		.reg_offset = off,					\
> +		.bits_per_irq = 0,					\
> +		.len = length,						\
> +		.access_flags = acc,					\
> +		.read = rd,						\
> +		.write = wr,						\
> +	}
> +
> +int kvm_vgic_register_mmio_region(struct kvm *kvm, struct kvm_vcpu *vcpu,
> +				  struct vgic_register_region *reg_desc,
> +				  struct vgic_io_device *region,
> +				  int nr_irqs, bool offset_private);
> +
> +unsigned long vgic_data_mmio_bus_to_host(const void *val, unsigned int len);
> +
> +void vgic_data_host_to_mmio_bus(void *buf, unsigned int len,
> +				unsigned long data);
> +
> +unsigned long vgic_mmio_read_raz(struct kvm_vcpu *vcpu,
> +				 gpa_t addr, unsigned int len);
> +
> +unsigned long vgic_mmio_read_rao(struct kvm_vcpu *vcpu,
> +				 gpa_t addr, unsigned int len);
> +
> +void vgic_mmio_write_wi(struct kvm_vcpu *vcpu, gpa_t addr,
> +			unsigned int len, unsigned long val);
> +
> +#endif
> 

Thanks,

	M.
-- 
Jazz is not dead. It just smells funny...

WARNING: multiple messages have this Message-ID (diff)
From: marc.zyngier@arm.com (Marc Zyngier)
To: linux-arm-kernel@lists.infradead.org
Subject: [PATCH v4 22/56] KVM: arm/arm64: vgic-new: Add MMIO handling framework
Date: Tue, 17 May 2016 14:33:36 +0100	[thread overview]
Message-ID: <573B1DB0.7030901@arm.com> (raw)
In-Reply-To: <1463392481-26583-23-git-send-email-andre.przywara@arm.com>

On 16/05/16 10:53, Andre Przywara wrote:
> From: Marc Zyngier <marc.zyngier@arm.com>
> 
> Add an MMIO handling framework to the VGIC emulation:
> Each register is described by its offset, size (or number of bits per
> IRQ, if applicable) and the read/write handler functions. We provide
> initialization macros to describe each GIC register later easily.
> 
> Separate dispatch functions for read and write accesses are connected
> to the kvm_io_bus framework and binary-search for the responsible
> register handler based on the offset address within the region.
> We convert the incoming data (referenced by a pointer) to the host's
> endianess and use pass-by-value to hand the data over to the actual
> handler functions.
> 
> The register handler prototype and the endianess conversion are
> courtesy of Christoffer Dall.
> 
> Signed-off-by: Marc Zyngier <marc.zyngier@arm.com>
> Signed-off-by: Christoffer Dall <christoffer.dall@linaro.org>
> Signed-off-by: Andre Przywara <andre.przywara@arm.com>
> ---
> Changelog RFC..v1:
> - rework MMIO dispatching to use only one kvm_io_bus device
> - document purpose of register region macros
> - rename "this" parameter to "dev"
> - change IGROUPR to be RAO (returning 1 => Group1 IRQs)
> 
> Changelog v1 .. v2:
> * MASSIVE rework:
> - store register_region pointer in kvm_io_bus linked struct
> - replace write_mask_xxx functions with extract_bytes() implementation
> - change handler functions' prototypes to take and return unsigned long
> - use binary search to find matching register handler
> - convert endianess of input data in dispatch_mmio_xxx functions
> - improve readability of register initializer macros
> - remove any GICv2/GICv3 specific functions from vgic-mmio.c
> - rename file from vgic_mmio.c to vgic-mmio.c
> 
> Changelog v2 .. v3:
> - replace inclusion of vgic/vgic.h with arm_vgic.h
> 
> Changelog v3 .. v4:
> - add IRQ number accessor macro
> - check access width in dispatcher
> - treat non-covered MMIO addresses as RAZ/WI
> - remove extract_bytes() (re-introduced as static later in the series)
> 
>  include/kvm/vgic/vgic.h       |  13 +++
>  virt/kvm/arm/vgic/vgic-mmio.c | 184 ++++++++++++++++++++++++++++++++++++++++++
>  virt/kvm/arm/vgic/vgic-mmio.h |  87 ++++++++++++++++++++
>  3 files changed, 284 insertions(+)
>  create mode 100644 virt/kvm/arm/vgic/vgic-mmio.c
>  create mode 100644 virt/kvm/arm/vgic/vgic-mmio.h
> 
> diff --git a/include/kvm/vgic/vgic.h b/include/kvm/vgic/vgic.h
> index f663288..ff3f9c2 100644
> --- a/include/kvm/vgic/vgic.h
> +++ b/include/kvm/vgic/vgic.h
> @@ -106,6 +106,16 @@ struct vgic_irq {
>  	enum vgic_irq_config config;	/* Level or edge */
>  };
>  
> +struct vgic_register_region;
> +
> +struct vgic_io_device {
> +	gpa_t base_addr;
> +	struct kvm_vcpu *redist_vcpu;
> +	const struct vgic_register_region *regions;
> +	int nr_regions;
> +	struct kvm_io_device dev;
> +};
> +
>  struct vgic_dist {
>  	bool			in_kernel;
>  	bool			ready;
> @@ -132,6 +142,9 @@ struct vgic_dist {
>  	bool			enabled;
>  
>  	struct vgic_irq		*spis;
> +
> +	struct vgic_io_device	dist_iodev;
> +	struct vgic_io_device	*redist_iodevs;
>  };
>  
>  struct vgic_v2_cpu_if {
> diff --git a/virt/kvm/arm/vgic/vgic-mmio.c b/virt/kvm/arm/vgic/vgic-mmio.c
> new file mode 100644
> index 0000000..012b82b
> --- /dev/null
> +++ b/virt/kvm/arm/vgic/vgic-mmio.c
> @@ -0,0 +1,184 @@
> +/*
> + * VGIC MMIO handling functions
> + *
> + * This program is free software; you can redistribute it and/or modify
> + * it under the terms of the GNU General Public License version 2 as
> + * published by the Free Software Foundation.
> + *
> + * This program is distributed in the hope that it will be useful,
> + * but WITHOUT ANY WARRANTY; without even the implied warranty of
> + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
> + * GNU General Public License for more details.
> + */
> +
> +#include <linux/bitops.h>
> +#include <linux/bsearch.h>
> +#include <linux/kvm.h>
> +#include <linux/kvm_host.h>
> +#include <kvm/iodev.h>
> +#include <kvm/arm_vgic.h>
> +
> +#include "vgic.h"
> +#include "vgic-mmio.h"
> +
> +unsigned long vgic_mmio_read_raz(struct kvm_vcpu *vcpu,
> +				 gpa_t addr, unsigned int len)
> +{
> +	return 0;
> +}
> +
> +unsigned long vgic_mmio_read_rao(struct kvm_vcpu *vcpu,
> +				 gpa_t addr, unsigned int len)
> +{
> +	return -1UL;
> +}
> +
> +void vgic_mmio_write_wi(struct kvm_vcpu *vcpu, gpa_t addr,
> +			unsigned int len, unsigned long val)
> +{
> +	/* Ignore */
> +}
> +
> +static int match_region(const void *key, const void *elt)
> +{
> +	const unsigned int offset = (unsigned long)key;
> +	const struct vgic_register_region *region = elt;
> +
> +	if (offset < region->reg_offset)
> +		return -1;
> +
> +	if (offset >= region->reg_offset + region->len)
> +		return 1;
> +
> +	return 0;
> +}
> +
> +/* Find the proper register handler entry given a certain address offset. */
> +static const struct vgic_register_region *
> +vgic_find_mmio_region(const struct vgic_register_region *region, int nr_regions,
> +		      unsigned int offset)
> +{
> +	return bsearch((void *)(uintptr_t)offset, region, nr_regions,
> +		       sizeof(region[0]), match_region);
> +}
> +
> +/*
> + * kvm_mmio_read_buf() returns a value in a format where it can be converted
> + * to a byte array and be directly observed as the guest wanted it to appear
> + * in memory if it had done the store itself, which is LE for the GIC, as the
> + * guest knows the GIC is always LE.
> + *
> + * We convert this value to the CPUs native format to deal with it as a data
> + * value.
> + */
> +unsigned long vgic_data_mmio_bus_to_host(const void *val, unsigned int len)
> +{
> +	unsigned long data = kvm_mmio_read_buf(val, len);
> +
> +	switch (len) {
> +	case 1:
> +		return data;
> +	case 2:
> +		return le16_to_cpu(data);
> +	case 4:
> +		return le32_to_cpu(data);
> +	default:
> +		return le64_to_cpu(data);
> +	}
> +}
> +
> +/*
> + * kvm_mmio_write_buf() expects a value in a format such that if converted to
> + * a byte array it is observed as the guest would see it if it could perform
> + * the load directly.  Since the GIC is LE, and the guest knows this, the
> + * guest expects a value in little endian format.
> + *
> + * We convert the data value from the CPUs native format to LE so that the
> + * value is returned in the proper format.
> + */
> +void vgic_data_host_to_mmio_bus(void *buf, unsigned int len,
> +				unsigned long data)
> +{
> +	switch (len) {
> +	case 1:
> +		break;
> +	case 2:
> +		data = cpu_to_le16(data);
> +		break;
> +	case 4:
> +		data = cpu_to_le32(data);
> +		break;
> +	default:
> +		data = cpu_to_le64(data);
> +	}
> +
> +	kvm_mmio_write_buf(buf, len, data);
> +}
> +
> +static
> +struct vgic_io_device *kvm_to_vgic_iodev(const struct kvm_io_device *dev)
> +{
> +	return container_of(dev, struct vgic_io_device, dev);
> +}
> +
> +static bool check_region(const struct vgic_register_region *region,
> +			 gpa_t addr, int len)
> +{
> +	if ((region->access_flags & VGIC_ACCESS_8bit) && len == 1)
> +		return true;
> +	if ((region->access_flags & VGIC_ACCESS_32bit) &&
> +	    len == sizeof(u32) && !(addr & 3))
> +		return true;
> +	if ((region->access_flags & VGIC_ACCESS_64bit) &&
> +	    len == sizeof(u64) && !(addr & 7))
> +		return true;
> +
> +	return false;
> +}
> +
> +static int dispatch_mmio_read(struct kvm_vcpu *vcpu, struct kvm_io_device *dev,
> +			      gpa_t addr, int len, void *val)
> +{
> +	struct vgic_io_device *iodev = kvm_to_vgic_iodev(dev);
> +	const struct vgic_register_region *region;
> +	struct kvm_vcpu *r_vcpu;
> +	unsigned long data;
> +
> +	region = vgic_find_mmio_region(iodev->regions, iodev->nr_regions,
> +				       addr - iodev->base_addr);
> +	if (!region || !check_region(region, addr, len)) {
> +		memset(val, 0, len);
> +		return 0;
> +	}
> +
> +	r_vcpu = iodev->redist_vcpu ? iodev->redist_vcpu : vcpu;
> +	data = region->read(r_vcpu, addr, len);
> +	vgic_data_host_to_mmio_bus(val, len, data);
> +	return 0;
> +}
> +
> +static int dispatch_mmio_write(struct kvm_vcpu *vcpu, struct kvm_io_device *dev,
> +			       gpa_t addr, int len, const void *val)
> +{
> +	struct vgic_io_device *iodev = kvm_to_vgic_iodev(dev);
> +	const struct vgic_register_region *region;
> +	struct kvm_vcpu *r_vcpu;
> +	unsigned long data = vgic_data_mmio_bus_to_host(val, len);
> +
> +	region = vgic_find_mmio_region(iodev->regions, iodev->nr_regions,
> +				       addr - iodev->base_addr);
> +	if (!region)
> +		return 0;
> +
> +	if (!check_region(region, addr, len))
> +		return 0;
> +
> +	r_vcpu = iodev->redist_vcpu ? iodev->redist_vcpu : vcpu;
> +	region->write(r_vcpu, addr, len, data);
> +	return 0;
> +}
> +
> +struct kvm_io_device_ops kvm_io_gic_ops = {
> +	.read = dispatch_mmio_read,
> +	.write = dispatch_mmio_write,
> +};
> diff --git a/virt/kvm/arm/vgic/vgic-mmio.h b/virt/kvm/arm/vgic/vgic-mmio.h
> new file mode 100644
> index 0000000..855b1db
> --- /dev/null
> +++ b/virt/kvm/arm/vgic/vgic-mmio.h
> @@ -0,0 +1,87 @@
> +/*
> + * Copyright (C) 2015, 2016 ARM Ltd.
> + *
> + * This program is free software; you can redistribute it and/or modify
> + * it under the terms of the GNU General Public License version 2 as
> + * published by the Free Software Foundation.
> + *
> + * This program is distributed in the hope that it will be useful,
> + * but WITHOUT ANY WARRANTY; without even the implied warranty of
> + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
> + * GNU General Public License for more details.
> + *
> + * You should have received a copy of the GNU General Public License
> + * along with this program.  If not, see <http://www.gnu.org/licenses/>.
> + */
> +#ifndef __KVM_ARM_VGIC_MMIO_H__
> +#define __KVM_ARM_VGIC_MMIO_H__
> +
> +struct vgic_register_region {
> +	unsigned int reg_offset;
> +	unsigned int len;
> +	unsigned int bits_per_irq;
> +	unsigned int access_flags;
> +	unsigned long (*read)(struct kvm_vcpu *vcpu, gpa_t addr,
> +			      unsigned int len);
> +	void (*write)(struct kvm_vcpu *vcpu, gpa_t addr, unsigned int len,
> +		      unsigned long val);
> +};
> +
> +extern struct kvm_io_device_ops kvm_io_gic_ops;
> +
> +#define VGIC_ACCESS_8bit	1
> +#define VGIC_ACCESS_32bit	2
> +#define VGIC_ACCESS_64bit	4
> +
> +/* generate a mask that covers 1024 interrupts with <b> bits per IRQ */

Hmmm. I'd appreciate some additional comments, specially when it comes
to the various restrictions. May I'd suggest something like:

/*
 * Generate a mask that covers the number of bytes required to address
 * up to 1024 interrupts, each represented by <b> bits. This assumes
 * that <b> is a power of two.
 *
 * ilog2(b) + ilog2(1024) is the number of bits required to bit-address
 * 1024 interrupts, each represented by b bits. Minus ilog2(8) converts
 * this to a byte address.
 */

> +#define VGIC_ADDR_IRQ_MASK(b) GENMASK_ULL(ilog2(b) + ilog2(1024) - \
> +					  ilog2(BITS_PER_BYTE) - 1, 0)

/*
 * Convert a base address into a base interrupt (each interrupt
 * represented by <bits> bits. This assumes that <bits> is a power
 * of two, that <addr> both part of a memory region aligned on a
 * <b> bits boundary, and itself aligned on that same boundary
 * (for regions that describe an interrupt with more than a single
 * byte of data).
 */

> +#define VGIC_ADDR_TO_INTID(addr, bits)  (((addr) & VGIC_ADDR_IRQ_MASK(bits)) * \
> +					64 / (bits) / 8)
> +
> +/*
> + * Some VGIC registers store per-IRQ information, with a different number
> + * of bits per IRQ. For those registers this macro is used.
> + * The _WITH_LENGTH version instantiates registers with a fixed length
> + * and is mutually exclusive with the _PER_IRQ version.
> + */
> +#define REGISTER_DESC_WITH_BITS_PER_IRQ(off, rd, wr, bpi, acc)		\
> +	{								\
> +		.reg_offset = off,					\
> +		.bits_per_irq = bpi,					\
> +		.len = bpi * 1024 / 8,					\
> +		.access_flags = acc,					\
> +		.read = rd,						\
> +		.write = wr,						\
> +	}
> +
> +#define REGISTER_DESC_WITH_LENGTH(off, rd, wr, length, acc)		\
> +	{								\
> +		.reg_offset = off,					\
> +		.bits_per_irq = 0,					\
> +		.len = length,						\
> +		.access_flags = acc,					\
> +		.read = rd,						\
> +		.write = wr,						\
> +	}
> +
> +int kvm_vgic_register_mmio_region(struct kvm *kvm, struct kvm_vcpu *vcpu,
> +				  struct vgic_register_region *reg_desc,
> +				  struct vgic_io_device *region,
> +				  int nr_irqs, bool offset_private);
> +
> +unsigned long vgic_data_mmio_bus_to_host(const void *val, unsigned int len);
> +
> +void vgic_data_host_to_mmio_bus(void *buf, unsigned int len,
> +				unsigned long data);
> +
> +unsigned long vgic_mmio_read_raz(struct kvm_vcpu *vcpu,
> +				 gpa_t addr, unsigned int len);
> +
> +unsigned long vgic_mmio_read_rao(struct kvm_vcpu *vcpu,
> +				 gpa_t addr, unsigned int len);
> +
> +void vgic_mmio_write_wi(struct kvm_vcpu *vcpu, gpa_t addr,
> +			unsigned int len, unsigned long val);
> +
> +#endif
> 

Thanks,

	M.
-- 
Jazz is not dead. It just smells funny...

  reply	other threads:[~2016-05-17 13:30 UTC|newest]

Thread overview: 316+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2016-05-16  9:52 [PATCH v4 00/56] KVM: arm/arm64: Rework virtual GIC emulation Andre Przywara
2016-05-16  9:52 ` Andre Przywara
2016-05-16  9:52 ` [PATCH v4 01/56] KVM: arm/arm64: vgic: streamline vgic_update_irq_pending() interface Andre Przywara
2016-05-16  9:52   ` Andre Przywara
2016-05-16  9:52 ` [PATCH v4 02/56] KVM: arm/arm64: vgic: avoid map in kvm_vgic_inject_mapped_irq() Andre Przywara
2016-05-16  9:52   ` Andre Przywara
2016-05-16  9:52 ` [PATCH v4 03/56] KVM: arm/arm64: vgic: avoid map in kvm_vgic_map_is_active() Andre Przywara
2016-05-16  9:52   ` Andre Przywara
2016-05-16  9:52 ` [PATCH v4 04/56] KVM: arm/arm64: vgic: avoid map in kvm_vgic_unmap_phys_irq() Andre Przywara
2016-05-16  9:52   ` Andre Przywara
2016-05-16  9:52 ` [PATCH v4 05/56] KVM: arm/arm64: Remove the IRQ field from struct irq_phys_map Andre Przywara
2016-05-16  9:52   ` Andre Przywara
2016-05-16  9:52 ` [PATCH v4 06/56] KVM: arm/arm64: arch_timer: Remove irq_phys_map Andre Przywara
2016-05-16  9:52   ` Andre Przywara
2016-05-16  9:52 ` [PATCH v4 07/56] KVM: arm/arm64: vgic: Remove irq_phys_map from interface Andre Przywara
2016-05-16  9:52   ` Andre Przywara
2016-05-16  9:52 ` [PATCH v4 08/56] KVM: arm/arm64: Get rid of vgic_cpu->nr_lr Andre Przywara
2016-05-16  9:52   ` Andre Przywara
2016-05-16  9:52 ` [PATCH v4 09/56] KVM: arm/arm64: Fix MMIO emulation data handling Andre Przywara
2016-05-16  9:52   ` Andre Przywara
2016-05-16  9:52 ` [PATCH v4 10/56] KVM: arm/arm64: Export mmio_read/write_bus Andre Przywara
2016-05-16  9:52   ` Andre Przywara
2016-05-16  9:52 ` [PATCH v4 11/56] KVM: arm/arm64: pmu: abstract access to number of SPIs Andre Przywara
2016-05-16  9:52   ` Andre Przywara
2016-05-18 10:27   ` Christoffer Dall
2016-05-18 10:27     ` Christoffer Dall
2016-05-16  9:53 ` [PATCH v4 12/56] KVM: arm/arm64: Provide functionality to pause and resume a guest Andre Przywara
2016-05-16  9:53   ` Andre Przywara
2016-05-16  9:53 ` [PATCH v4 13/56] KVM: arm/arm64: move GICv2 emulation defines into arm-gic-v3.h Andre Przywara
2016-05-16  9:53   ` Andre Przywara
2016-05-16  9:53 ` [PATCH v4 14/56] KVM: arm/arm64: vgic-new: Add data structure definitions Andre Przywara
2016-05-16  9:53   ` Andre Przywara
2016-05-16  9:53 ` [PATCH v4 15/56] KVM: arm/arm64: vgic-new: Add acccessor to new struct vgic_irq instance Andre Przywara
2016-05-16  9:53   ` Andre Przywara
2016-05-16  9:53 ` [PATCH v4 16/56] KVM: arm/arm64: vgic-new: Implement virtual IRQ injection Andre Przywara
2016-05-16  9:53   ` Andre Przywara
2016-05-18 14:14   ` Christoffer Dall
2016-05-18 14:14     ` Christoffer Dall
2016-05-16  9:53 ` [PATCH v4 17/56] KVM: arm/arm64: vgic-new: Add IRQ sorting Andre Przywara
2016-05-16  9:53   ` Andre Przywara
2016-05-18 11:49   ` Christoffer Dall
2016-05-18 11:49     ` Christoffer Dall
2016-05-16  9:53 ` [PATCH v4 18/56] KVM: arm/arm64: vgic-new: Add IRQ sync/flush framework Andre Przywara
2016-05-16  9:53   ` Andre Przywara
2016-05-17 10:55   ` Marc Zyngier
2016-05-17 10:55     ` Marc Zyngier
2016-05-16  9:53 ` [PATCH v4 19/56] KVM: arm/arm64: vgic-new: Add GICv2 world switch backend Andre Przywara
2016-05-16  9:53   ` Andre Przywara
2016-05-16  9:53 ` [PATCH v4 20/56] KVM: arm/arm64: vgic-new: Add GICv3 " Andre Przywara
2016-05-16  9:53   ` Andre Przywara
2016-05-18 14:14   ` Christoffer Dall
2016-05-18 14:14     ` Christoffer Dall
2016-05-16  9:53 ` [PATCH v4 21/56] KVM: arm/arm64: vgic-new: Implement kvm_vgic_vcpu_pending_irq Andre Przywara
2016-05-16  9:53   ` Andre Przywara
2016-05-16  9:53 ` [PATCH v4 22/56] KVM: arm/arm64: vgic-new: Add MMIO handling framework Andre Przywara
2016-05-16  9:53   ` Andre Przywara
2016-05-17 13:33   ` Marc Zyngier [this message]
2016-05-17 13:33     ` Marc Zyngier
2016-05-18 12:25     ` Christoffer Dall
2016-05-18 12:25       ` Christoffer Dall
2016-05-18 14:12       ` Marc Zyngier
2016-05-18 14:12         ` Marc Zyngier
2016-05-18 14:29         ` Christoffer Dall
2016-05-18 14:29           ` Christoffer Dall
2016-05-18 16:46       ` Andre Przywara
2016-05-18 16:46         ` Andre Przywara
2016-05-18 17:08         ` Christoffer Dall
2016-05-18 17:08           ` Christoffer Dall
2016-05-18 12:31   ` Christoffer Dall
2016-05-18 12:31     ` Christoffer Dall
2016-05-18 15:55     ` Andre Przywara
2016-05-18 15:55       ` Andre Przywara
2016-05-18 18:06       ` Christoffer Dall
2016-05-18 18:06         ` Christoffer Dall
2016-05-16  9:53 ` [PATCH v4 23/56] KVM: arm/arm64: vgic-new: Add GICv2 " Andre Przywara
2016-05-16  9:53   ` Andre Przywara
2016-05-16  9:53 ` [PATCH v4 24/56] KVM: arm/arm64: vgic-new: Add CTLR, TYPER and IIDR handlers Andre Przywara
2016-05-16  9:53   ` Andre Przywara
2016-05-18 12:33   ` Christoffer Dall
2016-05-18 12:33     ` Christoffer Dall
2016-05-16  9:53 ` [PATCH v4 25/56] KVM: arm/arm64: vgic-new: Add ENABLE registers handlers Andre Przywara
2016-05-16  9:53   ` Andre Przywara
2016-05-18 14:14   ` Christoffer Dall
2016-05-18 14:14     ` Christoffer Dall
2016-05-16  9:53 ` [PATCH v4 26/56] KVM: arm/arm64: vgic-new: Add PENDING " Andre Przywara
2016-05-16  9:53   ` Andre Przywara
2016-05-18 14:15   ` Christoffer Dall
2016-05-18 14:15     ` Christoffer Dall
2016-05-16  9:53 ` [PATCH v4 27/56] KVM: arm/arm64: vgic-new: Add ACTIVE " Andre Przywara
2016-05-16  9:53   ` Andre Przywara
2016-05-18 13:01   ` Christoffer Dall
2016-05-18 13:01     ` Christoffer Dall
2016-05-19 10:12     ` Andre Przywara
2016-05-19 10:12       ` Andre Przywara
2016-05-16  9:53 ` [PATCH v4 28/56] KVM: arm/arm64: vgic-new: Add PRIORITY " Andre Przywara
2016-05-16  9:53   ` Andre Przywara
2016-05-18 14:15   ` Christoffer Dall
2016-05-18 14:15     ` Christoffer Dall
2016-05-16  9:53 ` [PATCH v4 29/56] KVM: arm/arm64: vgic-new: Add CONFIG " Andre Przywara
2016-05-16  9:53   ` Andre Przywara
2016-05-18 13:08   ` Christoffer Dall
2016-05-18 13:08     ` Christoffer Dall
2016-05-16  9:53 ` [PATCH v4 30/56] KVM: arm/arm64: vgic-new: Add TARGET " Andre Przywara
2016-05-16  9:53   ` Andre Przywara
2016-05-18 14:15   ` Christoffer Dall
2016-05-18 14:15     ` Christoffer Dall
2016-05-16  9:53 ` [PATCH v4 31/56] KVM: arm/arm64: vgic-new: Add SGIR register handler Andre Przywara
2016-05-16  9:53   ` Andre Przywara
2016-05-16  9:53 ` [PATCH v4 32/56] KVM: arm/arm64: vgic-new: Add SGIPENDR register handlers Andre Przywara
2016-05-16  9:53   ` Andre Przywara
2016-05-18 13:14   ` Christoffer Dall
2016-05-18 13:14     ` Christoffer Dall
2016-05-18 13:31     ` Andre Przywara
2016-05-18 13:31       ` Andre Przywara
2016-05-18 13:50       ` Christoffer Dall
2016-05-18 13:50         ` Christoffer Dall
2016-05-19 13:25         ` Andre Przywara
2016-05-19 13:25           ` Andre Przywara
2016-05-19 14:09           ` Christoffer Dall
2016-05-19 14:09             ` Christoffer Dall
2016-05-16  9:53 ` [PATCH v4 33/56] KVM: arm/arm64: vgic-new: Add GICv3 MMIO handling framework Andre Przywara
2016-05-16  9:53   ` Andre Przywara
2016-05-18 13:21   ` Christoffer Dall
2016-05-18 13:21     ` Christoffer Dall
2016-05-16  9:53 ` [PATCH v4 34/56] KVM: arm/arm64: vgic-new: Add GICv3 CTLR, IIDR, TYPER handlers Andre Przywara
2016-05-16  9:53   ` Andre Przywara
2016-05-18 14:15   ` Christoffer Dall
2016-05-18 14:15     ` Christoffer Dall
2016-05-16  9:53 ` [PATCH v4 35/56] KVM: arm/arm64: vgic-new: Add GICv3 redistributor IIDR and TYPER handler Andre Przywara
2016-05-16  9:53   ` Andre Przywara
2016-05-18 14:15   ` Christoffer Dall
2016-05-18 14:15     ` Christoffer Dall
2016-05-16  9:53 ` [PATCH v4 36/56] KVM: arm/arm64: vgic-new: Add GICv3 IDREGS register handler Andre Przywara
2016-05-16  9:53   ` Andre Przywara
2016-05-18 14:14   ` Christoffer Dall
2016-05-18 14:14     ` Christoffer Dall
2016-05-18 14:16   ` Christoffer Dall
2016-05-18 14:16     ` Christoffer Dall
2016-05-16  9:53 ` [PATCH v4 37/56] KVM: arm/arm64: vgic-new: Add GICv3 IROUTER register handlers Andre Przywara
2016-05-16  9:53   ` Andre Przywara
2016-05-18 13:49   ` Christoffer Dall
2016-05-18 13:49     ` Christoffer Dall
2016-05-16  9:53 ` [PATCH v4 38/56] KVM: arm/arm64: vgic-new: Add GICv3 SGI system register trap handler Andre Przywara
2016-05-16  9:53   ` Andre Przywara
2016-05-18 13:53   ` Christoffer Dall
2016-05-18 13:53     ` Christoffer Dall
2016-05-16  9:53 ` [PATCH v4 39/56] KVM: arm/arm64: vgic-new: vgic_kvm_device: KVM device ops registration Andre Przywara
2016-05-16  9:53   ` Andre Przywara
2016-05-16  9:53 ` [PATCH v4 40/56] KVM: arm/arm64: vgic-new: vgic_kvm_device: KVM_DEV_ARM_VGIC_GRP_NR_IRQS Andre Przywara
2016-05-16  9:53   ` Andre Przywara
2016-05-16  9:53 ` [PATCH v4 41/56] KVM: arm/arm64: vgic-new: vgic_kvm_device: KVM_DEV_ARM_VGIC_GRP_CTRL Andre Przywara
2016-05-16  9:53   ` Andre Przywara
2016-05-16  9:53 ` [PATCH v4 42/56] KVM: arm/arm64: vgic-new: vgic_kvm_device: implement kvm_vgic_addr Andre Przywara
2016-05-16  9:53   ` Andre Przywara
2016-05-16  9:53 ` [PATCH v4 43/56] KVM: arm/arm64: vgic-new: vgic_kvm_device: KVM_DEV_ARM_VGIC_GRP_ADDR Andre Przywara
2016-05-16  9:53   ` Andre Przywara
2016-05-16  9:53 ` [PATCH v4 44/56] KVM: arm/arm64: vgic-new: vgic_kvm_device: access to VGIC registers Andre Przywara
2016-05-16  9:53   ` Andre Przywara
2016-05-18 13:55   ` Christoffer Dall
2016-05-18 13:55     ` Christoffer Dall
2016-05-16  9:53 ` [PATCH v4 45/56] KVM: arm/arm64: vgic-new: Export register access interface Andre Przywara
2016-05-16  9:53   ` Andre Przywara
2016-05-16  9:53 ` [PATCH v4 46/56] KVM: arm/arm64: vgic-new: Add userland access to VGIC dist registers Andre Przywara
2016-05-16  9:53   ` Andre Przywara
2016-05-18 13:57   ` Christoffer Dall
2016-05-18 13:57     ` Christoffer Dall
2016-05-18 14:06     ` Andre Przywara
2016-05-18 14:06       ` Andre Przywara
2016-05-18 15:12       ` Christoffer Dall
2016-05-18 15:12         ` Christoffer Dall
2016-05-16  9:53 ` [PATCH v4 47/56] KVM: arm/arm64: vgic-new: Add GICH_VMCR accessors Andre Przywara
2016-05-16  9:53   ` Andre Przywara
2016-05-18 13:59   ` Christoffer Dall
2016-05-18 13:59     ` Christoffer Dall
2016-05-16  9:53 ` [PATCH v4 48/56] KVM: arm/arm64: vgic-new: Add userland GIC CPU interface access Andre Przywara
2016-05-16  9:53   ` Andre Przywara
2016-05-18 14:02   ` Christoffer Dall
2016-05-18 14:02     ` Christoffer Dall
2016-05-16  9:53 ` [PATCH v4 49/56] KVM: arm/arm64: vgic-new: vgic_init: implement kvm_vgic_hyp_init Andre Przywara
2016-05-16  9:53   ` Andre Przywara
2016-05-18 14:08   ` Christoffer Dall
2016-05-18 14:08     ` Christoffer Dall
2016-05-16  9:53 ` [PATCH v4 50/56] KVM: arm/arm64: vgic-new: vgic_init: implement vgic_create Andre Przywara
2016-05-16  9:53   ` Andre Przywara
2016-05-18 14:11   ` Christoffer Dall
2016-05-18 14:11     ` Christoffer Dall
2016-05-16  9:53 ` [PATCH v4 51/56] KVM: arm/arm64: vgic-new: vgic_init: implement vgic_init Andre Przywara
2016-05-16  9:53   ` Andre Przywara
2016-05-16  9:53 ` [PATCH v4 52/56] KVM: arm/arm64: vgic-new: vgic_init: implement map_resources Andre Przywara
2016-05-16  9:53   ` Andre Przywara
2016-05-16  9:53 ` [PATCH v4 53/56] KVM: arm/arm64: vgic-new: Add vgic_v2/v3_enable Andre Przywara
2016-05-16  9:53   ` Andre Przywara
2016-05-16  9:53 ` [PATCH v4 54/56] KVM: arm/arm64: vgic-new: Wire up irqfd injection Andre Przywara
2016-05-16  9:53   ` Andre Przywara
2016-05-16  9:53 ` [PATCH v4 55/56] KVM: arm/arm64: vgic-new: implement mapped IRQ handling Andre Przywara
2016-05-16  9:53   ` Andre Przywara
2016-05-16  9:53 ` [PATCH v4 56/56] KVM: arm/arm64: vgic-new: enable build Andre Przywara
2016-05-16  9:53   ` Andre Przywara
2016-05-16  9:53 ` [PATCH v4 00/56] KVM: arm/arm64: Rework virtual GIC emulation Andre Przywara
2016-05-16  9:53   ` Andre Przywara
2016-05-16 10:14   ` Andre Przywara
2016-05-16 10:14     ` Andre Przywara
2016-05-16  9:53 ` [PATCH v4 01/56] KVM: arm/arm64: vgic: streamline vgic_update_irq_pending() interface Andre Przywara
2016-05-16  9:53   ` Andre Przywara
2016-05-16  9:53 ` [PATCH v4 02/56] KVM: arm/arm64: vgic: avoid map in kvm_vgic_inject_mapped_irq() Andre Przywara
2016-05-16  9:53   ` Andre Przywara
2016-05-16  9:53 ` [PATCH v4 03/56] KVM: arm/arm64: vgic: avoid map in kvm_vgic_map_is_active() Andre Przywara
2016-05-16  9:53   ` Andre Przywara
2016-05-16  9:53 ` [PATCH v4 04/56] KVM: arm/arm64: vgic: avoid map in kvm_vgic_unmap_phys_irq() Andre Przywara
2016-05-16  9:53   ` Andre Przywara
2016-05-16  9:53 ` [PATCH v4 05/56] KVM: arm/arm64: Remove the IRQ field from struct irq_phys_map Andre Przywara
2016-05-16  9:53   ` Andre Przywara
2016-05-16  9:53 ` [PATCH v4 06/56] KVM: arm/arm64: arch_timer: Remove irq_phys_map Andre Przywara
2016-05-16  9:53   ` Andre Przywara
2016-05-16  9:53 ` [PATCH v4 07/56] KVM: arm/arm64: vgic: Remove irq_phys_map from interface Andre Przywara
2016-05-16  9:53   ` Andre Przywara
2016-05-16  9:53 ` [PATCH v4 08/56] KVM: arm/arm64: Get rid of vgic_cpu->nr_lr Andre Przywara
2016-05-16  9:53   ` Andre Przywara
2016-05-16  9:53 ` [PATCH v4 09/56] KVM: arm/arm64: Fix MMIO emulation data handling Andre Przywara
2016-05-16  9:53   ` Andre Przywara
2016-05-16  9:53 ` [PATCH v4 10/56] KVM: arm/arm64: Export mmio_read/write_bus Andre Przywara
2016-05-16  9:53   ` Andre Przywara
2016-05-16  9:53 ` [PATCH v4 11/56] KVM: arm/arm64: pmu: abstract access to number of SPIs Andre Przywara
2016-05-16  9:53   ` Andre Przywara
2016-05-16  9:53 ` [PATCH v4 12/56] KVM: arm/arm64: Provide functionality to pause and resume a guest Andre Przywara
2016-05-16  9:53   ` Andre Przywara
2016-05-16  9:53 ` [PATCH v4 13/56] KVM: arm/arm64: move GICv2 emulation defines into arm-gic-v3.h Andre Przywara
2016-05-16  9:53   ` Andre Przywara
2016-05-16  9:53 ` [PATCH v4 14/56] KVM: arm/arm64: vgic-new: Add data structure definitions Andre Przywara
2016-05-16  9:53   ` Andre Przywara
2016-05-16  9:54 ` [PATCH v4 15/56] KVM: arm/arm64: vgic-new: Add acccessor to new struct vgic_irq instance Andre Przywara
2016-05-16  9:54   ` Andre Przywara
2016-05-16  9:54 ` [PATCH v4 16/56] KVM: arm/arm64: vgic-new: Implement virtual IRQ injection Andre Przywara
2016-05-16  9:54   ` Andre Przywara
2016-05-16  9:54 ` [PATCH v4 17/56] KVM: arm/arm64: vgic-new: Add IRQ sorting Andre Przywara
2016-05-16  9:54   ` Andre Przywara
2016-05-16  9:54 ` [PATCH v4 18/56] KVM: arm/arm64: vgic-new: Add IRQ sync/flush framework Andre Przywara
2016-05-16  9:54   ` Andre Przywara
2016-05-16  9:54 ` [PATCH v4 19/56] KVM: arm/arm64: vgic-new: Add GICv2 world switch backend Andre Przywara
2016-05-16  9:54   ` Andre Przywara
2016-05-16  9:54 ` [PATCH v4 20/56] KVM: arm/arm64: vgic-new: Add GICv3 " Andre Przywara
2016-05-16  9:54   ` Andre Przywara
2016-05-16  9:54 ` [PATCH v4 21/56] KVM: arm/arm64: vgic-new: Implement kvm_vgic_vcpu_pending_irq Andre Przywara
2016-05-16  9:54   ` Andre Przywara
2016-05-16  9:54 ` [PATCH v4 22/56] KVM: arm/arm64: vgic-new: Add MMIO handling framework Andre Przywara
2016-05-16  9:54   ` Andre Przywara
2016-05-16  9:54 ` [PATCH v4 23/56] KVM: arm/arm64: vgic-new: Add GICv2 " Andre Przywara
2016-05-16  9:54   ` Andre Przywara
2016-05-16  9:54 ` [PATCH v4 24/56] KVM: arm/arm64: vgic-new: Add CTLR, TYPER and IIDR handlers Andre Przywara
2016-05-16  9:54   ` Andre Przywara
2016-05-16  9:54 ` [PATCH v4 25/56] KVM: arm/arm64: vgic-new: Add ENABLE registers handlers Andre Przywara
2016-05-16  9:54   ` Andre Przywara
2016-05-16  9:54 ` [PATCH v4 26/56] KVM: arm/arm64: vgic-new: Add PENDING " Andre Przywara
2016-05-16  9:54   ` Andre Przywara
2016-05-16  9:54 ` [PATCH v4 27/56] KVM: arm/arm64: vgic-new: Add ACTIVE " Andre Przywara
2016-05-16  9:54   ` Andre Przywara
2016-05-16  9:54 ` [PATCH v4 28/56] KVM: arm/arm64: vgic-new: Add PRIORITY " Andre Przywara
2016-05-16  9:54   ` Andre Przywara
2016-05-16  9:54 ` [PATCH v4 29/56] KVM: arm/arm64: vgic-new: Add CONFIG " Andre Przywara
2016-05-16  9:54   ` Andre Przywara
2016-05-16  9:54 ` [PATCH v4 30/56] KVM: arm/arm64: vgic-new: Add TARGET " Andre Przywara
2016-05-16  9:54   ` Andre Przywara
2016-05-16  9:54 ` [PATCH v4 31/56] KVM: arm/arm64: vgic-new: Add SGIR register handler Andre Przywara
2016-05-16  9:54   ` Andre Przywara
2016-05-16  9:54 ` [PATCH v4 32/56] KVM: arm/arm64: vgic-new: Add SGIPENDR register handlers Andre Przywara
2016-05-16  9:54   ` Andre Przywara
2016-05-16  9:54 ` [PATCH v4 33/56] KVM: arm/arm64: vgic-new: Add GICv3 MMIO handling framework Andre Przywara
2016-05-16  9:54   ` Andre Przywara
2016-05-16  9:54 ` [PATCH v4 34/56] KVM: arm/arm64: vgic-new: Add GICv3 CTLR, IIDR, TYPER handlers Andre Przywara
2016-05-16  9:54   ` Andre Przywara
2016-05-16  9:54 ` [PATCH v4 35/56] KVM: arm/arm64: vgic-new: Add GICv3 redistributor IIDR and TYPER handler Andre Przywara
2016-05-16  9:54   ` Andre Przywara
2016-05-16  9:54 ` [PATCH v4 36/56] KVM: arm/arm64: vgic-new: Add GICv3 IDREGS register handler Andre Przywara
2016-05-16  9:54   ` Andre Przywara
2016-05-16  9:54 ` [PATCH v4 37/56] KVM: arm/arm64: vgic-new: Add GICv3 IROUTER register handlers Andre Przywara
2016-05-16  9:54   ` Andre Przywara
2016-05-16  9:54 ` [PATCH v4 38/56] KVM: arm/arm64: vgic-new: Add GICv3 SGI system register trap handler Andre Przywara
2016-05-16  9:54   ` Andre Przywara
2016-05-16  9:54 ` [PATCH v4 39/56] KVM: arm/arm64: vgic-new: vgic_kvm_device: KVM device ops registration Andre Przywara
2016-05-16  9:54   ` Andre Przywara
2016-05-16  9:54 ` [PATCH v4 40/56] KVM: arm/arm64: vgic-new: vgic_kvm_device: KVM_DEV_ARM_VGIC_GRP_NR_IRQS Andre Przywara
2016-05-16  9:54   ` Andre Przywara
2016-05-16  9:54 ` [PATCH v4 41/56] KVM: arm/arm64: vgic-new: vgic_kvm_device: KVM_DEV_ARM_VGIC_GRP_CTRL Andre Przywara
2016-05-16  9:54   ` Andre Przywara
2016-05-16  9:54 ` [PATCH v4 42/56] KVM: arm/arm64: vgic-new: vgic_kvm_device: implement kvm_vgic_addr Andre Przywara
2016-05-16  9:54   ` Andre Przywara
2016-05-16  9:54 ` [PATCH v4 43/56] KVM: arm/arm64: vgic-new: vgic_kvm_device: KVM_DEV_ARM_VGIC_GRP_ADDR Andre Przywara
2016-05-16  9:54   ` Andre Przywara
2016-05-16  9:54 ` [PATCH v4 44/56] KVM: arm/arm64: vgic-new: vgic_kvm_device: access to VGIC registers Andre Przywara
2016-05-16  9:54   ` Andre Przywara
2016-05-16  9:54 ` [PATCH v4 45/56] KVM: arm/arm64: vgic-new: Export register access interface Andre Przywara
2016-05-16  9:54   ` Andre Przywara
2016-05-16  9:54 ` [PATCH v4 46/56] KVM: arm/arm64: vgic-new: Add userland access to VGIC dist registers Andre Przywara
2016-05-16  9:54   ` Andre Przywara
2016-05-16  9:54 ` [PATCH v4 47/56] KVM: arm/arm64: vgic-new: Add GICH_VMCR accessors Andre Przywara
2016-05-16  9:54   ` Andre Przywara
2016-05-16  9:54 ` [PATCH v4 48/56] KVM: arm/arm64: vgic-new: Add userland GIC CPU interface access Andre Przywara
2016-05-16  9:54   ` Andre Przywara
2016-05-16  9:54 ` [PATCH v4 49/56] KVM: arm/arm64: vgic-new: vgic_init: implement kvm_vgic_hyp_init Andre Przywara
2016-05-16  9:54   ` Andre Przywara
2016-05-17 15:50   ` Julien Grall
2016-05-17 15:50     ` Julien Grall
2016-05-16  9:54 ` [PATCH v4 50/56] KVM: arm/arm64: vgic-new: vgic_init: implement vgic_create Andre Przywara
2016-05-16  9:54   ` Andre Przywara
2016-05-16  9:54 ` [PATCH v4 51/56] KVM: arm/arm64: vgic-new: vgic_init: implement vgic_init Andre Przywara
2016-05-16  9:54   ` Andre Przywara
2016-05-16  9:54 ` [PATCH v4 52/56] KVM: arm/arm64: vgic-new: vgic_init: implement map_resources Andre Przywara
2016-05-16  9:54   ` Andre Przywara
2016-05-16  9:54 ` [PATCH v4 53/56] KVM: arm/arm64: vgic-new: Add vgic_v2/v3_enable Andre Przywara
2016-05-16  9:54   ` Andre Przywara
2016-05-16  9:54 ` [PATCH v4 54/56] KVM: arm/arm64: vgic-new: Wire up irqfd injection Andre Przywara
2016-05-16  9:54   ` Andre Przywara
2016-05-16  9:54 ` [PATCH v4 55/56] KVM: arm/arm64: vgic-new: implement mapped IRQ handling Andre Przywara
2016-05-16  9:54   ` Andre Przywara
2016-05-16  9:54 ` [PATCH v4 56/56] KVM: arm/arm64: vgic-new: enable build Andre Przywara
2016-05-16  9:54   ` Andre Przywara

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