* [U-Boot] [PATCH v2 0/3] rockchip: rk3288: add fastboot support
@ 2016-07-05 2:05 Ziyuan Xu
2016-07-05 2:05 ` [U-Boot] [PATCH v2 1/3] usb: rockchip-phy: implement USB2.0 phy control for Synopsys Ziyuan Xu
` (2 more replies)
0 siblings, 3 replies; 6+ messages in thread
From: Ziyuan Xu @ 2016-07-05 2:05 UTC (permalink / raw)
To: u-boot
This patchset add the fastboot support for rk3288, and I have tested on
firefly-rk3288 board.
Summary of changes in this series:
- Rework the behaviour in otg_phy_init() and otg_phy_off()
- Achieve the regs_phy from DT
- Update comments a little
Xu Ziyuan (3):
usb: rockchip-phy: implement USB2.0 phy control for Synopsys
usb: dwc2-otg: re-define fifo-size for Rockchip SoCs
rockchip: rk3288: add fastboot support
arch/arm/dts/rk3288.dtsi | 1 +
arch/arm/mach-rockchip/board.c | 53 +++++++++++++++++++++++++++++++++
drivers/usb/gadget/dwc2_udc_otg_regs.h | 6 ++++
drivers/usb/phy/Makefile | 1 +
drivers/usb/phy/rockchip_usb_syno_phy.c | 48 +++++++++++++++++++++++++++++
include/configs/rk3288_common.h | 26 ++++++++++++++++
6 files changed, 135 insertions(+)
create mode 100644 drivers/usb/phy/rockchip_usb_syno_phy.c
--
1.9.1
^ permalink raw reply [flat|nested] 6+ messages in thread* [U-Boot] [PATCH v2 1/3] usb: rockchip-phy: implement USB2.0 phy control for Synopsys 2016-07-05 2:05 [U-Boot] [PATCH v2 0/3] rockchip: rk3288: add fastboot support Ziyuan Xu @ 2016-07-05 2:05 ` Ziyuan Xu 2016-07-05 22:01 ` Heiko Stuebner 2016-07-05 2:05 ` [U-Boot] [PATCH v2 2/3] usb: dwc2-otg: re-define fifo-size for Rockchip SoCs Ziyuan Xu 2016-07-05 2:05 ` [U-Boot] [PATCH v2 3/3] rockchip: rk3288: add fastboot support Ziyuan Xu 2 siblings, 1 reply; 6+ messages in thread From: Ziyuan Xu @ 2016-07-05 2:05 UTC (permalink / raw) To: u-boot From: Xu Ziyuan <xzy.xu@rock-chips.com> So far, Rockchip SoCs have two kinds of USB2.0 phy, like Synopsys and Innosilicon. This patch applys dwc2 usb driver framework to implement phy_init and phy_off for Synopsys phy on Rockchip platform. Signed-off-by: Ziyuan Xu <xzy.xu@rock-chips.com> --- Changes in v2: - Rename rk3288_usb_phy.c to rockchip_usb_syno_phy.c - Rework the behaviour in otg_phy_init() and otg_phy_off() drivers/usb/phy/Makefile | 1 + drivers/usb/phy/rockchip_usb_syno_phy.c | 48 +++++++++++++++++++++++++++++++++ 2 files changed, 49 insertions(+) create mode 100644 drivers/usb/phy/rockchip_usb_syno_phy.c diff --git a/drivers/usb/phy/Makefile b/drivers/usb/phy/Makefile index 93d147e..8002a18 100644 --- a/drivers/usb/phy/Makefile +++ b/drivers/usb/phy/Makefile @@ -7,3 +7,4 @@ obj-$(CONFIG_TWL4030_USB) += twl4030.o obj-$(CONFIG_OMAP_USB_PHY) += omap_usb_phy.o +obj-$(CONFIG_ROCKCHIP_USB_SYNO_PHY) += rockchip_usb_syno_phy.o diff --git a/drivers/usb/phy/rockchip_usb_syno_phy.c b/drivers/usb/phy/rockchip_usb_syno_phy.c new file mode 100644 index 0000000..f79cb10 --- /dev/null +++ b/drivers/usb/phy/rockchip_usb_syno_phy.c @@ -0,0 +1,48 @@ +/* + * Copyright 2016 Rockchip Electronics Co., Ltd + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include <common.h> +#include <asm/io.h> + +#include "../gadget/dwc2_udc_otg_priv.h" + +#define GRF_UOC0_CON0 0x320 +#define RESET_WRITE_ENA BIT(28) +#define PORT_RESET BIT(12) +#define PORT_NORMAL (0 << 12) + +#define GRF_UOC0_CON2 0x328 +#define SOFT_CTRL_WRITE_ENA BIT(18) +#define SOFT_CTRL_ENABLE BIT(2) + +#define GRF_UOC0_CON3 0x32c +#define SUSPEND_SETTING 0x2A +#define SUSPEND_WRITE_ENA (0x3f << 16) + + +void otg_phy_init(struct dwc2_udc *dev) +{ + /* disable software control */ + writel(SOFT_CTRL_WRITE_ENA | (0 << 2), + dev->pdata->regs_phy + GRF_UOC0_CON2); + /* reset otg port */ + writel(RESET_WRITE_ENA | PORT_RESET, + dev->pdata->regs_phy + GRF_UOC0_CON0); + mdelay(1); + writel(RESET_WRITE_ENA | PORT_NORMAL, + dev->pdata->regs_phy + GRF_UOC0_CON0); + udelay(1); +} + +void otg_phy_off(struct dwc2_udc *dev) +{ + /* enable software control */ + writel(SOFT_CTRL_WRITE_ENA | SOFT_CTRL_ENABLE, + dev->pdata->regs_phy + GRF_UOC0_CON2); + /* enter suspend */ + writel(SUSPEND_WRITE_ENA | SUSPEND_SETTING, + dev->pdata->regs_phy + GRF_UOC0_CON3); +} -- 1.9.1 ^ permalink raw reply related [flat|nested] 6+ messages in thread
* [U-Boot] [PATCH v2 1/3] usb: rockchip-phy: implement USB2.0 phy control for Synopsys 2016-07-05 2:05 ` [U-Boot] [PATCH v2 1/3] usb: rockchip-phy: implement USB2.0 phy control for Synopsys Ziyuan Xu @ 2016-07-05 22:01 ` Heiko Stuebner 2016-07-06 3:26 ` Ziyuan Xu 0 siblings, 1 reply; 6+ messages in thread From: Heiko Stuebner @ 2016-07-05 22:01 UTC (permalink / raw) To: u-boot Am Dienstag, 5. Juli 2016, 10:05:52 schrieb Ziyuan Xu: > From: Xu Ziyuan <xzy.xu@rock-chips.com> > > So far, Rockchip SoCs have two kinds of USB2.0 phy, like Synopsys and > Innosilicon. This patch applys dwc2 usb driver framework to implement > phy_init and phy_off for Synopsys phy on Rockchip platform. > > Signed-off-by: Ziyuan Xu <xzy.xu@rock-chips.com> > > --- > > Changes in v2: > - Rename rk3288_usb_phy.c to rockchip_usb_syno_phy.c > - Rework the behaviour in otg_phy_init() and otg_phy_off() > > drivers/usb/phy/Makefile | 1 + > drivers/usb/phy/rockchip_usb_syno_phy.c | 48 > +++++++++++++++++++++++++++++++++ 2 files changed, 49 insertions(+) > create mode 100644 drivers/usb/phy/rockchip_usb_syno_phy.c > > diff --git a/drivers/usb/phy/Makefile b/drivers/usb/phy/Makefile > index 93d147e..8002a18 100644 > --- a/drivers/usb/phy/Makefile > +++ b/drivers/usb/phy/Makefile > @@ -7,3 +7,4 @@ > > obj-$(CONFIG_TWL4030_USB) += twl4030.o > obj-$(CONFIG_OMAP_USB_PHY) += omap_usb_phy.o > +obj-$(CONFIG_ROCKCHIP_USB_SYNO_PHY) += rockchip_usb_syno_phy.o > diff --git a/drivers/usb/phy/rockchip_usb_syno_phy.c > b/drivers/usb/phy/rockchip_usb_syno_phy.c new file mode 100644 > index 0000000..f79cb10 > --- /dev/null > +++ b/drivers/usb/phy/rockchip_usb_syno_phy.c > @@ -0,0 +1,48 @@ > +/* > + * Copyright 2016 Rockchip Electronics Co., Ltd > + * > + * SPDX-License-Identifier: GPL-2.0+ > + */ > + > +#include <common.h> > +#include <asm/io.h> > + > +#include "../gadget/dwc2_udc_otg_priv.h" > + > +#define GRF_UOC0_CON0 0x320 That isn't terrible future proof ... the GRF offsets are different for on every Rockchip soc using that phy. We do have the phy nodes in the devicetree, so shouldn't all that be readable from there somehow? Heiko ^ permalink raw reply [flat|nested] 6+ messages in thread
* [U-Boot] [PATCH v2 1/3] usb: rockchip-phy: implement USB2.0 phy control for Synopsys 2016-07-05 22:01 ` Heiko Stuebner @ 2016-07-06 3:26 ` Ziyuan Xu 0 siblings, 0 replies; 6+ messages in thread From: Ziyuan Xu @ 2016-07-06 3:26 UTC (permalink / raw) To: u-boot On 2016?07?06? 06:01, Heiko Stuebner wrote: > Am Dienstag, 5. Juli 2016, 10:05:52 schrieb Ziyuan Xu: >> From: Xu Ziyuan <xzy.xu@rock-chips.com> >> >> So far, Rockchip SoCs have two kinds of USB2.0 phy, like Synopsys and >> Innosilicon. This patch applys dwc2 usb driver framework to implement >> phy_init and phy_off for Synopsys phy on Rockchip platform. >> >> Signed-off-by: Ziyuan Xu <xzy.xu@rock-chips.com> >> >> --- >> >> Changes in v2: >> - Rename rk3288_usb_phy.c to rockchip_usb_syno_phy.c >> - Rework the behaviour in otg_phy_init() and otg_phy_off() >> >> drivers/usb/phy/Makefile | 1 + >> drivers/usb/phy/rockchip_usb_syno_phy.c | 48 >> +++++++++++++++++++++++++++++++++ 2 files changed, 49 insertions(+) >> create mode 100644 drivers/usb/phy/rockchip_usb_syno_phy.c >> >> diff --git a/drivers/usb/phy/Makefile b/drivers/usb/phy/Makefile >> index 93d147e..8002a18 100644 >> --- a/drivers/usb/phy/Makefile >> +++ b/drivers/usb/phy/Makefile >> @@ -7,3 +7,4 @@ >> >> obj-$(CONFIG_TWL4030_USB) += twl4030.o >> obj-$(CONFIG_OMAP_USB_PHY) += omap_usb_phy.o >> +obj-$(CONFIG_ROCKCHIP_USB_SYNO_PHY) += rockchip_usb_syno_phy.o >> diff --git a/drivers/usb/phy/rockchip_usb_syno_phy.c >> b/drivers/usb/phy/rockchip_usb_syno_phy.c new file mode 100644 >> index 0000000..f79cb10 >> --- /dev/null >> +++ b/drivers/usb/phy/rockchip_usb_syno_phy.c >> @@ -0,0 +1,48 @@ >> +/* >> + * Copyright 2016 Rockchip Electronics Co., Ltd >> + * >> + * SPDX-License-Identifier: GPL-2.0+ >> + */ >> + >> +#include <common.h> >> +#include <asm/io.h> >> + >> +#include "../gadget/dwc2_udc_otg_priv.h" >> + >> +#define GRF_UOC0_CON0 0x320 > That isn't terrible future proof ... the GRF offsets are different for on > every Rockchip soc using that phy. > > We do have the phy nodes in the devicetree, so shouldn't all that be > readable from there somehow? Yup, it makes sense to me. dwc2 usb driver didn't apply the devicetree model in u-boot, it's too prolix to get phy_offset from DT. hmm, I have fixed it, and pass it via regs_phy field. Thanks! > > Heiko > > > > ^ permalink raw reply [flat|nested] 6+ messages in thread
* [U-Boot] [PATCH v2 2/3] usb: dwc2-otg: re-define fifo-size for Rockchip SoCs 2016-07-05 2:05 [U-Boot] [PATCH v2 0/3] rockchip: rk3288: add fastboot support Ziyuan Xu 2016-07-05 2:05 ` [U-Boot] [PATCH v2 1/3] usb: rockchip-phy: implement USB2.0 phy control for Synopsys Ziyuan Xu @ 2016-07-05 2:05 ` Ziyuan Xu 2016-07-05 2:05 ` [U-Boot] [PATCH v2 3/3] rockchip: rk3288: add fastboot support Ziyuan Xu 2 siblings, 0 replies; 6+ messages in thread From: Ziyuan Xu @ 2016-07-05 2:05 UTC (permalink / raw) To: u-boot From: Xu Ziyuan <xzy.xu@rock-chips.com> The total FIFO size of dwc2 on Rockchip SoCs is shorter than the existen, so re-define them to fit Rockchip SoCs. Signed-off-by: Ziyuan Xu <xzy.xu@rock-chips.com> --- Changes in v2: - Update detailed commit message - Modify the macro's values drivers/usb/gadget/dwc2_udc_otg_regs.h | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/drivers/usb/gadget/dwc2_udc_otg_regs.h b/drivers/usb/gadget/dwc2_udc_otg_regs.h index 78ec90e..6004a4b 100644 --- a/drivers/usb/gadget/dwc2_udc_otg_regs.h +++ b/drivers/usb/gadget/dwc2_udc_otg_regs.h @@ -130,9 +130,15 @@ struct dwc2_usbotg_reg { #define HIGH_SPEED_CONTROL_PKT_SIZE 64 #define HIGH_SPEED_BULK_PKT_SIZE 512 +#ifdef CONFIG_ARCH_ROCKCHIP +#define RX_FIFO_SIZE (512*4) +#define NPTX_FIFO_SIZE (16*4) +#define PTX_FIFO_SIZE (128*4) +#else #define RX_FIFO_SIZE (1024*4) #define NPTX_FIFO_SIZE (1024*4) #define PTX_FIFO_SIZE (1536*1) +#endif #define DEPCTL_TXFNUM_0 (0x0<<22) #define DEPCTL_TXFNUM_1 (0x1<<22) -- 1.9.1 ^ permalink raw reply related [flat|nested] 6+ messages in thread
* [U-Boot] [PATCH v2 3/3] rockchip: rk3288: add fastboot support 2016-07-05 2:05 [U-Boot] [PATCH v2 0/3] rockchip: rk3288: add fastboot support Ziyuan Xu 2016-07-05 2:05 ` [U-Boot] [PATCH v2 1/3] usb: rockchip-phy: implement USB2.0 phy control for Synopsys Ziyuan Xu 2016-07-05 2:05 ` [U-Boot] [PATCH v2 2/3] usb: dwc2-otg: re-define fifo-size for Rockchip SoCs Ziyuan Xu @ 2016-07-05 2:05 ` Ziyuan Xu 2 siblings, 0 replies; 6+ messages in thread From: Ziyuan Xu @ 2016-07-05 2:05 UTC (permalink / raw) To: u-boot From: Xu Ziyuan <xzy.xu@rock-chips.com> Enable fastboot feature on rk3288. This path doesn't support the fastboot flash function command entirely. We will hit "cannot find partition" assertion without specified partition environment. Define gpt partition layout in specified board such as firefly-rk3288, then enjoy it! Signed-off-by: Ziyuan Xu <xzy.xu@rock-chips.com> --- Changes in v2: - Achieve the regs_phy from DT - Update comments a little arch/arm/dts/rk3288.dtsi | 1 + arch/arm/mach-rockchip/board.c | 53 +++++++++++++++++++++++++++++++++++++++++ include/configs/rk3288_common.h | 26 ++++++++++++++++++++ 3 files changed, 80 insertions(+) diff --git a/arch/arm/dts/rk3288.dtsi b/arch/arm/dts/rk3288.dtsi index 3dab0fc..bcf051a 100644 --- a/arch/arm/dts/rk3288.dtsi +++ b/arch/arm/dts/rk3288.dtsi @@ -454,6 +454,7 @@ interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>; clocks = <&cru HCLK_OTG0>; clock-names = "otg"; + dr_mode = "otg"; phys = <&usbphy0>; phy-names = "usb2-phy"; status = "disabled"; diff --git a/arch/arm/mach-rockchip/board.c b/arch/arm/mach-rockchip/board.c index 816540e..4e281b2 100644 --- a/arch/arm/mach-rockchip/board.c +++ b/arch/arm/mach-rockchip/board.c @@ -52,6 +52,59 @@ void lowlevel_init(void) { } +#if defined(CONFIG_USB_GADGET) && defined(CONFIG_USB_GADGET_DWC2_OTG) +#include <usb.h> +#include <usb/dwc2_udc.h> + +static struct dwc2_plat_otg_data rk3288_otg_data; + +int board_usb_init(int index, enum usb_init_type init) +{ + int offset; + const char *mode; + bool matched = false; + void *blob = gd->fdt_blob; + u32 base; + + /* find the usb_otg node */ + offset = fdt_node_offset_by_compatible(blob, -1, + "rockchip,rk3288-usb"); + + while (offset != -FDT_ERR_NOTFOUND) { + mode = fdt_getprop(blob, offset, "dr_mode", NULL); + if (mode && strcmp(mode, "otg") == 0) { + matched = true; + break; + } + + offset = fdt_node_offset_by_compatible(blob, offset, + "rockchip,rk3288-usb"); + } + if (!matched) { + debug("Not found usb_otg device\n"); + return -ENODEV; + } + rk3288_otg_data.regs_otg = fdtdec_get_addr(blob, offset, "reg"); + + /* find the grf node */ + offset = fdt_node_offset_by_compatible(blob, -1, + "rockchip,rk3288-grf"); + + if (offset == -FDT_ERR_NOTFOUND) { + debug("Not found grf device\n"); + return -ENODEV; + } + rk3288_otg_data.regs_phy = fdtdec_get_addr(blob, offset, "reg"); + + return dwc2_udc_probe(&rk3288_otg_data); +} + +int board_usb_cleanup(int index, enum usb_init_type init) +{ + return 0; +} +#endif + static int do_clock(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) { diff --git a/include/configs/rk3288_common.h b/include/configs/rk3288_common.h index 9d50d83..94fd13f 100644 --- a/include/configs/rk3288_common.h +++ b/include/configs/rk3288_common.h @@ -80,6 +80,32 @@ #define CONFIG_SPI #define CONFIG_SF_DEFAULT_SPEED 20000000 +/* usb otg */ +#define CONFIG_USB_GADGET +#define CONFIG_USB_GADGET_DUALSPEED +#define CONFIG_USB_GADGET_DWC2_OTG +#define CONFIG_ROCKCHIP_USB_SYNO_PHY +#define CONFIG_USB_GADGET_VBUS_DRAW 0 + +/* fastboot */ +#define CONFIG_CMD_FASTBOOT +#define CONFIG_USB_FUNCTION_FASTBOOT +#define CONFIG_FASTBOOT_FLASH +#define CONFIG_FASTBOOT_FLASH_MMC_DEV 1 /* eMMC */ +/* stroe safely fastboot buffer data to the middle of bank */ +#define CONFIG_FASTBOOT_BUF_ADDR (CONFIG_SYS_SDRAM_BASE \ + + SDRAM_BANK_SIZE / 2) +#define CONFIG_FASTBOOT_BUF_SIZE 0x08000000 + +#define CONFIG_USB_GADGET_DOWNLOAD +#define CONFIG_G_DNL_MANUFACTURER "Rockchip" +#define CONFIG_G_DNL_VENDOR_NUM 0x2207 +#define CONFIG_G_DNL_PRODUCT_NUM 0x320a + +/* Enable gpt partition table */ +#define CONFIG_CMD_GPT +#define CONFIG_EFI_PARTITION + #ifndef CONFIG_SPL_BUILD #include <config_distro_defaults.h> -- 1.9.1 ^ permalink raw reply related [flat|nested] 6+ messages in thread
end of thread, other threads:[~2016-07-06 3:26 UTC | newest] Thread overview: 6+ messages (download: mbox.gz follow: Atom feed -- links below jump to the message on this page -- 2016-07-05 2:05 [U-Boot] [PATCH v2 0/3] rockchip: rk3288: add fastboot support Ziyuan Xu 2016-07-05 2:05 ` [U-Boot] [PATCH v2 1/3] usb: rockchip-phy: implement USB2.0 phy control for Synopsys Ziyuan Xu 2016-07-05 22:01 ` Heiko Stuebner 2016-07-06 3:26 ` Ziyuan Xu 2016-07-05 2:05 ` [U-Boot] [PATCH v2 2/3] usb: dwc2-otg: re-define fifo-size for Rockchip SoCs Ziyuan Xu 2016-07-05 2:05 ` [U-Boot] [PATCH v2 3/3] rockchip: rk3288: add fastboot support Ziyuan Xu
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