From: Marc Zyngier <marc.zyngier@arm.com>
To: Geert Uytterhoeven <geert@linux-m68k.org>,
Catalin Marinas <catalin.marinas@arm.com>,
Will Deacon <will.deacon@arm.com>
Cc: "linux-kernel@vger.kernel.org" <linux-kernel@vger.kernel.org>,
"linux-arm-kernel@lists.infradead.org"
<linux-arm-kernel@lists.infradead.org>,
"devicetree@vger.kernel.org" <devicetree@vger.kernel.org>,
"open list:ARM/Rockchip SoC..."
<linux-rockchip@lists.infradead.org>,
Heiko Stuebner <heiko@sntech.de>,
cf@rock-chips.com, huangtao@rock-chips.com,
Xu Jianqun <jay.xu@rock-chips.com>,
Caesar Wang <wxt@rock-chips.com>,
David Wu <david.wu@rock-chips.com>,
Brian Norris <briannorris@chromium.org>,
Mark Rutland <mark.rutland@arm.com>,
Rob Herring <robh+dt@kernel.org>,
Linux-Renesas <linux-renesas-soc@vger.kernel.org>
Subject: Re: [PATCH v2] drivers/perf: arm-pmu: Handle per-interrupt affinity mask
Date: Tue, 19 Jul 2016 14:46:40 +0100 [thread overview]
Message-ID: <578E2F40.1000309@arm.com> (raw)
In-Reply-To: <CAMuHMdXU6C=jFD16Jj3NFNawiY0YEpQDZSbL+T4bLgUOG3nTUQ@mail.gmail.com>
Hi Geert,
On 19/07/16 14:25, Geert Uytterhoeven wrote:
> Hi Marc, Catalin, Will,
>
> On Wed, Jul 6, 2016 at 4:33 PM, Marc Zyngier <marc.zyngier@arm.com> wrote:
>> On a big-little system, PMUs can be wired to CPUs using per CPU
>> interrups (PPI). In this case, it is important to make sure that
>> the enable/disable do happen on the right set of CPUs.
>>
>> So instead of relying on the interrupt-affinity property, we can
>> use the actual percpu affinity that DT exposes as part of the
>> interrupt specifier. The DT binding is also updated to reflect
>> the fact that the interrupt-affinity property shouldn't be used
>> in that case.
>>
>> Signed-off-by: Marc Zyngier <marc.zyngier@arm.com>
>> ---
>> * From v1:
>> - propagate the error if irq_get_percpu_devid_partition fails
>
> This patch, which is commit 19a469a58720ea96 in arm64/for-next/core, broke
> the PMU on r8a7740/armadillo800eva:
>
> -hw perfevents: enabled with armv7_cortex_a9 PMU driver, 7
> counters available
> +hw perfevents: /pmu: failed to probe PMU!
> +hw perfevents: /pmu: failed to register PMU devices!
> +armv7-pmu: probe of pmu failed with error -22
>
> This is a single-core Cortex A9.
>
>> Documentation/devicetree/bindings/arm/pmu.txt | 4 +++-
>> drivers/perf/arm_pmu.c | 27 ++++++++++++++++++++++-----
>> 2 files changed, 25 insertions(+), 6 deletions(-)
>>
>> diff --git a/Documentation/devicetree/bindings/arm/pmu.txt b/Documentation/devicetree/bindings/arm/pmu.txt
>> index 74d5417..61c8b46 100644
>> --- a/Documentation/devicetree/bindings/arm/pmu.txt
>> +++ b/Documentation/devicetree/bindings/arm/pmu.txt
>> @@ -39,7 +39,9 @@ Optional properties:
>> When using a PPI, specifies a list of phandles to CPU
>> nodes corresponding to the set of CPUs which have
>> a PMU of this type signalling the PPI listed in the
>> - interrupts property.
>> + interrupts property, unless this is already specified
>> + by the PPI interrupt specifier itself (in which case
>> + the interrupt-affinity property shouldn't be present).
>>
>> This property should be present when there is more than
>> a single SPI.
>
> On a single core, there's only a single SPI, hence there's no need for an
> "interrupt-affinity" property.
>
>> diff --git a/drivers/perf/arm_pmu.c b/drivers/perf/arm_pmu.c
>> index 140436a..8e4d7f5 100644
>> --- a/drivers/perf/arm_pmu.c
>> +++ b/drivers/perf/arm_pmu.c
>> @@ -961,9 +964,23 @@ static int of_pmu_irq_cfg(struct arm_pmu *pmu)
>> i++;
>> } while (1);
>>
>> - /* If we didn't manage to parse anything, claim to support all CPUs */
>> - if (cpumask_weight(&pmu->supported_cpus) == 0)
>> - cpumask_setall(&pmu->supported_cpus);
>> + /* If we didn't manage to parse anything, try the interrupt affinity */
>> + if (cpumask_weight(&pmu->supported_cpus) == 0) {
>> + if (!using_spi) {
>
> However, using_spi is never set to true in the absence of that property,
> causing the wrong branch to be taken...
>
>> + /* If using PPIs, check the affinity of the partition */
>> + int ret, irq;
>> +
>> + irq = platform_get_irq(pdev, 0);
>> + ret = irq_get_percpu_devid_partition(irq, &pmu->supported_cpus);
>
> ... and ret to become -22 here.
Thanks for the thorough analysis. Could you please give the following
patchlet a go:
diff --git a/drivers/perf/arm_pmu.c b/drivers/perf/arm_pmu.c
index 2513365..9275e08 100644
--- a/drivers/perf/arm_pmu.c
+++ b/drivers/perf/arm_pmu.c
@@ -958,11 +958,12 @@ static int of_pmu_irq_cfg(struct arm_pmu *pmu)
/* If we didn't manage to parse anything, try the interrupt affinity */
if (cpumask_weight(&pmu->supported_cpus) == 0) {
- if (!using_spi) {
+ int irq = platform_get_irq(pdev, 0);
+
+ if (irq_is_percpu(irq)) {
/* If using PPIs, check the affinity of the partition */
- int ret, irq;
+ int ret;
- irq = platform_get_irq(pdev, 0);
ret = irq_get_percpu_devid_partition(irq, &pmu->supported_cpus);
if (ret) {
kfree(irqs);
and let me know if that helps?
Thanks,
M.
--
Jazz is not dead. It just smells funny...
WARNING: multiple messages have this Message-ID (diff)
From: marc.zyngier@arm.com (Marc Zyngier)
To: linux-arm-kernel@lists.infradead.org
Subject: [PATCH v2] drivers/perf: arm-pmu: Handle per-interrupt affinity mask
Date: Tue, 19 Jul 2016 14:46:40 +0100 [thread overview]
Message-ID: <578E2F40.1000309@arm.com> (raw)
In-Reply-To: <CAMuHMdXU6C=jFD16Jj3NFNawiY0YEpQDZSbL+T4bLgUOG3nTUQ@mail.gmail.com>
Hi Geert,
On 19/07/16 14:25, Geert Uytterhoeven wrote:
> Hi Marc, Catalin, Will,
>
> On Wed, Jul 6, 2016 at 4:33 PM, Marc Zyngier <marc.zyngier@arm.com> wrote:
>> On a big-little system, PMUs can be wired to CPUs using per CPU
>> interrups (PPI). In this case, it is important to make sure that
>> the enable/disable do happen on the right set of CPUs.
>>
>> So instead of relying on the interrupt-affinity property, we can
>> use the actual percpu affinity that DT exposes as part of the
>> interrupt specifier. The DT binding is also updated to reflect
>> the fact that the interrupt-affinity property shouldn't be used
>> in that case.
>>
>> Signed-off-by: Marc Zyngier <marc.zyngier@arm.com>
>> ---
>> * From v1:
>> - propagate the error if irq_get_percpu_devid_partition fails
>
> This patch, which is commit 19a469a58720ea96 in arm64/for-next/core, broke
> the PMU on r8a7740/armadillo800eva:
>
> -hw perfevents: enabled with armv7_cortex_a9 PMU driver, 7
> counters available
> +hw perfevents: /pmu: failed to probe PMU!
> +hw perfevents: /pmu: failed to register PMU devices!
> +armv7-pmu: probe of pmu failed with error -22
>
> This is a single-core Cortex A9.
>
>> Documentation/devicetree/bindings/arm/pmu.txt | 4 +++-
>> drivers/perf/arm_pmu.c | 27 ++++++++++++++++++++++-----
>> 2 files changed, 25 insertions(+), 6 deletions(-)
>>
>> diff --git a/Documentation/devicetree/bindings/arm/pmu.txt b/Documentation/devicetree/bindings/arm/pmu.txt
>> index 74d5417..61c8b46 100644
>> --- a/Documentation/devicetree/bindings/arm/pmu.txt
>> +++ b/Documentation/devicetree/bindings/arm/pmu.txt
>> @@ -39,7 +39,9 @@ Optional properties:
>> When using a PPI, specifies a list of phandles to CPU
>> nodes corresponding to the set of CPUs which have
>> a PMU of this type signalling the PPI listed in the
>> - interrupts property.
>> + interrupts property, unless this is already specified
>> + by the PPI interrupt specifier itself (in which case
>> + the interrupt-affinity property shouldn't be present).
>>
>> This property should be present when there is more than
>> a single SPI.
>
> On a single core, there's only a single SPI, hence there's no need for an
> "interrupt-affinity" property.
>
>> diff --git a/drivers/perf/arm_pmu.c b/drivers/perf/arm_pmu.c
>> index 140436a..8e4d7f5 100644
>> --- a/drivers/perf/arm_pmu.c
>> +++ b/drivers/perf/arm_pmu.c
>> @@ -961,9 +964,23 @@ static int of_pmu_irq_cfg(struct arm_pmu *pmu)
>> i++;
>> } while (1);
>>
>> - /* If we didn't manage to parse anything, claim to support all CPUs */
>> - if (cpumask_weight(&pmu->supported_cpus) == 0)
>> - cpumask_setall(&pmu->supported_cpus);
>> + /* If we didn't manage to parse anything, try the interrupt affinity */
>> + if (cpumask_weight(&pmu->supported_cpus) == 0) {
>> + if (!using_spi) {
>
> However, using_spi is never set to true in the absence of that property,
> causing the wrong branch to be taken...
>
>> + /* If using PPIs, check the affinity of the partition */
>> + int ret, irq;
>> +
>> + irq = platform_get_irq(pdev, 0);
>> + ret = irq_get_percpu_devid_partition(irq, &pmu->supported_cpus);
>
> ... and ret to become -22 here.
Thanks for the thorough analysis. Could you please give the following
patchlet a go:
diff --git a/drivers/perf/arm_pmu.c b/drivers/perf/arm_pmu.c
index 2513365..9275e08 100644
--- a/drivers/perf/arm_pmu.c
+++ b/drivers/perf/arm_pmu.c
@@ -958,11 +958,12 @@ static int of_pmu_irq_cfg(struct arm_pmu *pmu)
/* If we didn't manage to parse anything, try the interrupt affinity */
if (cpumask_weight(&pmu->supported_cpus) == 0) {
- if (!using_spi) {
+ int irq = platform_get_irq(pdev, 0);
+
+ if (irq_is_percpu(irq)) {
/* If using PPIs, check the affinity of the partition */
- int ret, irq;
+ int ret;
- irq = platform_get_irq(pdev, 0);
ret = irq_get_percpu_devid_partition(irq, &pmu->supported_cpus);
if (ret) {
kfree(irqs);
and let me know if that helps?
Thanks,
M.
--
Jazz is not dead. It just smells funny...
next prev parent reply other threads:[~2016-07-19 13:46 UTC|newest]
Thread overview: 17+ messages / expand[flat|nested] mbox.gz Atom feed top
2016-07-06 14:33 [PATCH v2] drivers/perf: arm-pmu: Handle per-interrupt affinity mask Marc Zyngier
2016-07-06 14:33 ` Marc Zyngier
2016-07-06 14:33 ` Marc Zyngier
2016-07-06 16:05 ` Will Deacon
2016-07-06 16:05 ` Will Deacon
2016-07-11 14:37 ` Rob Herring
2016-07-11 14:37 ` Rob Herring
2016-07-11 14:47 ` Will Deacon
2016-07-11 14:47 ` Will Deacon
2016-07-11 14:47 ` Will Deacon
[not found] ` <1467815627-4061-1-git-send-email-marc.zyngier-5wv7dgnIgG8@public.gmane.org>
2016-07-19 13:25 ` Geert Uytterhoeven
2016-07-19 13:25 ` Geert Uytterhoeven
2016-07-19 13:25 ` Geert Uytterhoeven
2016-07-19 13:46 ` Marc Zyngier [this message]
2016-07-19 13:46 ` Marc Zyngier
2016-07-19 14:24 ` Geert Uytterhoeven
2016-07-19 14:24 ` Geert Uytterhoeven
Reply instructions:
You may reply publicly to this message via plain-text email
using any one of the following methods:
* Save the following mbox file, import it into your mail client,
and reply-to-all from there: mbox
Avoid top-posting and favor interleaved quoting:
https://en.wikipedia.org/wiki/Posting_style#Interleaved_style
* Reply using the --to, --cc, and --in-reply-to
switches of git-send-email(1):
git send-email \
--in-reply-to=578E2F40.1000309@arm.com \
--to=marc.zyngier@arm.com \
--cc=briannorris@chromium.org \
--cc=catalin.marinas@arm.com \
--cc=cf@rock-chips.com \
--cc=david.wu@rock-chips.com \
--cc=devicetree@vger.kernel.org \
--cc=geert@linux-m68k.org \
--cc=heiko@sntech.de \
--cc=huangtao@rock-chips.com \
--cc=jay.xu@rock-chips.com \
--cc=linux-arm-kernel@lists.infradead.org \
--cc=linux-kernel@vger.kernel.org \
--cc=linux-renesas-soc@vger.kernel.org \
--cc=linux-rockchip@lists.infradead.org \
--cc=mark.rutland@arm.com \
--cc=robh+dt@kernel.org \
--cc=will.deacon@arm.com \
--cc=wxt@rock-chips.com \
/path/to/YOUR_REPLY
https://kernel.org/pub/software/scm/git/docs/git-send-email.html
* If your mail client supports setting the In-Reply-To header
via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line
before the message body.
This is an external index of several public inboxes,
see mirroring instructions on how to clone and mirror
all data and code used by this external index.