From: Ziyuan Xu <xzy.xu@rock-chips.com>
To: u-boot@lists.denx.de
Subject: [U-Boot] [PATCH] mmc: dw_mmc: fix the wrong Mask bit boundary for fifo_count bit
Date: Thu, 28 Jul 2016 13:54:42 +0800 [thread overview]
Message-ID: <57999E22.6030605@rock-chips.com> (raw)
In-Reply-To: <1469683584-21695-1-git-send-email-jh80.chung@samsung.com>
Hi Jaehoon,
On 2016?07?28? 13:26, Jaehoon Chung wrote:
> According to DesignWare TRM, FIFO_COUNT is bit[29:17].
> If get the correct fifo_count value, it has to use the FIFO_MASK
> as 0x1FFF, not 0x1FF.
Ah, I have no doubt the fifo_count defined. The fifo depth of Rockchip
SoCs is 256, the former work sane coincidentally.:-)
Thanks for fix.
Reviewed-by: Ziyuan Xu <xzy.xu@rock-chips.com>
>
> Signed-off-by: Jaehoon Chung <jh80.chung@samsung.com>
> ---
> include/dwmmc.h | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/include/dwmmc.h b/include/dwmmc.h
> index 6aebe96..eb03f7f 100644
> --- a/include/dwmmc.h
> +++ b/include/dwmmc.h
> @@ -105,7 +105,7 @@
>
> /* Status Register */
> #define DWMCI_BUSY (1 << 9)
> -#define DWMCI_FIFO_MASK 0x1ff
> +#define DWMCI_FIFO_MASK 0x1fff
> #define DWMCI_FIFO_SHIFT 17
>
> /* FIFOTH Register */
next prev parent reply other threads:[~2016-07-28 5:54 UTC|newest]
Thread overview: 3+ messages / expand[flat|nested] mbox.gz Atom feed top
2016-07-28 5:26 [U-Boot] [PATCH] mmc: dw_mmc: fix the wrong Mask bit boundary for fifo_count bit Jaehoon Chung
2016-07-28 5:54 ` Ziyuan Xu [this message]
2016-08-05 2:27 ` [U-Boot] " Jaehoon Chung
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