* [PATCH v3 0/2] arm64: dts: rockchip: Support PMU for rk3399 SoCs @ 2016-09-05 18:17 ` Caesar Wang 0 siblings, 0 replies; 16+ messages in thread From: Caesar Wang @ 2016-09-05 18:17 UTC (permalink / raw) To: Heiko Stuebner Cc: linux-rockchip-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r, Douglas Anderson, sonnyrao-F7+t8E8rja9g9hUCZPvPmw, linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r, Caesar Wang, devicetree-u79uwXL29TY76Z2rM5mHXA, David Wu, Elaine Zhang, Brian Norris, linux-kernel-u79uwXL29TY76Z2rM5mHXA, Huang Tao, Shawn Lin, Will Deacon, Jianqun Xu, Mark Rutland, Rob Herring, Catalin Marinas, Xing Zheng Hello Heiko, ARM guys When Jay first submitted the rk3399.dtsi upstream <https://patchwork.kernel.org/patch/8885821/> he had the PMU node in there, but then took it out because the upstream binding wasn't done yet. It looks as if the upstream stuff has landed, since in linux/master I see: 287e9357abcc DT/arm,gic-v3: Documment PPI partition support e3825ba1af3a irqchip/gic-v3: Add support for partitioned PPIs 9e2c986cb460 irqchip: Add per-cpu interrupt partitioning library 222df54fd8b7 genirq: Allow the affinity of a percpu interrupt to be set/retrieved 651e8b54abde irqdomain: Allow domain matching on irq_fwspec This series patches add to support the rk3399 SoCs PMU. I pick up the https://patchwork.kernel.org/patch/9209369/. As do some tests with ChromeOs for my rk3399 board. Tested with next-20160905 kernel on rk3399 board. https://github.com/Caesar-github/rockchip/tree/rk3399/pmu-upstream localhost / # perf list List of pre-defined events (to be used in -e): cpu-cycles OR cycles [Hardware event] instructions [Hardware event] cache-references [Hardware event] cache-misses [Hardware event] branch-instructions OR branches [Hardware event] branch-misses [Hardware event] bus-cycles [Hardware event] ... perf stat --cpu 0/1/2/3..... to minitor e.g. cpu0; localhost / # perf stat --cpu 0 Performance counter stats for 'CPU(s) 0': 3374.917571 task-clock (msec) # 1.001 CPUs utilized [100.00%] 20 context-switches # 0.006 K/sec [100.00%] 2 cpu-migrations # 0.001 K/sec [100.00%] 55 page-faults # 0.016 K/sec 7151843 cycles # 0.002 GHz [100.00%] <not supported> stalled-cycles-frontend <not supported> stalled-cycles-backend 4272536 instructions # 0.60 insns per cycle [100.00%] 568406 branches # 0.168 M/sec [100.00%] 65652 branch-misses # 11.55% of all branches Also, 'perf top' to monitor the PMU interrupts from cpus -Caesar Changes in v3: - update with the lastest next kernel(20160905). - add Mark's ACK for PATCH[1/2]. - updated on next kernel(20160905). - add the Mark's ACK for PATCH[2/2]. Changes in v2: - AS Mark comments on https://patchwork.kernel.org/patch/9209369/ remove the interrupt-affinity property, we need depend on Marc' perf code on https://patchwork.kernel.org/patch/9209369/. Caesar Wang (2): arm64: dts: rockchip: change all interrupts cells for 4 on rk3399 SoCs arm64: dts: rockchip: support the pmu node for rk3399 arch/arm64/boot/dts/rockchip/rk3399.dtsi | 122 ++++++++++++++++++------------- 1 file changed, 71 insertions(+), 51 deletions(-) -- 1.9.1 -- To unsubscribe from this list: send the line "unsubscribe devicetree" in the body of a message to majordomo-u79uwXL29TY76Z2rM5mHXA@public.gmane.org More majordomo info at http://vger.kernel.org/majordomo-info.html ^ permalink raw reply [flat|nested] 16+ messages in thread
* [PATCH v3 0/2] arm64: dts: rockchip: Support PMU for rk3399 SoCs @ 2016-09-05 18:17 ` Caesar Wang 0 siblings, 0 replies; 16+ messages in thread From: Caesar Wang @ 2016-09-05 18:17 UTC (permalink / raw) To: Heiko Stuebner Cc: linux-rockchip, Douglas Anderson, sonnyrao, linux-arm-kernel, Caesar Wang, devicetree, David Wu, Elaine Zhang, Brian Norris, linux-kernel, Huang Tao, Shawn Lin, Will Deacon, Jianqun Xu, Mark Rutland, Rob Herring, Catalin Marinas, Xing Zheng Hello Heiko, ARM guys When Jay first submitted the rk3399.dtsi upstream <https://patchwork.kernel.org/patch/8885821/> he had the PMU node in there, but then took it out because the upstream binding wasn't done yet. It looks as if the upstream stuff has landed, since in linux/master I see: 287e9357abcc DT/arm,gic-v3: Documment PPI partition support e3825ba1af3a irqchip/gic-v3: Add support for partitioned PPIs 9e2c986cb460 irqchip: Add per-cpu interrupt partitioning library 222df54fd8b7 genirq: Allow the affinity of a percpu interrupt to be set/retrieved 651e8b54abde irqdomain: Allow domain matching on irq_fwspec This series patches add to support the rk3399 SoCs PMU. I pick up the https://patchwork.kernel.org/patch/9209369/. As do some tests with ChromeOs for my rk3399 board. Tested with next-20160905 kernel on rk3399 board. https://github.com/Caesar-github/rockchip/tree/rk3399/pmu-upstream localhost / # perf list List of pre-defined events (to be used in -e): cpu-cycles OR cycles [Hardware event] instructions [Hardware event] cache-references [Hardware event] cache-misses [Hardware event] branch-instructions OR branches [Hardware event] branch-misses [Hardware event] bus-cycles [Hardware event] ... perf stat --cpu 0/1/2/3..... to minitor e.g. cpu0; localhost / # perf stat --cpu 0 Performance counter stats for 'CPU(s) 0': 3374.917571 task-clock (msec) # 1.001 CPUs utilized [100.00%] 20 context-switches # 0.006 K/sec [100.00%] 2 cpu-migrations # 0.001 K/sec [100.00%] 55 page-faults # 0.016 K/sec 7151843 cycles # 0.002 GHz [100.00%] <not supported> stalled-cycles-frontend <not supported> stalled-cycles-backend 4272536 instructions # 0.60 insns per cycle [100.00%] 568406 branches # 0.168 M/sec [100.00%] 65652 branch-misses # 11.55% of all branches Also, 'perf top' to monitor the PMU interrupts from cpus -Caesar Changes in v3: - update with the lastest next kernel(20160905). - add Mark's ACK for PATCH[1/2]. - updated on next kernel(20160905). - add the Mark's ACK for PATCH[2/2]. Changes in v2: - AS Mark comments on https://patchwork.kernel.org/patch/9209369/ remove the interrupt-affinity property, we need depend on Marc' perf code on https://patchwork.kernel.org/patch/9209369/. Caesar Wang (2): arm64: dts: rockchip: change all interrupts cells for 4 on rk3399 SoCs arm64: dts: rockchip: support the pmu node for rk3399 arch/arm64/boot/dts/rockchip/rk3399.dtsi | 122 ++++++++++++++++++------------- 1 file changed, 71 insertions(+), 51 deletions(-) -- 1.9.1 ^ permalink raw reply [flat|nested] 16+ messages in thread
* [PATCH v3 0/2] arm64: dts: rockchip: Support PMU for rk3399 SoCs @ 2016-09-05 18:17 ` Caesar Wang 0 siblings, 0 replies; 16+ messages in thread From: Caesar Wang @ 2016-09-05 18:17 UTC (permalink / raw) To: linux-arm-kernel Hello Heiko, ARM guys When Jay first submitted the rk3399.dtsi upstream <https://patchwork.kernel.org/patch/8885821/> he had the PMU node in there, but then took it out because the upstream binding wasn't done yet. It looks as if the upstream stuff has landed, since in linux/master I see: 287e9357abcc DT/arm,gic-v3: Documment PPI partition support e3825ba1af3a irqchip/gic-v3: Add support for partitioned PPIs 9e2c986cb460 irqchip: Add per-cpu interrupt partitioning library 222df54fd8b7 genirq: Allow the affinity of a percpu interrupt to be set/retrieved 651e8b54abde irqdomain: Allow domain matching on irq_fwspec This series patches add to support the rk3399 SoCs PMU. I pick up the https://patchwork.kernel.org/patch/9209369/. As do some tests with ChromeOs for my rk3399 board. Tested with next-20160905 kernel on rk3399 board. https://github.com/Caesar-github/rockchip/tree/rk3399/pmu-upstream localhost / # perf list List of pre-defined events (to be used in -e): cpu-cycles OR cycles [Hardware event] instructions [Hardware event] cache-references [Hardware event] cache-misses [Hardware event] branch-instructions OR branches [Hardware event] branch-misses [Hardware event] bus-cycles [Hardware event] ... perf stat --cpu 0/1/2/3..... to minitor e.g. cpu0; localhost / # perf stat --cpu 0 Performance counter stats for 'CPU(s) 0': 3374.917571 task-clock (msec) # 1.001 CPUs utilized [100.00%] 20 context-switches # 0.006 K/sec [100.00%] 2 cpu-migrations # 0.001 K/sec [100.00%] 55 page-faults # 0.016 K/sec 7151843 cycles # 0.002 GHz [100.00%] <not supported> stalled-cycles-frontend <not supported> stalled-cycles-backend 4272536 instructions # 0.60 insns per cycle [100.00%] 568406 branches # 0.168 M/sec [100.00%] 65652 branch-misses # 11.55% of all branches Also, 'perf top' to monitor the PMU interrupts from cpus -Caesar Changes in v3: - update with the lastest next kernel(20160905). - add Mark's ACK for PATCH[1/2]. - updated on next kernel(20160905). - add the Mark's ACK for PATCH[2/2]. Changes in v2: - AS Mark comments on https://patchwork.kernel.org/patch/9209369/ remove the interrupt-affinity property, we need depend on Marc' perf code on https://patchwork.kernel.org/patch/9209369/. Caesar Wang (2): arm64: dts: rockchip: change all interrupts cells for 4 on rk3399 SoCs arm64: dts: rockchip: support the pmu node for rk3399 arch/arm64/boot/dts/rockchip/rk3399.dtsi | 122 ++++++++++++++++++------------- 1 file changed, 71 insertions(+), 51 deletions(-) -- 1.9.1 ^ permalink raw reply [flat|nested] 16+ messages in thread
* [PATCH v3 1/2] arm64: dts: rockchip: change all interrupts cells for 4 on rk3399 SoCs 2016-09-05 18:17 ` Caesar Wang @ 2016-09-05 18:17 ` Caesar Wang -1 siblings, 0 replies; 16+ messages in thread From: Caesar Wang @ 2016-09-05 18:17 UTC (permalink / raw) To: Heiko Stuebner Cc: linux-rockchip, Douglas Anderson, sonnyrao, linux-arm-kernel, Caesar Wang, Will Deacon, Marc Zyngier, devicetree, David Wu, Elaine Zhang, Brian Norris, linux-kernel, Huang Tao, Shawn Lin, Jianqun Xu, Mark Rutland, Rob Herring, Catalin Marinas Add the interrupts cells value for 4, and the 4th cell is zero. Due to the doc[0] said:" the system requires describing PPI affinity, then the value must be at least 4" The 4th cell is a phandle to a node describing a set of CPUs this interrupt is affine to. The interrupt must be a PPI, and the node pointed must be a subnode of the "ppi-partitions" subnode. For interrupt types other than PPI or PPIs that are not partitionned, this cell must be zero. See the "ppi-partitions" node description below. [0]: Documentation/devicetree/bindings/interrupt-controller/arm,gic-v3.txt Signed-off-by: Caesar Wang <wxt@rock-chips.com> Acked-by: Mark Rutland <mark.rutland@arm.com> Cc: Heiko Stuebner <heiko@sntech.de> Cc: Will Deacon <will.deacon@arm.com> Cc: Marc Zyngier <marc.zyngier@arm.com> CC: linux-arm-kernel@lists.infradead.org --- Changes in v3: - update with the lastest next kernel(20160905). - add Mark's ACK for PATCH[1/2]. Changes in v2: None arch/arm64/boot/dts/rockchip/rk3399.dtsi | 102 +++++++++++++++---------------- 1 file changed, 51 insertions(+), 51 deletions(-) diff --git a/arch/arm64/boot/dts/rockchip/rk3399.dtsi b/arch/arm64/boot/dts/rockchip/rk3399.dtsi index 6c89d77..e9e22fe 100644 --- a/arch/arm64/boot/dts/rockchip/rk3399.dtsi +++ b/arch/arm64/boot/dts/rockchip/rk3399.dtsi @@ -160,10 +160,10 @@ timer { compatible = "arm,armv8-timer"; - interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>, - <GIC_PPI 14 IRQ_TYPE_LEVEL_LOW>, - <GIC_PPI 11 IRQ_TYPE_LEVEL_LOW>, - <GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>; + interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW 0>, + <GIC_PPI 14 IRQ_TYPE_LEVEL_LOW 0>, + <GIC_PPI 11 IRQ_TYPE_LEVEL_LOW 0>, + <GIC_PPI 10 IRQ_TYPE_LEVEL_LOW 0>; }; xin24m: xin24m { @@ -182,8 +182,8 @@ dmac_bus: dma-controller@ff6d0000 { compatible = "arm,pl330", "arm,primecell"; reg = <0x0 0xff6d0000 0x0 0x4000>; - interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>; + interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH 0>, + <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH 0>; #dma-cells = <1>; clocks = <&cru ACLK_DMAC0_PERILP>; clock-names = "apb_pclk"; @@ -192,8 +192,8 @@ dmac_peri: dma-controller@ff6e0000 { compatible = "arm,pl330", "arm,primecell"; reg = <0x0 0xff6e0000 0x0 0x4000>; - interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>; + interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH 0>, + <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH 0>; #dma-cells = <1>; clocks = <&cru ACLK_DMAC1_PERILP>; clock-names = "apb_pclk"; @@ -204,7 +204,7 @@ compatible = "rockchip,rk3399-dw-mshc", "rockchip,rk3288-dw-mshc"; reg = <0x0 0xfe310000 0x0 0x4000>; - interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>; + interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH 0>; clock-freq-min-max = <400000 150000000>; clocks = <&cru HCLK_SDIO>, <&cru SCLK_SDIO>, <&cru SCLK_SDIO_DRV>, <&cru SCLK_SDIO_SAMPLE>; @@ -217,7 +217,7 @@ compatible = "rockchip,rk3399-dw-mshc", "rockchip,rk3288-dw-mshc"; reg = <0x0 0xfe320000 0x0 0x4000>; - interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>; + interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH 0>; clock-freq-min-max = <400000 150000000>; clocks = <&cru HCLK_SDMMC>, <&cru SCLK_SDMMC>, <&cru SCLK_SDMMC_DRV>, <&cru SCLK_SDMMC_SAMPLE>; @@ -229,7 +229,7 @@ sdhci: sdhci@fe330000 { compatible = "rockchip,rk3399-sdhci-5.1", "arasan,sdhci-5.1"; reg = <0x0 0xfe330000 0x0 0x10000>; - interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>; + interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH 0>; arasan,soc-ctl-syscon = <&grf>; assigned-clocks = <&cru SCLK_EMMC>; assigned-clock-rates = <200000000>; @@ -284,7 +284,7 @@ usb_host0_ehci: usb@fe380000 { compatible = "generic-ehci"; reg = <0x0 0xfe380000 0x0 0x20000>; - interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>; + interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH 0>; clocks = <&cru HCLK_HOST0>, <&cru HCLK_HOST0_ARB>; clock-names = "hclk_host0", "hclk_host0_arb"; phys = <&u2phy0_host>; @@ -295,7 +295,7 @@ usb_host0_ohci: usb@fe3a0000 { compatible = "generic-ohci"; reg = <0x0 0xfe3a0000 0x0 0x20000>; - interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>; + interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH 0>; clocks = <&cru HCLK_HOST0>, <&cru HCLK_HOST0_ARB>; clock-names = "hclk_host0", "hclk_host0_arb"; status = "disabled"; @@ -304,7 +304,7 @@ usb_host1_ehci: usb@fe3c0000 { compatible = "generic-ehci"; reg = <0x0 0xfe3c0000 0x0 0x20000>; - interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>; + interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH 0>; clocks = <&cru HCLK_HOST1>, <&cru HCLK_HOST1_ARB>; clock-names = "hclk_host1", "hclk_host1_arb"; phys = <&u2phy1_host>; @@ -315,7 +315,7 @@ usb_host1_ohci: usb@fe3e0000 { compatible = "generic-ohci"; reg = <0x0 0xfe3e0000 0x0 0x20000>; - interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>; + interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH 0>; clocks = <&cru HCLK_HOST1>, <&cru HCLK_HOST1_ARB>; clock-names = "hclk_host1", "hclk_host1_arb"; status = "disabled"; @@ -334,7 +334,7 @@ <0x0 0xfff00000 0 0x10000>, /* GICC */ <0x0 0xfff10000 0 0x10000>, /* GICH */ <0x0 0xfff20000 0 0x10000>; /* GICV */ - interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>; + interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH 0>; its: interrupt-controller@fee20000 { compatible = "arm,gic-v3-its"; msi-controller; @@ -345,7 +345,7 @@ saradc: saradc@ff100000 { compatible = "rockchip,rk3399-saradc"; reg = <0x0 0xff100000 0x0 0x100>; - interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>; + interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH 0>; #io-channel-cells = <1>; clocks = <&cru SCLK_SARADC>, <&cru PCLK_SARADC>; clock-names = "saradc", "apb_pclk"; @@ -361,7 +361,7 @@ assigned-clock-rates = <200000000>; clocks = <&cru SCLK_I2C1>, <&cru PCLK_I2C1>; clock-names = "i2c", "pclk"; - interrupts = <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>; + interrupts = <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH 0>; pinctrl-names = "default"; pinctrl-0 = <&i2c1_xfer>; #address-cells = <1>; @@ -376,7 +376,7 @@ assigned-clock-rates = <200000000>; clocks = <&cru SCLK_I2C2>, <&cru PCLK_I2C2>; clock-names = "i2c", "pclk"; - interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>; + interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH 0>; pinctrl-names = "default"; pinctrl-0 = <&i2c2_xfer>; #address-cells = <1>; @@ -391,7 +391,7 @@ assigned-clock-rates = <200000000>; clocks = <&cru SCLK_I2C3>, <&cru PCLK_I2C3>; clock-names = "i2c", "pclk"; - interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>; + interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH 0>; pinctrl-names = "default"; pinctrl-0 = <&i2c3_xfer>; #address-cells = <1>; @@ -406,7 +406,7 @@ assigned-clock-rates = <200000000>; clocks = <&cru SCLK_I2C5>, <&cru PCLK_I2C5>; clock-names = "i2c", "pclk"; - interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>; + interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH 0>; pinctrl-names = "default"; pinctrl-0 = <&i2c5_xfer>; #address-cells = <1>; @@ -421,7 +421,7 @@ assigned-clock-rates = <200000000>; clocks = <&cru SCLK_I2C6>, <&cru PCLK_I2C6>; clock-names = "i2c", "pclk"; - interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>; + interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH 0>; pinctrl-names = "default"; pinctrl-0 = <&i2c6_xfer>; #address-cells = <1>; @@ -436,7 +436,7 @@ assigned-clock-rates = <200000000>; clocks = <&cru SCLK_I2C7>, <&cru PCLK_I2C7>; clock-names = "i2c", "pclk"; - interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>; + interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH 0>; pinctrl-names = "default"; pinctrl-0 = <&i2c7_xfer>; #address-cells = <1>; @@ -449,7 +449,7 @@ reg = <0x0 0xff180000 0x0 0x100>; clocks = <&cru SCLK_UART0>, <&cru PCLK_UART0>; clock-names = "baudclk", "apb_pclk"; - interrupts = <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>; + interrupts = <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH 0>; reg-shift = <2>; reg-io-width = <4>; pinctrl-names = "default"; @@ -462,7 +462,7 @@ reg = <0x0 0xff190000 0x0 0x100>; clocks = <&cru SCLK_UART1>, <&cru PCLK_UART1>; clock-names = "baudclk", "apb_pclk"; - interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>; + interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH 0>; reg-shift = <2>; reg-io-width = <4>; pinctrl-names = "default"; @@ -475,7 +475,7 @@ reg = <0x0 0xff1a0000 0x0 0x100>; clocks = <&cru SCLK_UART2>, <&cru PCLK_UART2>; clock-names = "baudclk", "apb_pclk"; - interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>; + interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH 0>; reg-shift = <2>; reg-io-width = <4>; pinctrl-names = "default"; @@ -488,7 +488,7 @@ reg = <0x0 0xff1b0000 0x0 0x100>; clocks = <&cru SCLK_UART3>, <&cru PCLK_UART3>; clock-names = "baudclk", "apb_pclk"; - interrupts = <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>; + interrupts = <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH 0>; reg-shift = <2>; reg-io-width = <4>; pinctrl-names = "default"; @@ -501,7 +501,7 @@ reg = <0x0 0xff1c0000 0x0 0x1000>; clocks = <&cru SCLK_SPI0>, <&cru PCLK_SPI0>; clock-names = "spiclk", "apb_pclk"; - interrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>; + interrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH 0>; pinctrl-names = "default"; pinctrl-0 = <&spi0_clk &spi0_tx &spi0_rx &spi0_cs0>; #address-cells = <1>; @@ -514,7 +514,7 @@ reg = <0x0 0xff1d0000 0x0 0x1000>; clocks = <&cru SCLK_SPI1>, <&cru PCLK_SPI1>; clock-names = "spiclk", "apb_pclk"; - interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>; + interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH 0>; pinctrl-names = "default"; pinctrl-0 = <&spi1_clk &spi1_tx &spi1_rx &spi1_cs0>; #address-cells = <1>; @@ -527,7 +527,7 @@ reg = <0x0 0xff1e0000 0x0 0x1000>; clocks = <&cru SCLK_SPI2>, <&cru PCLK_SPI2>; clock-names = "spiclk", "apb_pclk"; - interrupts = <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>; + interrupts = <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH 0>; pinctrl-names = "default"; pinctrl-0 = <&spi2_clk &spi2_tx &spi2_rx &spi2_cs0>; #address-cells = <1>; @@ -540,7 +540,7 @@ reg = <0x0 0xff1f0000 0x0 0x1000>; clocks = <&cru SCLK_SPI4>, <&cru PCLK_SPI4>; clock-names = "spiclk", "apb_pclk"; - interrupts = <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>; + interrupts = <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH 0>; pinctrl-names = "default"; pinctrl-0 = <&spi4_clk &spi4_tx &spi4_rx &spi4_cs0>; #address-cells = <1>; @@ -553,7 +553,7 @@ reg = <0x0 0xff200000 0x0 0x1000>; clocks = <&cru SCLK_SPI5>, <&cru PCLK_SPI5>; clock-names = "spiclk", "apb_pclk"; - interrupts = <GIC_SPI 132 IRQ_TYPE_LEVEL_HIGH>; + interrupts = <GIC_SPI 132 IRQ_TYPE_LEVEL_HIGH 0>; pinctrl-names = "default"; pinctrl-0 = <&spi5_clk &spi5_tx &spi5_rx &spi5_cs0>; #address-cells = <1>; @@ -633,7 +633,7 @@ tsadc: tsadc@ff260000 { compatible = "rockchip,rk3399-tsadc"; reg = <0x0 0xff260000 0x0 0x100>; - interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>; + interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH 0>; assigned-clocks = <&cru SCLK_TSADC>; assigned-clock-rates = <750000>; clocks = <&cru SCLK_TSADC>, <&cru PCLK_TSADC>; @@ -864,7 +864,7 @@ reg = <0x0 0xff350000 0x0 0x1000>; clocks = <&pmucru SCLK_SPI3_PMU>, <&pmucru PCLK_SPI3_PMU>; clock-names = "spiclk", "apb_pclk"; - interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>; + interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH 0>; pinctrl-names = "default"; pinctrl-0 = <&spi3_clk &spi3_tx &spi3_rx &spi3_cs0>; #address-cells = <1>; @@ -877,7 +877,7 @@ reg = <0x0 0xff370000 0x0 0x100>; clocks = <&pmucru SCLK_UART4_PMU>, <&pmucru PCLK_UART4_PMU>; clock-names = "baudclk", "apb_pclk"; - interrupts = <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>; + interrupts = <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH 0>; reg-shift = <2>; reg-io-width = <4>; pinctrl-names = "default"; @@ -892,7 +892,7 @@ assigned-clock-rates = <200000000>; clocks = <&pmucru SCLK_I2C0_PMU>, <&pmucru PCLK_I2C0_PMU>; clock-names = "i2c", "pclk"; - interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>; + interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH 0>; pinctrl-names = "default"; pinctrl-0 = <&i2c0_xfer>; #address-cells = <1>; @@ -907,7 +907,7 @@ assigned-clock-rates = <200000000>; clocks = <&pmucru SCLK_I2C4_PMU>, <&pmucru PCLK_I2C4_PMU>; clock-names = "i2c", "pclk"; - interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>; + interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH 0>; pinctrl-names = "default"; pinctrl-0 = <&i2c4_xfer>; #address-cells = <1>; @@ -922,7 +922,7 @@ assigned-clock-rates = <200000000>; clocks = <&pmucru SCLK_I2C8_PMU>, <&pmucru PCLK_I2C8_PMU>; clock-names = "i2c", "pclk"; - interrupts = <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>; + interrupts = <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH 0>; pinctrl-names = "default"; pinctrl-0 = <&i2c8_xfer>; #address-cells = <1>; @@ -1057,7 +1057,7 @@ u2phy0_host: host-port { #phy-cells = <0>; - interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>; + interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH 0>; interrupt-names = "linestate"; status = "disabled"; }; @@ -1074,7 +1074,7 @@ u2phy1_host: host-port { #phy-cells = <0>; - interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>; + interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH 0>; interrupt-names = "linestate"; status = "disabled"; }; @@ -1104,13 +1104,13 @@ compatible = "snps,dw-wdt"; reg = <0x0 0xff848000 0x0 0x100>; clocks = <&cru PCLK_WDT>; - interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>; + interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH 0>; }; rktimer: rktimer@ff850000 { compatible = "rockchip,rk3399-timer"; reg = <0x0 0xff850000 0x0 0x1000>; - interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>; + interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH 0>; clocks = <&cru PCLK_TIMER0>, <&cru SCLK_TIMER00>; clock-names = "pclk", "timer"; }; @@ -1118,7 +1118,7 @@ spdif: spdif@ff870000 { compatible = "rockchip,rk3399-spdif"; reg = <0x0 0xff870000 0x0 0x1000>; - interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>; + interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH 0>; dmas = <&dmac_bus 7>; dma-names = "tx"; clock-names = "mclk", "hclk"; @@ -1132,7 +1132,7 @@ compatible = "rockchip,rk3399-i2s", "rockchip,rk3066-i2s"; reg = <0x0 0xff880000 0x0 0x1000>; rockchip,grf = <&grf>; - interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>; + interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH 0>; dmas = <&dmac_bus 0>, <&dmac_bus 1>; dma-names = "tx", "rx"; clock-names = "i2s_clk", "i2s_hclk"; @@ -1145,7 +1145,7 @@ i2s1: i2s@ff890000 { compatible = "rockchip,rk3399-i2s", "rockchip,rk3066-i2s"; reg = <0x0 0xff890000 0x0 0x1000>; - interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>; + interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH 0>; dmas = <&dmac_bus 2>, <&dmac_bus 3>; dma-names = "tx", "rx"; clock-names = "i2s_clk", "i2s_hclk"; @@ -1158,7 +1158,7 @@ i2s2: i2s@ff8a0000 { compatible = "rockchip,rk3399-i2s", "rockchip,rk3066-i2s"; reg = <0x0 0xff8a0000 0x0 0x1000>; - interrupts = <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>; + interrupts = <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH 0>; dmas = <&dmac_bus 4>, <&dmac_bus 5>; dma-names = "tx", "rx"; clock-names = "i2s_clk", "i2s_hclk"; @@ -1178,7 +1178,7 @@ compatible = "rockchip,gpio-bank"; reg = <0x0 0xff720000 0x0 0x100>; clocks = <&pmucru PCLK_GPIO0_PMU>; - interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>; + interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH 0>; gpio-controller; #gpio-cells = <0x2>; @@ -1191,7 +1191,7 @@ compatible = "rockchip,gpio-bank"; reg = <0x0 0xff730000 0x0 0x100>; clocks = <&pmucru PCLK_GPIO1_PMU>; - interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>; + interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH 0>; gpio-controller; #gpio-cells = <0x2>; @@ -1204,7 +1204,7 @@ compatible = "rockchip,gpio-bank"; reg = <0x0 0xff780000 0x0 0x100>; clocks = <&cru PCLK_GPIO2>; - interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>; + interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH 0>; gpio-controller; #gpio-cells = <0x2>; @@ -1217,7 +1217,7 @@ compatible = "rockchip,gpio-bank"; reg = <0x0 0xff788000 0x0 0x100>; clocks = <&cru PCLK_GPIO3>; - interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>; + interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH 0>; gpio-controller; #gpio-cells = <0x2>; @@ -1230,7 +1230,7 @@ compatible = "rockchip,gpio-bank"; reg = <0x0 0xff790000 0x0 0x100>; clocks = <&cru PCLK_GPIO4>; - interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>; + interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH 0>; gpio-controller; #gpio-cells = <0x2>; -- 1.9.1 ^ permalink raw reply related [flat|nested] 16+ messages in thread
* [PATCH v3 1/2] arm64: dts: rockchip: change all interrupts cells for 4 on rk3399 SoCs @ 2016-09-05 18:17 ` Caesar Wang 0 siblings, 0 replies; 16+ messages in thread From: Caesar Wang @ 2016-09-05 18:17 UTC (permalink / raw) To: linux-arm-kernel Add the interrupts cells value for 4, and the 4th cell is zero. Due to the doc[0] said:" the system requires describing PPI affinity, then the value must be at least 4" The 4th cell is a phandle to a node describing a set of CPUs this interrupt is affine to. The interrupt must be a PPI, and the node pointed must be a subnode of the "ppi-partitions" subnode. For interrupt types other than PPI or PPIs that are not partitionned, this cell must be zero. See the "ppi-partitions" node description below. [0]: Documentation/devicetree/bindings/interrupt-controller/arm,gic-v3.txt Signed-off-by: Caesar Wang <wxt@rock-chips.com> Acked-by: Mark Rutland <mark.rutland@arm.com> Cc: Heiko Stuebner <heiko@sntech.de> Cc: Will Deacon <will.deacon@arm.com> Cc: Marc Zyngier <marc.zyngier@arm.com> CC: linux-arm-kernel at lists.infradead.org --- Changes in v3: - update with the lastest next kernel(20160905). - add Mark's ACK for PATCH[1/2]. Changes in v2: None arch/arm64/boot/dts/rockchip/rk3399.dtsi | 102 +++++++++++++++---------------- 1 file changed, 51 insertions(+), 51 deletions(-) diff --git a/arch/arm64/boot/dts/rockchip/rk3399.dtsi b/arch/arm64/boot/dts/rockchip/rk3399.dtsi index 6c89d77..e9e22fe 100644 --- a/arch/arm64/boot/dts/rockchip/rk3399.dtsi +++ b/arch/arm64/boot/dts/rockchip/rk3399.dtsi @@ -160,10 +160,10 @@ timer { compatible = "arm,armv8-timer"; - interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>, - <GIC_PPI 14 IRQ_TYPE_LEVEL_LOW>, - <GIC_PPI 11 IRQ_TYPE_LEVEL_LOW>, - <GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>; + interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW 0>, + <GIC_PPI 14 IRQ_TYPE_LEVEL_LOW 0>, + <GIC_PPI 11 IRQ_TYPE_LEVEL_LOW 0>, + <GIC_PPI 10 IRQ_TYPE_LEVEL_LOW 0>; }; xin24m: xin24m { @@ -182,8 +182,8 @@ dmac_bus: dma-controller at ff6d0000 { compatible = "arm,pl330", "arm,primecell"; reg = <0x0 0xff6d0000 0x0 0x4000>; - interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>; + interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH 0>, + <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH 0>; #dma-cells = <1>; clocks = <&cru ACLK_DMAC0_PERILP>; clock-names = "apb_pclk"; @@ -192,8 +192,8 @@ dmac_peri: dma-controller at ff6e0000 { compatible = "arm,pl330", "arm,primecell"; reg = <0x0 0xff6e0000 0x0 0x4000>; - interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>; + interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH 0>, + <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH 0>; #dma-cells = <1>; clocks = <&cru ACLK_DMAC1_PERILP>; clock-names = "apb_pclk"; @@ -204,7 +204,7 @@ compatible = "rockchip,rk3399-dw-mshc", "rockchip,rk3288-dw-mshc"; reg = <0x0 0xfe310000 0x0 0x4000>; - interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>; + interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH 0>; clock-freq-min-max = <400000 150000000>; clocks = <&cru HCLK_SDIO>, <&cru SCLK_SDIO>, <&cru SCLK_SDIO_DRV>, <&cru SCLK_SDIO_SAMPLE>; @@ -217,7 +217,7 @@ compatible = "rockchip,rk3399-dw-mshc", "rockchip,rk3288-dw-mshc"; reg = <0x0 0xfe320000 0x0 0x4000>; - interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>; + interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH 0>; clock-freq-min-max = <400000 150000000>; clocks = <&cru HCLK_SDMMC>, <&cru SCLK_SDMMC>, <&cru SCLK_SDMMC_DRV>, <&cru SCLK_SDMMC_SAMPLE>; @@ -229,7 +229,7 @@ sdhci: sdhci at fe330000 { compatible = "rockchip,rk3399-sdhci-5.1", "arasan,sdhci-5.1"; reg = <0x0 0xfe330000 0x0 0x10000>; - interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>; + interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH 0>; arasan,soc-ctl-syscon = <&grf>; assigned-clocks = <&cru SCLK_EMMC>; assigned-clock-rates = <200000000>; @@ -284,7 +284,7 @@ usb_host0_ehci: usb at fe380000 { compatible = "generic-ehci"; reg = <0x0 0xfe380000 0x0 0x20000>; - interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>; + interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH 0>; clocks = <&cru HCLK_HOST0>, <&cru HCLK_HOST0_ARB>; clock-names = "hclk_host0", "hclk_host0_arb"; phys = <&u2phy0_host>; @@ -295,7 +295,7 @@ usb_host0_ohci: usb at fe3a0000 { compatible = "generic-ohci"; reg = <0x0 0xfe3a0000 0x0 0x20000>; - interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>; + interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH 0>; clocks = <&cru HCLK_HOST0>, <&cru HCLK_HOST0_ARB>; clock-names = "hclk_host0", "hclk_host0_arb"; status = "disabled"; @@ -304,7 +304,7 @@ usb_host1_ehci: usb at fe3c0000 { compatible = "generic-ehci"; reg = <0x0 0xfe3c0000 0x0 0x20000>; - interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>; + interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH 0>; clocks = <&cru HCLK_HOST1>, <&cru HCLK_HOST1_ARB>; clock-names = "hclk_host1", "hclk_host1_arb"; phys = <&u2phy1_host>; @@ -315,7 +315,7 @@ usb_host1_ohci: usb at fe3e0000 { compatible = "generic-ohci"; reg = <0x0 0xfe3e0000 0x0 0x20000>; - interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>; + interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH 0>; clocks = <&cru HCLK_HOST1>, <&cru HCLK_HOST1_ARB>; clock-names = "hclk_host1", "hclk_host1_arb"; status = "disabled"; @@ -334,7 +334,7 @@ <0x0 0xfff00000 0 0x10000>, /* GICC */ <0x0 0xfff10000 0 0x10000>, /* GICH */ <0x0 0xfff20000 0 0x10000>; /* GICV */ - interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>; + interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH 0>; its: interrupt-controller at fee20000 { compatible = "arm,gic-v3-its"; msi-controller; @@ -345,7 +345,7 @@ saradc: saradc at ff100000 { compatible = "rockchip,rk3399-saradc"; reg = <0x0 0xff100000 0x0 0x100>; - interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>; + interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH 0>; #io-channel-cells = <1>; clocks = <&cru SCLK_SARADC>, <&cru PCLK_SARADC>; clock-names = "saradc", "apb_pclk"; @@ -361,7 +361,7 @@ assigned-clock-rates = <200000000>; clocks = <&cru SCLK_I2C1>, <&cru PCLK_I2C1>; clock-names = "i2c", "pclk"; - interrupts = <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>; + interrupts = <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH 0>; pinctrl-names = "default"; pinctrl-0 = <&i2c1_xfer>; #address-cells = <1>; @@ -376,7 +376,7 @@ assigned-clock-rates = <200000000>; clocks = <&cru SCLK_I2C2>, <&cru PCLK_I2C2>; clock-names = "i2c", "pclk"; - interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>; + interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH 0>; pinctrl-names = "default"; pinctrl-0 = <&i2c2_xfer>; #address-cells = <1>; @@ -391,7 +391,7 @@ assigned-clock-rates = <200000000>; clocks = <&cru SCLK_I2C3>, <&cru PCLK_I2C3>; clock-names = "i2c", "pclk"; - interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>; + interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH 0>; pinctrl-names = "default"; pinctrl-0 = <&i2c3_xfer>; #address-cells = <1>; @@ -406,7 +406,7 @@ assigned-clock-rates = <200000000>; clocks = <&cru SCLK_I2C5>, <&cru PCLK_I2C5>; clock-names = "i2c", "pclk"; - interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>; + interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH 0>; pinctrl-names = "default"; pinctrl-0 = <&i2c5_xfer>; #address-cells = <1>; @@ -421,7 +421,7 @@ assigned-clock-rates = <200000000>; clocks = <&cru SCLK_I2C6>, <&cru PCLK_I2C6>; clock-names = "i2c", "pclk"; - interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>; + interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH 0>; pinctrl-names = "default"; pinctrl-0 = <&i2c6_xfer>; #address-cells = <1>; @@ -436,7 +436,7 @@ assigned-clock-rates = <200000000>; clocks = <&cru SCLK_I2C7>, <&cru PCLK_I2C7>; clock-names = "i2c", "pclk"; - interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>; + interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH 0>; pinctrl-names = "default"; pinctrl-0 = <&i2c7_xfer>; #address-cells = <1>; @@ -449,7 +449,7 @@ reg = <0x0 0xff180000 0x0 0x100>; clocks = <&cru SCLK_UART0>, <&cru PCLK_UART0>; clock-names = "baudclk", "apb_pclk"; - interrupts = <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>; + interrupts = <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH 0>; reg-shift = <2>; reg-io-width = <4>; pinctrl-names = "default"; @@ -462,7 +462,7 @@ reg = <0x0 0xff190000 0x0 0x100>; clocks = <&cru SCLK_UART1>, <&cru PCLK_UART1>; clock-names = "baudclk", "apb_pclk"; - interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>; + interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH 0>; reg-shift = <2>; reg-io-width = <4>; pinctrl-names = "default"; @@ -475,7 +475,7 @@ reg = <0x0 0xff1a0000 0x0 0x100>; clocks = <&cru SCLK_UART2>, <&cru PCLK_UART2>; clock-names = "baudclk", "apb_pclk"; - interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>; + interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH 0>; reg-shift = <2>; reg-io-width = <4>; pinctrl-names = "default"; @@ -488,7 +488,7 @@ reg = <0x0 0xff1b0000 0x0 0x100>; clocks = <&cru SCLK_UART3>, <&cru PCLK_UART3>; clock-names = "baudclk", "apb_pclk"; - interrupts = <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>; + interrupts = <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH 0>; reg-shift = <2>; reg-io-width = <4>; pinctrl-names = "default"; @@ -501,7 +501,7 @@ reg = <0x0 0xff1c0000 0x0 0x1000>; clocks = <&cru SCLK_SPI0>, <&cru PCLK_SPI0>; clock-names = "spiclk", "apb_pclk"; - interrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>; + interrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH 0>; pinctrl-names = "default"; pinctrl-0 = <&spi0_clk &spi0_tx &spi0_rx &spi0_cs0>; #address-cells = <1>; @@ -514,7 +514,7 @@ reg = <0x0 0xff1d0000 0x0 0x1000>; clocks = <&cru SCLK_SPI1>, <&cru PCLK_SPI1>; clock-names = "spiclk", "apb_pclk"; - interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>; + interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH 0>; pinctrl-names = "default"; pinctrl-0 = <&spi1_clk &spi1_tx &spi1_rx &spi1_cs0>; #address-cells = <1>; @@ -527,7 +527,7 @@ reg = <0x0 0xff1e0000 0x0 0x1000>; clocks = <&cru SCLK_SPI2>, <&cru PCLK_SPI2>; clock-names = "spiclk", "apb_pclk"; - interrupts = <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>; + interrupts = <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH 0>; pinctrl-names = "default"; pinctrl-0 = <&spi2_clk &spi2_tx &spi2_rx &spi2_cs0>; #address-cells = <1>; @@ -540,7 +540,7 @@ reg = <0x0 0xff1f0000 0x0 0x1000>; clocks = <&cru SCLK_SPI4>, <&cru PCLK_SPI4>; clock-names = "spiclk", "apb_pclk"; - interrupts = <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>; + interrupts = <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH 0>; pinctrl-names = "default"; pinctrl-0 = <&spi4_clk &spi4_tx &spi4_rx &spi4_cs0>; #address-cells = <1>; @@ -553,7 +553,7 @@ reg = <0x0 0xff200000 0x0 0x1000>; clocks = <&cru SCLK_SPI5>, <&cru PCLK_SPI5>; clock-names = "spiclk", "apb_pclk"; - interrupts = <GIC_SPI 132 IRQ_TYPE_LEVEL_HIGH>; + interrupts = <GIC_SPI 132 IRQ_TYPE_LEVEL_HIGH 0>; pinctrl-names = "default"; pinctrl-0 = <&spi5_clk &spi5_tx &spi5_rx &spi5_cs0>; #address-cells = <1>; @@ -633,7 +633,7 @@ tsadc: tsadc at ff260000 { compatible = "rockchip,rk3399-tsadc"; reg = <0x0 0xff260000 0x0 0x100>; - interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>; + interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH 0>; assigned-clocks = <&cru SCLK_TSADC>; assigned-clock-rates = <750000>; clocks = <&cru SCLK_TSADC>, <&cru PCLK_TSADC>; @@ -864,7 +864,7 @@ reg = <0x0 0xff350000 0x0 0x1000>; clocks = <&pmucru SCLK_SPI3_PMU>, <&pmucru PCLK_SPI3_PMU>; clock-names = "spiclk", "apb_pclk"; - interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>; + interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH 0>; pinctrl-names = "default"; pinctrl-0 = <&spi3_clk &spi3_tx &spi3_rx &spi3_cs0>; #address-cells = <1>; @@ -877,7 +877,7 @@ reg = <0x0 0xff370000 0x0 0x100>; clocks = <&pmucru SCLK_UART4_PMU>, <&pmucru PCLK_UART4_PMU>; clock-names = "baudclk", "apb_pclk"; - interrupts = <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>; + interrupts = <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH 0>; reg-shift = <2>; reg-io-width = <4>; pinctrl-names = "default"; @@ -892,7 +892,7 @@ assigned-clock-rates = <200000000>; clocks = <&pmucru SCLK_I2C0_PMU>, <&pmucru PCLK_I2C0_PMU>; clock-names = "i2c", "pclk"; - interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>; + interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH 0>; pinctrl-names = "default"; pinctrl-0 = <&i2c0_xfer>; #address-cells = <1>; @@ -907,7 +907,7 @@ assigned-clock-rates = <200000000>; clocks = <&pmucru SCLK_I2C4_PMU>, <&pmucru PCLK_I2C4_PMU>; clock-names = "i2c", "pclk"; - interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>; + interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH 0>; pinctrl-names = "default"; pinctrl-0 = <&i2c4_xfer>; #address-cells = <1>; @@ -922,7 +922,7 @@ assigned-clock-rates = <200000000>; clocks = <&pmucru SCLK_I2C8_PMU>, <&pmucru PCLK_I2C8_PMU>; clock-names = "i2c", "pclk"; - interrupts = <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>; + interrupts = <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH 0>; pinctrl-names = "default"; pinctrl-0 = <&i2c8_xfer>; #address-cells = <1>; @@ -1057,7 +1057,7 @@ u2phy0_host: host-port { #phy-cells = <0>; - interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>; + interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH 0>; interrupt-names = "linestate"; status = "disabled"; }; @@ -1074,7 +1074,7 @@ u2phy1_host: host-port { #phy-cells = <0>; - interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>; + interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH 0>; interrupt-names = "linestate"; status = "disabled"; }; @@ -1104,13 +1104,13 @@ compatible = "snps,dw-wdt"; reg = <0x0 0xff848000 0x0 0x100>; clocks = <&cru PCLK_WDT>; - interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>; + interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH 0>; }; rktimer: rktimer at ff850000 { compatible = "rockchip,rk3399-timer"; reg = <0x0 0xff850000 0x0 0x1000>; - interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>; + interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH 0>; clocks = <&cru PCLK_TIMER0>, <&cru SCLK_TIMER00>; clock-names = "pclk", "timer"; }; @@ -1118,7 +1118,7 @@ spdif: spdif at ff870000 { compatible = "rockchip,rk3399-spdif"; reg = <0x0 0xff870000 0x0 0x1000>; - interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>; + interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH 0>; dmas = <&dmac_bus 7>; dma-names = "tx"; clock-names = "mclk", "hclk"; @@ -1132,7 +1132,7 @@ compatible = "rockchip,rk3399-i2s", "rockchip,rk3066-i2s"; reg = <0x0 0xff880000 0x0 0x1000>; rockchip,grf = <&grf>; - interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>; + interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH 0>; dmas = <&dmac_bus 0>, <&dmac_bus 1>; dma-names = "tx", "rx"; clock-names = "i2s_clk", "i2s_hclk"; @@ -1145,7 +1145,7 @@ i2s1: i2s at ff890000 { compatible = "rockchip,rk3399-i2s", "rockchip,rk3066-i2s"; reg = <0x0 0xff890000 0x0 0x1000>; - interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>; + interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH 0>; dmas = <&dmac_bus 2>, <&dmac_bus 3>; dma-names = "tx", "rx"; clock-names = "i2s_clk", "i2s_hclk"; @@ -1158,7 +1158,7 @@ i2s2: i2s at ff8a0000 { compatible = "rockchip,rk3399-i2s", "rockchip,rk3066-i2s"; reg = <0x0 0xff8a0000 0x0 0x1000>; - interrupts = <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>; + interrupts = <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH 0>; dmas = <&dmac_bus 4>, <&dmac_bus 5>; dma-names = "tx", "rx"; clock-names = "i2s_clk", "i2s_hclk"; @@ -1178,7 +1178,7 @@ compatible = "rockchip,gpio-bank"; reg = <0x0 0xff720000 0x0 0x100>; clocks = <&pmucru PCLK_GPIO0_PMU>; - interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>; + interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH 0>; gpio-controller; #gpio-cells = <0x2>; @@ -1191,7 +1191,7 @@ compatible = "rockchip,gpio-bank"; reg = <0x0 0xff730000 0x0 0x100>; clocks = <&pmucru PCLK_GPIO1_PMU>; - interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>; + interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH 0>; gpio-controller; #gpio-cells = <0x2>; @@ -1204,7 +1204,7 @@ compatible = "rockchip,gpio-bank"; reg = <0x0 0xff780000 0x0 0x100>; clocks = <&cru PCLK_GPIO2>; - interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>; + interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH 0>; gpio-controller; #gpio-cells = <0x2>; @@ -1217,7 +1217,7 @@ compatible = "rockchip,gpio-bank"; reg = <0x0 0xff788000 0x0 0x100>; clocks = <&cru PCLK_GPIO3>; - interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>; + interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH 0>; gpio-controller; #gpio-cells = <0x2>; @@ -1230,7 +1230,7 @@ compatible = "rockchip,gpio-bank"; reg = <0x0 0xff790000 0x0 0x100>; clocks = <&cru PCLK_GPIO4>; - interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>; + interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH 0>; gpio-controller; #gpio-cells = <0x2>; -- 1.9.1 ^ permalink raw reply related [flat|nested] 16+ messages in thread
[parent not found: <1473099435-28198-2-git-send-email-wxt-TNX95d0MmH7DzftRWevZcw@public.gmane.org>]
* Re: [PATCH v3 1/2] arm64: dts: rockchip: change all interrupts cells for 4 on rk3399 SoCs 2016-09-05 18:17 ` Caesar Wang (?) @ 2016-09-05 22:20 ` Heiko Stuebner -1 siblings, 0 replies; 16+ messages in thread From: Heiko Stuebner @ 2016-09-05 22:20 UTC (permalink / raw) To: Caesar Wang Cc: linux-rockchip-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r, Douglas Anderson, sonnyrao-F7+t8E8rja9g9hUCZPvPmw, linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r, Will Deacon, Marc Zyngier, devicetree-u79uwXL29TY76Z2rM5mHXA, David Wu, Elaine Zhang, Brian Norris, linux-kernel-u79uwXL29TY76Z2rM5mHXA, Huang Tao, Shawn Lin, Jianqun Xu, Mark Rutland, Rob Herring, Catalin Marinas Am Dienstag, 6. September 2016, 02:17:14 CEST schrieb Caesar Wang: > Add the interrupts cells value for 4, and the 4th cell is zero. > > Due to the doc[0] said:" the system requires describing PPI affinity, > then the value must be at least 4" > The 4th cell is a phandle to a node describing a set of CPUs this > interrupt is affine to. The interrupt must be a PPI, and the node > pointed must be a subnode of the "ppi-partitions" subnode. For > interrupt types other than PPI or PPIs that are not partitionned, > this cell must be zero. See the "ppi-partitions" node description > below. > > [0]: > Documentation/devicetree/bindings/interrupt-controller/arm,gic-v3.txt > > Signed-off-by: Caesar Wang <wxt-TNX95d0MmH7DzftRWevZcw@public.gmane.org> > Acked-by: Mark Rutland <mark.rutland-5wv7dgnIgG8@public.gmane.org> > Cc: Heiko Stuebner <heiko-4mtYJXux2i+zQB+pC5nmwQ@public.gmane.org> > Cc: Will Deacon <will.deacon-5wv7dgnIgG8@public.gmane.org> > Cc: Marc Zyngier <marc.zyngier-5wv7dgnIgG8@public.gmane.org> > CC: linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r@public.gmane.org applied to my dts64 branch for 4.9 Thanks Heiko -- To unsubscribe from this list: send the line "unsubscribe devicetree" in the body of a message to majordomo-u79uwXL29TY76Z2rM5mHXA@public.gmane.org More majordomo info at http://vger.kernel.org/majordomo-info.html ^ permalink raw reply [flat|nested] 16+ messages in thread
* Re: [PATCH v3 1/2] arm64: dts: rockchip: change all interrupts cells for 4 on rk3399 SoCs @ 2016-09-05 22:20 ` Heiko Stuebner 0 siblings, 0 replies; 16+ messages in thread From: Heiko Stuebner @ 2016-09-05 22:20 UTC (permalink / raw) To: Caesar Wang Cc: linux-rockchip, Douglas Anderson, sonnyrao, linux-arm-kernel, Will Deacon, Marc Zyngier, devicetree, David Wu, Elaine Zhang, Brian Norris, linux-kernel, Huang Tao, Shawn Lin, Jianqun Xu, Mark Rutland, Rob Herring, Catalin Marinas Am Dienstag, 6. September 2016, 02:17:14 CEST schrieb Caesar Wang: > Add the interrupts cells value for 4, and the 4th cell is zero. > > Due to the doc[0] said:" the system requires describing PPI affinity, > then the value must be at least 4" > The 4th cell is a phandle to a node describing a set of CPUs this > interrupt is affine to. The interrupt must be a PPI, and the node > pointed must be a subnode of the "ppi-partitions" subnode. For > interrupt types other than PPI or PPIs that are not partitionned, > this cell must be zero. See the "ppi-partitions" node description > below. > > [0]: > Documentation/devicetree/bindings/interrupt-controller/arm,gic-v3.txt > > Signed-off-by: Caesar Wang <wxt@rock-chips.com> > Acked-by: Mark Rutland <mark.rutland@arm.com> > Cc: Heiko Stuebner <heiko@sntech.de> > Cc: Will Deacon <will.deacon@arm.com> > Cc: Marc Zyngier <marc.zyngier@arm.com> > CC: linux-arm-kernel@lists.infradead.org applied to my dts64 branch for 4.9 Thanks Heiko ^ permalink raw reply [flat|nested] 16+ messages in thread
* [PATCH v3 1/2] arm64: dts: rockchip: change all interrupts cells for 4 on rk3399 SoCs @ 2016-09-05 22:20 ` Heiko Stuebner 0 siblings, 0 replies; 16+ messages in thread From: Heiko Stuebner @ 2016-09-05 22:20 UTC (permalink / raw) To: linux-arm-kernel Am Dienstag, 6. September 2016, 02:17:14 CEST schrieb Caesar Wang: > Add the interrupts cells value for 4, and the 4th cell is zero. > > Due to the doc[0] said:" the system requires describing PPI affinity, > then the value must be at least 4" > The 4th cell is a phandle to a node describing a set of CPUs this > interrupt is affine to. The interrupt must be a PPI, and the node > pointed must be a subnode of the "ppi-partitions" subnode. For > interrupt types other than PPI or PPIs that are not partitionned, > this cell must be zero. See the "ppi-partitions" node description > below. > > [0]: > Documentation/devicetree/bindings/interrupt-controller/arm,gic-v3.txt > > Signed-off-by: Caesar Wang <wxt@rock-chips.com> > Acked-by: Mark Rutland <mark.rutland@arm.com> > Cc: Heiko Stuebner <heiko@sntech.de> > Cc: Will Deacon <will.deacon@arm.com> > Cc: Marc Zyngier <marc.zyngier@arm.com> > CC: linux-arm-kernel at lists.infradead.org applied to my dts64 branch for 4.9 Thanks Heiko ^ permalink raw reply [flat|nested] 16+ messages in thread
[parent not found: <1473099435-28198-1-git-send-email-wxt-TNX95d0MmH7DzftRWevZcw@public.gmane.org>]
* [PATCH v3 2/2] arm64: dts: rockchip: support the pmu node for rk3399 2016-09-05 18:17 ` Caesar Wang (?) @ 2016-09-05 18:17 ` Caesar Wang -1 siblings, 0 replies; 16+ messages in thread From: Caesar Wang @ 2016-09-05 18:17 UTC (permalink / raw) To: Heiko Stuebner Cc: linux-rockchip-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r, Douglas Anderson, sonnyrao-F7+t8E8rja9g9hUCZPvPmw, linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r, Caesar Wang, Marc Zyngier, devicetree-u79uwXL29TY76Z2rM5mHXA, David Wu, Elaine Zhang, Brian Norris, linux-kernel-u79uwXL29TY76Z2rM5mHXA, Shawn Lin, Will Deacon, Jianqun Xu, Mark Rutland, Rob Herring, Catalin Marinas, Xing Zheng This patch adds to enable the ARM Performance Monitor Units for rk3399. ARM cores often have a PMU for counting cpu and cache events like cache misses and hits. Also, as the Marc posted the patches [0] to support Partitioning per-cpu interrupts. Let's add this patch to match it on rk3399 SoCs. [0]: https://lkml.org/lkml/2016/4/11/182 Signed-off-by: Caesar Wang <wxt-TNX95d0MmH7DzftRWevZcw@public.gmane.org> Acked-by: Mark Rutland <mark.rutland-5wv7dgnIgG8@public.gmane.org> Cc: Heiko Stuebner <heiko-4mtYJXux2i+zQB+pC5nmwQ@public.gmane.org> Cc: Marc Zyngier <marc.zyngier-5wv7dgnIgG8@public.gmane.org> CC: linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r@public.gmane.org --- Changes in v3: - updated on next kernel(20160905). - add the Mark's ACK for PATCH[2/2]. Changes in v2: - AS Mark comments on https://patchwork.kernel.org/patch/9209369/ remove the interrupt-affinity property, we need depend on Marc' perf code on https://patchwork.kernel.org/patch/9209369/. arch/arm64/boot/dts/rockchip/rk3399.dtsi | 20 ++++++++++++++++++++ 1 file changed, 20 insertions(+) diff --git a/arch/arm64/boot/dts/rockchip/rk3399.dtsi b/arch/arm64/boot/dts/rockchip/rk3399.dtsi index e9e22fe..4e65f3b 100644 --- a/arch/arm64/boot/dts/rockchip/rk3399.dtsi +++ b/arch/arm64/boot/dts/rockchip/rk3399.dtsi @@ -166,6 +166,16 @@ <GIC_PPI 10 IRQ_TYPE_LEVEL_LOW 0>; }; + pmu_a53 { + compatible = "arm,cortex-a53-pmu"; + interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_LOW &part0>; + }; + + pmu_a72 { + compatible = "arm,cortex-a72-pmu"; + interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_LOW &part1>; + }; + xin24m: xin24m { compatible = "fixed-clock"; clock-frequency = <24000000>; @@ -354,6 +364,16 @@ status = "disabled"; }; + ppi-partitions { + part0: interrupt-partition-0 { + affinity = <&cpu_l0 &cpu_l1 &cpu_l2 &cpu_l3>; + }; + + part1: interrupt-partition-1 { + affinity = <&cpu_b0 &cpu_b1>; + }; + }; + i2c1: i2c@ff110000 { compatible = "rockchip,rk3399-i2c"; reg = <0x0 0xff110000 0x0 0x1000>; -- 1.9.1 -- To unsubscribe from this list: send the line "unsubscribe devicetree" in the body of a message to majordomo-u79uwXL29TY76Z2rM5mHXA@public.gmane.org More majordomo info at http://vger.kernel.org/majordomo-info.html ^ permalink raw reply related [flat|nested] 16+ messages in thread
* [PATCH v3 2/2] arm64: dts: rockchip: support the pmu node for rk3399 @ 2016-09-05 18:17 ` Caesar Wang 0 siblings, 0 replies; 16+ messages in thread From: Caesar Wang @ 2016-09-05 18:17 UTC (permalink / raw) To: Heiko Stuebner Cc: linux-rockchip, Douglas Anderson, sonnyrao, linux-arm-kernel, Caesar Wang, Marc Zyngier, devicetree, David Wu, Elaine Zhang, Brian Norris, linux-kernel, Shawn Lin, Will Deacon, Jianqun Xu, Mark Rutland, Rob Herring, Catalin Marinas, Xing Zheng This patch adds to enable the ARM Performance Monitor Units for rk3399. ARM cores often have a PMU for counting cpu and cache events like cache misses and hits. Also, as the Marc posted the patches [0] to support Partitioning per-cpu interrupts. Let's add this patch to match it on rk3399 SoCs. [0]: https://lkml.org/lkml/2016/4/11/182 Signed-off-by: Caesar Wang <wxt@rock-chips.com> Acked-by: Mark Rutland <mark.rutland@arm.com> Cc: Heiko Stuebner <heiko@sntech.de> Cc: Marc Zyngier <marc.zyngier@arm.com> CC: linux-arm-kernel@lists.infradead.org --- Changes in v3: - updated on next kernel(20160905). - add the Mark's ACK for PATCH[2/2]. Changes in v2: - AS Mark comments on https://patchwork.kernel.org/patch/9209369/ remove the interrupt-affinity property, we need depend on Marc' perf code on https://patchwork.kernel.org/patch/9209369/. arch/arm64/boot/dts/rockchip/rk3399.dtsi | 20 ++++++++++++++++++++ 1 file changed, 20 insertions(+) diff --git a/arch/arm64/boot/dts/rockchip/rk3399.dtsi b/arch/arm64/boot/dts/rockchip/rk3399.dtsi index e9e22fe..4e65f3b 100644 --- a/arch/arm64/boot/dts/rockchip/rk3399.dtsi +++ b/arch/arm64/boot/dts/rockchip/rk3399.dtsi @@ -166,6 +166,16 @@ <GIC_PPI 10 IRQ_TYPE_LEVEL_LOW 0>; }; + pmu_a53 { + compatible = "arm,cortex-a53-pmu"; + interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_LOW &part0>; + }; + + pmu_a72 { + compatible = "arm,cortex-a72-pmu"; + interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_LOW &part1>; + }; + xin24m: xin24m { compatible = "fixed-clock"; clock-frequency = <24000000>; @@ -354,6 +364,16 @@ status = "disabled"; }; + ppi-partitions { + part0: interrupt-partition-0 { + affinity = <&cpu_l0 &cpu_l1 &cpu_l2 &cpu_l3>; + }; + + part1: interrupt-partition-1 { + affinity = <&cpu_b0 &cpu_b1>; + }; + }; + i2c1: i2c@ff110000 { compatible = "rockchip,rk3399-i2c"; reg = <0x0 0xff110000 0x0 0x1000>; -- 1.9.1 ^ permalink raw reply related [flat|nested] 16+ messages in thread
* [PATCH v3 2/2] arm64: dts: rockchip: support the pmu node for rk3399 @ 2016-09-05 18:17 ` Caesar Wang 0 siblings, 0 replies; 16+ messages in thread From: Caesar Wang @ 2016-09-05 18:17 UTC (permalink / raw) To: linux-arm-kernel This patch adds to enable the ARM Performance Monitor Units for rk3399. ARM cores often have a PMU for counting cpu and cache events like cache misses and hits. Also, as the Marc posted the patches [0] to support Partitioning per-cpu interrupts. Let's add this patch to match it on rk3399 SoCs. [0]: https://lkml.org/lkml/2016/4/11/182 Signed-off-by: Caesar Wang <wxt@rock-chips.com> Acked-by: Mark Rutland <mark.rutland@arm.com> Cc: Heiko Stuebner <heiko@sntech.de> Cc: Marc Zyngier <marc.zyngier@arm.com> CC: linux-arm-kernel at lists.infradead.org --- Changes in v3: - updated on next kernel(20160905). - add the Mark's ACK for PATCH[2/2]. Changes in v2: - AS Mark comments on https://patchwork.kernel.org/patch/9209369/ remove the interrupt-affinity property, we need depend on Marc' perf code on https://patchwork.kernel.org/patch/9209369/. arch/arm64/boot/dts/rockchip/rk3399.dtsi | 20 ++++++++++++++++++++ 1 file changed, 20 insertions(+) diff --git a/arch/arm64/boot/dts/rockchip/rk3399.dtsi b/arch/arm64/boot/dts/rockchip/rk3399.dtsi index e9e22fe..4e65f3b 100644 --- a/arch/arm64/boot/dts/rockchip/rk3399.dtsi +++ b/arch/arm64/boot/dts/rockchip/rk3399.dtsi @@ -166,6 +166,16 @@ <GIC_PPI 10 IRQ_TYPE_LEVEL_LOW 0>; }; + pmu_a53 { + compatible = "arm,cortex-a53-pmu"; + interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_LOW &part0>; + }; + + pmu_a72 { + compatible = "arm,cortex-a72-pmu"; + interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_LOW &part1>; + }; + xin24m: xin24m { compatible = "fixed-clock"; clock-frequency = <24000000>; @@ -354,6 +364,16 @@ status = "disabled"; }; + ppi-partitions { + part0: interrupt-partition-0 { + affinity = <&cpu_l0 &cpu_l1 &cpu_l2 &cpu_l3>; + }; + + part1: interrupt-partition-1 { + affinity = <&cpu_b0 &cpu_b1>; + }; + }; + i2c1: i2c at ff110000 { compatible = "rockchip,rk3399-i2c"; reg = <0x0 0xff110000 0x0 0x1000>; -- 1.9.1 ^ permalink raw reply related [flat|nested] 16+ messages in thread
* Re: [PATCH v3 2/2] arm64: dts: rockchip: support the pmu node for rk3399 2016-09-05 18:17 ` Caesar Wang @ 2016-09-05 22:27 ` Heiko Stuebner -1 siblings, 0 replies; 16+ messages in thread From: Heiko Stuebner @ 2016-09-05 22:27 UTC (permalink / raw) To: Caesar Wang Cc: linux-rockchip, Douglas Anderson, sonnyrao, linux-arm-kernel, Marc Zyngier, devicetree, David Wu, Elaine Zhang, Brian Norris, linux-kernel, Shawn Lin, Will Deacon, Jianqun Xu, Mark Rutland, Rob Herring, Catalin Marinas, Xing Zheng Am Dienstag, 6. September 2016, 02:17:15 CEST schrieb Caesar Wang: > This patch adds to enable the ARM Performance Monitor Units for rk3399. > ARM cores often have a PMU for counting cpu and cache events like cache > misses and hits. > > Also, as the Marc posted the patches [0] to support Partitioning per-cpu > interrupts. Let's add this patch to match it on rk3399 SoCs. > > [0]: > https://lkml.org/lkml/2016/4/11/182 > > Signed-off-by: Caesar Wang <wxt@rock-chips.com> > Acked-by: Mark Rutland <mark.rutland@arm.com> > Cc: Heiko Stuebner <heiko@sntech.de> > Cc: Marc Zyngier <marc.zyngier@arm.com> > CC: linux-arm-kernel@lists.infradead.org I've applied this one but did some corrections [0]: - ppi-partitions is supposed to be a subnode of the gic, that is why the code also start search for it starting from the gic node - I've moved it - I've renamed the phandles taking part0/part1 from the example feels a bit to generic, so it's now ppi_cluster0 and ppi_cluster1 matching the cpu-clusters I've gave this a spin on my rk3399evb and the ppi-partitions got recognized as well as the pmu instances got created, but please also double check again. Thanks Heiko [0] https://git.kernel.org/cgit/linux/kernel/git/mmind/linux-rockchip.git/ commit/?id=48120b1af6f072bfd6b075bf9be560ad6fda2faa ^ permalink raw reply [flat|nested] 16+ messages in thread
* [PATCH v3 2/2] arm64: dts: rockchip: support the pmu node for rk3399 @ 2016-09-05 22:27 ` Heiko Stuebner 0 siblings, 0 replies; 16+ messages in thread From: Heiko Stuebner @ 2016-09-05 22:27 UTC (permalink / raw) To: linux-arm-kernel Am Dienstag, 6. September 2016, 02:17:15 CEST schrieb Caesar Wang: > This patch adds to enable the ARM Performance Monitor Units for rk3399. > ARM cores often have a PMU for counting cpu and cache events like cache > misses and hits. > > Also, as the Marc posted the patches [0] to support Partitioning per-cpu > interrupts. Let's add this patch to match it on rk3399 SoCs. > > [0]: > https://lkml.org/lkml/2016/4/11/182 > > Signed-off-by: Caesar Wang <wxt@rock-chips.com> > Acked-by: Mark Rutland <mark.rutland@arm.com> > Cc: Heiko Stuebner <heiko@sntech.de> > Cc: Marc Zyngier <marc.zyngier@arm.com> > CC: linux-arm-kernel at lists.infradead.org I've applied this one but did some corrections [0]: - ppi-partitions is supposed to be a subnode of the gic, that is why the code also start search for it starting from the gic node - I've moved it - I've renamed the phandles taking part0/part1 from the example feels a bit to generic, so it's now ppi_cluster0 and ppi_cluster1 matching the cpu-clusters I've gave this a spin on my rk3399evb and the ppi-partitions got recognized as well as the pmu instances got created, but please also double check again. Thanks Heiko [0] https://git.kernel.org/cgit/linux/kernel/git/mmind/linux-rockchip.git/ commit/?id=48120b1af6f072bfd6b075bf9be560ad6fda2faa ^ permalink raw reply [flat|nested] 16+ messages in thread
* Re: [PATCH v3 2/2] arm64: dts: rockchip: support the pmu node for rk3399 2016-09-05 22:27 ` Heiko Stuebner (?) @ 2016-09-05 23:27 ` Caesar Wang -1 siblings, 0 replies; 16+ messages in thread From: Caesar Wang @ 2016-09-05 23:27 UTC (permalink / raw) To: Heiko Stuebner Cc: Caesar Wang, Mark Rutland, devicetree-u79uwXL29TY76Z2rM5mHXA, Brian Norris, Catalin Marinas, Xing Zheng, Marc Zyngier, Jianqun Xu, Shawn Lin, Elaine Zhang, Will Deacon, Douglas Anderson, linux-kernel-u79uwXL29TY76Z2rM5mHXA, linux-rockchip-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r, Rob Herring, David Wu, sonnyrao-F7+t8E8rja9g9hUCZPvPmw, linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r On 2016年09月06日 06:27, Heiko Stuebner wrote: > Am Dienstag, 6. September 2016, 02:17:15 CEST schrieb Caesar Wang: >> This patch adds to enable the ARM Performance Monitor Units for rk3399. >> ARM cores often have a PMU for counting cpu and cache events like cache >> misses and hits. >> >> Also, as the Marc posted the patches [0] to support Partitioning per-cpu >> interrupts. Let's add this patch to match it on rk3399 SoCs. >> >> [0]: >> https://lkml.org/lkml/2016/4/11/182 >> >> Signed-off-by: Caesar Wang <wxt-TNX95d0MmH7DzftRWevZcw@public.gmane.org> >> Acked-by: Mark Rutland <mark.rutland-5wv7dgnIgG8@public.gmane.org> >> Cc: Heiko Stuebner <heiko-4mtYJXux2i+zQB+pC5nmwQ@public.gmane.org> >> Cc: Marc Zyngier <marc.zyngier-5wv7dgnIgG8@public.gmane.org> >> CC: linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r@public.gmane.org > I've applied this one but did some corrections [0]: > > - ppi-partitions is supposed to be a subnode of the gic, that is why the code > also start search for it starting from the gic node - I've moved it > - I've renamed the phandles taking part0/part1 from the example feels a bit to > generic, so it's now ppi_cluster0 and ppi_cluster1 matching the cpu-clusters > > I've gave this a spin on my rk3399evb and the ppi-partitions got recognized > as well as the pmu instances got created, but please also double check again. Yup, thanks the fixes. > > > Thanks > Heiko > > > [0] https://git.kernel.org/cgit/linux/kernel/git/mmind/linux-rockchip.git/ > commit/?id=48120b1af6f072bfd6b075bf9be560ad6fda2faa > > > _______________________________________________ > Linux-rockchip mailing list > Linux-rockchip-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r@public.gmane.org > http://lists.infradead.org/mailman/listinfo/linux-rockchip -- caesar wang | software engineer | wxt-TNX95d0MmH73oGB3hsPCZA@public.gmane.org -- To unsubscribe from this list: send the line "unsubscribe devicetree" in the body of a message to majordomo-u79uwXL29TY76Z2rM5mHXA@public.gmane.org More majordomo info at http://vger.kernel.org/majordomo-info.html ^ permalink raw reply [flat|nested] 16+ messages in thread
* Re: [PATCH v3 2/2] arm64: dts: rockchip: support the pmu node for rk3399 @ 2016-09-05 23:27 ` Caesar Wang 0 siblings, 0 replies; 16+ messages in thread From: Caesar Wang @ 2016-09-05 23:27 UTC (permalink / raw) To: Heiko Stuebner Cc: Caesar Wang, Mark Rutland, devicetree, Brian Norris, Catalin Marinas, Xing Zheng, Marc Zyngier, Jianqun Xu, Shawn Lin, Elaine Zhang, Will Deacon, Douglas Anderson, linux-kernel, linux-rockchip, Rob Herring, David Wu, sonnyrao, linux-arm-kernel On 2016年09月06日 06:27, Heiko Stuebner wrote: > Am Dienstag, 6. September 2016, 02:17:15 CEST schrieb Caesar Wang: >> This patch adds to enable the ARM Performance Monitor Units for rk3399. >> ARM cores often have a PMU for counting cpu and cache events like cache >> misses and hits. >> >> Also, as the Marc posted the patches [0] to support Partitioning per-cpu >> interrupts. Let's add this patch to match it on rk3399 SoCs. >> >> [0]: >> https://lkml.org/lkml/2016/4/11/182 >> >> Signed-off-by: Caesar Wang <wxt@rock-chips.com> >> Acked-by: Mark Rutland <mark.rutland@arm.com> >> Cc: Heiko Stuebner <heiko@sntech.de> >> Cc: Marc Zyngier <marc.zyngier@arm.com> >> CC: linux-arm-kernel@lists.infradead.org > I've applied this one but did some corrections [0]: > > - ppi-partitions is supposed to be a subnode of the gic, that is why the code > also start search for it starting from the gic node - I've moved it > - I've renamed the phandles taking part0/part1 from the example feels a bit to > generic, so it's now ppi_cluster0 and ppi_cluster1 matching the cpu-clusters > > I've gave this a spin on my rk3399evb and the ppi-partitions got recognized > as well as the pmu instances got created, but please also double check again. Yup, thanks the fixes. > > > Thanks > Heiko > > > [0] https://git.kernel.org/cgit/linux/kernel/git/mmind/linux-rockchip.git/ > commit/?id=48120b1af6f072bfd6b075bf9be560ad6fda2faa > > > _______________________________________________ > Linux-rockchip mailing list > Linux-rockchip@lists.infradead.org > http://lists.infradead.org/mailman/listinfo/linux-rockchip -- caesar wang | software engineer | wxt@rock-chip.com ^ permalink raw reply [flat|nested] 16+ messages in thread
* [PATCH v3 2/2] arm64: dts: rockchip: support the pmu node for rk3399 @ 2016-09-05 23:27 ` Caesar Wang 0 siblings, 0 replies; 16+ messages in thread From: Caesar Wang @ 2016-09-05 23:27 UTC (permalink / raw) To: linux-arm-kernel On 2016?09?06? 06:27, Heiko Stuebner wrote: > Am Dienstag, 6. September 2016, 02:17:15 CEST schrieb Caesar Wang: >> This patch adds to enable the ARM Performance Monitor Units for rk3399. >> ARM cores often have a PMU for counting cpu and cache events like cache >> misses and hits. >> >> Also, as the Marc posted the patches [0] to support Partitioning per-cpu >> interrupts. Let's add this patch to match it on rk3399 SoCs. >> >> [0]: >> https://lkml.org/lkml/2016/4/11/182 >> >> Signed-off-by: Caesar Wang <wxt@rock-chips.com> >> Acked-by: Mark Rutland <mark.rutland@arm.com> >> Cc: Heiko Stuebner <heiko@sntech.de> >> Cc: Marc Zyngier <marc.zyngier@arm.com> >> CC: linux-arm-kernel at lists.infradead.org > I've applied this one but did some corrections [0]: > > - ppi-partitions is supposed to be a subnode of the gic, that is why the code > also start search for it starting from the gic node - I've moved it > - I've renamed the phandles taking part0/part1 from the example feels a bit to > generic, so it's now ppi_cluster0 and ppi_cluster1 matching the cpu-clusters > > I've gave this a spin on my rk3399evb and the ppi-partitions got recognized > as well as the pmu instances got created, but please also double check again. Yup, thanks the fixes. > > > Thanks > Heiko > > > [0] https://git.kernel.org/cgit/linux/kernel/git/mmind/linux-rockchip.git/ > commit/?id=48120b1af6f072bfd6b075bf9be560ad6fda2faa > > > _______________________________________________ > Linux-rockchip mailing list > Linux-rockchip at lists.infradead.org > http://lists.infradead.org/mailman/listinfo/linux-rockchip -- caesar wang | software engineer | wxt at rock-chip.com ^ permalink raw reply [flat|nested] 16+ messages in thread
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2016-09-05 18:17 [PATCH v3 0/2] arm64: dts: rockchip: Support PMU for rk3399 SoCs Caesar Wang
2016-09-05 18:17 ` Caesar Wang
2016-09-05 18:17 ` Caesar Wang
2016-09-05 18:17 ` [PATCH v3 1/2] arm64: dts: rockchip: change all interrupts cells for 4 on " Caesar Wang
2016-09-05 18:17 ` Caesar Wang
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2016-09-05 22:20 ` Heiko Stuebner
2016-09-05 22:20 ` Heiko Stuebner
2016-09-05 22:20 ` Heiko Stuebner
[not found] ` <1473099435-28198-1-git-send-email-wxt-TNX95d0MmH7DzftRWevZcw@public.gmane.org>
2016-09-05 18:17 ` [PATCH v3 2/2] arm64: dts: rockchip: support the pmu node for rk3399 Caesar Wang
2016-09-05 18:17 ` Caesar Wang
2016-09-05 18:17 ` Caesar Wang
2016-09-05 22:27 ` Heiko Stuebner
2016-09-05 22:27 ` Heiko Stuebner
2016-09-05 23:27 ` Caesar Wang
2016-09-05 23:27 ` Caesar Wang
2016-09-05 23:27 ` Caesar Wang
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