* [PATCH 1/3] sparc64: recognize and support sparc M8 cpu type
@ 2017-07-20 7:52 Allen Pais
2017-07-20 19:52 ` Sam Ravnborg
` (9 more replies)
0 siblings, 10 replies; 11+ messages in thread
From: Allen Pais @ 2017-07-20 7:52 UTC (permalink / raw)
To: sparclinux
Recognize SPARC-M8 cpu type, hardware caps and cpu
distribution map.
Signed-off-by: Allen Pais <allen.pais@oracle.com>
Signed-off-by: David Aldridge <david.j.aldridge@oracle.com>
---
arch/sparc/include/asm/spitfire.h | 1 +
arch/sparc/kernel/cpu.c | 6 ++++++
arch/sparc/kernel/cpumap.c | 1 +
arch/sparc/kernel/head_64.S | 6 ++++++
arch/sparc/kernel/setup_64.c | 15 +++++++++++++--
arch/sparc/mm/init_64.c | 2 ++
6 files changed, 29 insertions(+), 2 deletions(-)
diff --git a/arch/sparc/include/asm/spitfire.h b/arch/sparc/include/asm/spitfire.h
index 1d8321c..ba3a655 100644
--- a/arch/sparc/include/asm/spitfire.h
+++ b/arch/sparc/include/asm/spitfire.h
@@ -47,6 +47,7 @@
#define SUN4V_CHIP_NIAGARA5 0x05
#define SUN4V_CHIP_SPARC_M6 0x06
#define SUN4V_CHIP_SPARC_M7 0x07
+#define SUN4V_CHIP_SPARC_M8 0x08
#define SUN4V_CHIP_SPARC64X 0x8a
#define SUN4V_CHIP_SPARC_SN 0x8b
#define SUN4V_CHIP_UNKNOWN 0xff
diff --git a/arch/sparc/kernel/cpu.c b/arch/sparc/kernel/cpu.c
index 493e023..ef4f18f 100644
--- a/arch/sparc/kernel/cpu.c
+++ b/arch/sparc/kernel/cpu.c
@@ -506,6 +506,12 @@ static void __init sun4v_cpu_probe(void)
sparc_pmu_type = "sparc-m7";
break;
+ case SUN4V_CHIP_SPARC_M8:
+ sparc_cpu_type = "SPARC-M8";
+ sparc_fpu_type = "SPARC-M8 integrated FPU";
+ sparc_pmu_type = "sparc-m8";
+ break;
+
case SUN4V_CHIP_SPARC_SN:
sparc_cpu_type = "SPARC-SN";
sparc_fpu_type = "SPARC-SN integrated FPU";
diff --git a/arch/sparc/kernel/cpumap.c b/arch/sparc/kernel/cpumap.c
index 45c820e..90d550b 100644
--- a/arch/sparc/kernel/cpumap.c
+++ b/arch/sparc/kernel/cpumap.c
@@ -328,6 +328,7 @@ static int iterate_cpu(struct cpuinfo_tree *t, unsigned int root_index)
case SUN4V_CHIP_NIAGARA5:
case SUN4V_CHIP_SPARC_M6:
case SUN4V_CHIP_SPARC_M7:
+ case SUN4V_CHIP_SPARC_M8:
case SUN4V_CHIP_SPARC_SN:
case SUN4V_CHIP_SPARC64X:
rover_inc_table = niagara_iterate_method;
diff --git a/arch/sparc/kernel/head_64.S b/arch/sparc/kernel/head_64.S
index 41a4073..afcd4ca 100644
--- a/arch/sparc/kernel/head_64.S
+++ b/arch/sparc/kernel/head_64.S
@@ -439,6 +439,9 @@ EXPORT_SYMBOL(sun4v_chip_type)
cmp %g2, '7'
be,pt %xcc, 5f
mov SUN4V_CHIP_SPARC_M7, %g4
+ cmp %g2, '8'
+ be,pt %xcc, 5f
+ mov SUN4V_CHIP_SPARC_M8, %g4
cmp %g2, 'N'
be,pt %xcc, 5f
mov SUN4V_CHIP_SPARC_SN, %g4
@@ -602,6 +605,9 @@ niagara_tlb_fixup:
cmp %g1, SUN4V_CHIP_SPARC_M7
be,pt %xcc, niagara4_patch
nop
+ cmp %g1, SUN4V_CHIP_SPARC_M8
+ be,pt %xcc, niagara4_patch
+ nop
cmp %g1, SUN4V_CHIP_SPARC_SN
be,pt %xcc, niagara4_patch
nop
diff --git a/arch/sparc/kernel/setup_64.c b/arch/sparc/kernel/setup_64.c
index 4d9c3e1..150ee7d 100644
--- a/arch/sparc/kernel/setup_64.c
+++ b/arch/sparc/kernel/setup_64.c
@@ -288,10 +288,17 @@ static void __init sun4v_patch(void)
sun4v_patch_2insn_range(&__sun4v_2insn_patch,
&__sun4v_2insn_patch_end);
- if (sun4v_chip_type = SUN4V_CHIP_SPARC_M7 ||
- sun4v_chip_type = SUN4V_CHIP_SPARC_SN)
+
+ switch (sun4v_chip_type) {
+ case SUN4V_CHIP_SPARC_M7:
+ case SUN4V_CHIP_SPARC_M8:
+ case SUN4V_CHIP_SPARC_SN:
sun_m7_patch_2insn_range(&__sun_m7_2insn_patch,
&__sun_m7_2insn_patch_end);
+ break;
+ default:
+ break;
+ }
sun4v_hvapi_init();
}
@@ -529,6 +536,7 @@ static void __init init_sparc64_elf_hwcap(void)
sun4v_chip_type = SUN4V_CHIP_NIAGARA5 ||
sun4v_chip_type = SUN4V_CHIP_SPARC_M6 ||
sun4v_chip_type = SUN4V_CHIP_SPARC_M7 ||
+ sun4v_chip_type = SUN4V_CHIP_SPARC_M8 ||
sun4v_chip_type = SUN4V_CHIP_SPARC_SN ||
sun4v_chip_type = SUN4V_CHIP_SPARC64X)
cap |= HWCAP_SPARC_BLKINIT;
@@ -538,6 +546,7 @@ static void __init init_sparc64_elf_hwcap(void)
sun4v_chip_type = SUN4V_CHIP_NIAGARA5 ||
sun4v_chip_type = SUN4V_CHIP_SPARC_M6 ||
sun4v_chip_type = SUN4V_CHIP_SPARC_M7 ||
+ sun4v_chip_type = SUN4V_CHIP_SPARC_M8 ||
sun4v_chip_type = SUN4V_CHIP_SPARC_SN ||
sun4v_chip_type = SUN4V_CHIP_SPARC64X)
cap |= HWCAP_SPARC_N2;
@@ -568,6 +577,7 @@ static void __init init_sparc64_elf_hwcap(void)
sun4v_chip_type = SUN4V_CHIP_NIAGARA5 ||
sun4v_chip_type = SUN4V_CHIP_SPARC_M6 ||
sun4v_chip_type = SUN4V_CHIP_SPARC_M7 ||
+ sun4v_chip_type = SUN4V_CHIP_SPARC_M8 ||
sun4v_chip_type = SUN4V_CHIP_SPARC_SN ||
sun4v_chip_type = SUN4V_CHIP_SPARC64X)
cap |= (AV_SPARC_VIS | AV_SPARC_VIS2 |
@@ -578,6 +588,7 @@ static void __init init_sparc64_elf_hwcap(void)
sun4v_chip_type = SUN4V_CHIP_NIAGARA5 ||
sun4v_chip_type = SUN4V_CHIP_SPARC_M6 ||
sun4v_chip_type = SUN4V_CHIP_SPARC_M7 ||
+ sun4v_chip_type = SUN4V_CHIP_SPARC_M8 ||
sun4v_chip_type = SUN4V_CHIP_SPARC_SN ||
sun4v_chip_type = SUN4V_CHIP_SPARC64X)
cap |= (AV_SPARC_VIS3 | AV_SPARC_HPC |
diff --git a/arch/sparc/mm/init_64.c b/arch/sparc/mm/init_64.c
index 3c40ebd..a111625 100644
--- a/arch/sparc/mm/init_64.c
+++ b/arch/sparc/mm/init_64.c
@@ -2138,6 +2138,7 @@ static void __init sun4v_linear_pte_xor_finalize(void)
*/
switch (sun4v_chip_type) {
case SUN4V_CHIP_SPARC_M7:
+ case SUN4V_CHIP_SPARC_M8:
case SUN4V_CHIP_SPARC_SN:
pagecv_flag = 0x00;
break;
@@ -2290,6 +2291,7 @@ void __init paging_init(void)
*/
switch (sun4v_chip_type) {
case SUN4V_CHIP_SPARC_M7:
+ case SUN4V_CHIP_SPARC_M8:
case SUN4V_CHIP_SPARC_SN:
page_cache4v_flag = _PAGE_CP_4V;
break;
--
1.9.1
^ permalink raw reply related [flat|nested] 11+ messages in thread
* Re: [PATCH 1/3] sparc64: recognize and support sparc M8 cpu type
2017-07-20 7:52 [PATCH 1/3] sparc64: recognize and support sparc M8 cpu type Allen Pais
@ 2017-07-20 19:52 ` Sam Ravnborg
2017-07-21 8:37 ` Allen
` (8 subsequent siblings)
9 siblings, 0 replies; 11+ messages in thread
From: Sam Ravnborg @ 2017-07-20 19:52 UTC (permalink / raw)
To: sparclinux
Hi Allen.
On Thu, Jul 20, 2017 at 01:10:35PM +0530, Allen Pais wrote:
> Recognize SPARC-M8 cpu type, hardware caps and cpu
> distribution map.
>
> Signed-off-by: Allen Pais <allen.pais@oracle.com>
> Signed-off-by: David Aldridge <david.j.aldridge@oracle.com>
> ---
> arch/sparc/include/asm/spitfire.h | 1 +
> arch/sparc/kernel/cpu.c | 6 ++++++
> arch/sparc/kernel/cpumap.c | 1 +
> arch/sparc/kernel/head_64.S | 6 ++++++
> arch/sparc/kernel/setup_64.c | 15 +++++++++++++--
> arch/sparc/mm/init_64.c | 2 ++
> 6 files changed, 29 insertions(+), 2 deletions(-)
>
> diff --git a/arch/sparc/include/asm/spitfire.h b/arch/sparc/include/asm/spitfire.h
> index 1d8321c..ba3a655 100644
> --- a/arch/sparc/include/asm/spitfire.h
> +++ b/arch/sparc/include/asm/spitfire.h
> @@ -47,6 +47,7 @@
> #define SUN4V_CHIP_NIAGARA5 0x05
> #define SUN4V_CHIP_SPARC_M6 0x06
> #define SUN4V_CHIP_SPARC_M7 0x07
> +#define SUN4V_CHIP_SPARC_M8 0x08
> #define SUN4V_CHIP_SPARC64X 0x8a
> #define SUN4V_CHIP_SPARC_SN 0x8b
> #define SUN4V_CHIP_UNKNOWN 0xff
> diff --git a/arch/sparc/kernel/cpu.c b/arch/sparc/kernel/cpu.c
> index 493e023..ef4f18f 100644
> --- a/arch/sparc/kernel/cpu.c
> +++ b/arch/sparc/kernel/cpu.c
> @@ -506,6 +506,12 @@ static void __init sun4v_cpu_probe(void)
> sparc_pmu_type = "sparc-m7";
> break;
>
> + case SUN4V_CHIP_SPARC_M8:
> + sparc_cpu_type = "SPARC-M8";
> + sparc_fpu_type = "SPARC-M8 integrated FPU";
> + sparc_pmu_type = "sparc-m8";
> + break;
> +
> case SUN4V_CHIP_SPARC_SN:
> sparc_cpu_type = "SPARC-SN";
> sparc_fpu_type = "SPARC-SN integrated FPU";
> diff --git a/arch/sparc/kernel/cpumap.c b/arch/sparc/kernel/cpumap.c
> index 45c820e..90d550b 100644
> --- a/arch/sparc/kernel/cpumap.c
> +++ b/arch/sparc/kernel/cpumap.c
> @@ -328,6 +328,7 @@ static int iterate_cpu(struct cpuinfo_tree *t, unsigned int root_index)
> case SUN4V_CHIP_NIAGARA5:
> case SUN4V_CHIP_SPARC_M6:
> case SUN4V_CHIP_SPARC_M7:
> + case SUN4V_CHIP_SPARC_M8:
> case SUN4V_CHIP_SPARC_SN:
> case SUN4V_CHIP_SPARC64X:
> rover_inc_table = niagara_iterate_method;
> diff --git a/arch/sparc/kernel/head_64.S b/arch/sparc/kernel/head_64.S
> index 41a4073..afcd4ca 100644
> --- a/arch/sparc/kernel/head_64.S
> +++ b/arch/sparc/kernel/head_64.S
> @@ -439,6 +439,9 @@ EXPORT_SYMBOL(sun4v_chip_type)
> cmp %g2, '7'
> be,pt %xcc, 5f
> mov SUN4V_CHIP_SPARC_M7, %g4
> + cmp %g2, '8'
> + be,pt %xcc, 5f
> + mov SUN4V_CHIP_SPARC_M8, %g4
Could we use this opportunity to create properly named
constants for '7', '8', 'N' etc, rather than harcoding these
in some assembler files.
(Obviously in a separate patch).
Sam
^ permalink raw reply [flat|nested] 11+ messages in thread
* Re: [PATCH 1/3] sparc64: recognize and support sparc M8 cpu type
2017-07-20 7:52 [PATCH 1/3] sparc64: recognize and support sparc M8 cpu type Allen Pais
2017-07-20 19:52 ` Sam Ravnborg
@ 2017-07-21 8:37 ` Allen
2017-07-21 9:33 ` Allen
` (7 subsequent siblings)
9 siblings, 0 replies; 11+ messages in thread
From: Allen @ 2017-07-21 8:37 UTC (permalink / raw)
To: sparclinux
>> index 41a4073..afcd4ca 100644
>> --- a/arch/sparc/kernel/head_64.S
>> +++ b/arch/sparc/kernel/head_64.S
>> @@ -439,6 +439,9 @@ EXPORT_SYMBOL(sun4v_chip_type)
>> cmp %g2, '7'
>> be,pt %xcc, 5f
>> mov SUN4V_CHIP_SPARC_M7, %g4
>> + cmp %g2, '8'
>> + be,pt %xcc, 5f
>> + mov SUN4V_CHIP_SPARC_M8, %g4
>
> Could we use this opportunity to create properly named
> constants for '7', '8', 'N' etc, rather than harcoding these
> in some assembler files.
> (Obviously in a separate patch).
Sure. Will send out V2 with the changes.
- Allen
^ permalink raw reply [flat|nested] 11+ messages in thread
* Re: [PATCH 1/3] sparc64: recognize and support sparc M8 cpu type
2017-07-20 7:52 [PATCH 1/3] sparc64: recognize and support sparc M8 cpu type Allen Pais
2017-07-20 19:52 ` Sam Ravnborg
2017-07-21 8:37 ` Allen
@ 2017-07-21 9:33 ` Allen
2017-07-21 10:46 ` Richard Mortimer
` (6 subsequent siblings)
9 siblings, 0 replies; 11+ messages in thread
From: Allen @ 2017-07-21 9:33 UTC (permalink / raw)
To: sparclinux
Hi Sam,
>> +++ b/arch/sparc/kernel/head_64.S
>> @@ -439,6 +439,9 @@ EXPORT_SYMBOL(sun4v_chip_type)
>> cmp %g2, '7'
>> be,pt %xcc, 5f
>> mov SUN4V_CHIP_SPARC_M7, %g4
>> + cmp %g2, '8'
>> + be,pt %xcc, 5f
>> + mov SUN4V_CHIP_SPARC_M8, %g4
>
> Could we use this opportunity to create properly named
> constants for '7', '8', 'N' etc, rather than harcoding these
> in some assembler files.
> (Obviously in a separate patch).
Would this work?
diff --git a/arch/sparc/include/asm/spitfire.h
b/arch/sparc/include/asm/spitfire.h
index ba3a655..c23b24e 100644
--- a/arch/sparc/include/asm/spitfire.h
+++ b/arch/sparc/include/asm/spitfire.h
@@ -52,6 +52,17 @@
#define SUN4V_CHIP_SPARC_SN 0x8b
#define SUN4V_CHIP_UNKNOWN 0xff
+/* CPU Constants */
+#define NIAGARA1 1
+#define NIAGARA2 2
+#define NIAGARA3 3
+#define NIAGARA4 4
+#define NIAGARA5 5
+#define M6 6
+#define M7 7
+#define M8 8
+#define SONOMA1 ('N')
+
#ifndef __ASSEMBLY__
enum ultra_tlb_layout {
diff --git a/arch/sparc/kernel/head_64.S b/arch/sparc/kernel/head_64.S
index afcd4ca..46c12d6 100644
--- a/arch/sparc/kernel/head_64.S
+++ b/arch/sparc/kernel/head_64.S
@@ -424,25 +424,25 @@ EXPORT_SYMBOL(sun4v_chip_type)
nop
70: ldub [%g1 + 7], %g2
- cmp %g2, '3'
+ cmp %g2, NIAGARA3
be,pt %xcc, 5f
mov SUN4V_CHIP_NIAGARA3, %g4
- cmp %g2, '4'
+ cmp %g2, NIAGARA4
be,pt %xcc, 5f
mov SUN4V_CHIP_NIAGARA4, %g4
- cmp %g2, '5'
+ cmp %g2, NIAGARA5
be,pt %xcc, 5f
mov SUN4V_CHIP_NIAGARA5, %g4
- cmp %g2, '6'
+ cmp %g2, M6
be,pt %xcc, 5f
mov SUN4V_CHIP_SPARC_M6, %g4
- cmp %g2, '7'
+ cmp %g2, M7
be,pt %xcc, 5f
mov SUN4V_CHIP_SPARC_M7, %g4
- cmp %g2, '8'
+ cmp %g2, M8
be,pt %xcc, 5f
mov SUN4V_CHIP_SPARC_M8, %g4
- cmp %g2, 'N'
+ cmp %g2, SONOMA1
be,pt %xcc, 5f
mov SUN4V_CHIP_SPARC_SN, %g4
ba,pt %xcc, 49f
@@ -451,10 +451,10 @@ EXPORT_SYMBOL(sun4v_chip_type)
91: sethi %hi(prom_cpu_compatible), %g1
or %g1, %lo(prom_cpu_compatible), %g1
ldub [%g1 + 17], %g2
- cmp %g2, '1'
+ cmp %g2, NIAGARA1
be,pt %xcc, 5f
mov SUN4V_CHIP_NIAGARA1, %g4
- cmp %g2, '2'
+ cmp %g2, NIAGARA2
be,pt %xcc, 5f
mov SUN4V_CHIP_NIAGARA2, %g4
- Allen
^ permalink raw reply related [flat|nested] 11+ messages in thread
* Re: [PATCH 1/3] sparc64: recognize and support sparc M8 cpu type
2017-07-20 7:52 [PATCH 1/3] sparc64: recognize and support sparc M8 cpu type Allen Pais
` (2 preceding siblings ...)
2017-07-21 9:33 ` Allen
@ 2017-07-21 10:46 ` Richard Mortimer
2017-07-21 10:55 ` Allen
` (5 subsequent siblings)
9 siblings, 0 replies; 11+ messages in thread
From: Richard Mortimer @ 2017-07-21 10:46 UTC (permalink / raw)
To: sparclinux
Hi Allen,
On 21/07/2017 10:21, Allen wrote:
>
> Hi Sam,
>
>>> +++ b/arch/sparc/kernel/head_64.S
>>> @@ -439,6 +439,9 @@ EXPORT_SYMBOL(sun4v_chip_type)
>>> cmp %g2, '7'
>>> be,pt %xcc, 5f
>>> mov SUN4V_CHIP_SPARC_M7, %g4
>>> + cmp %g2, '8'
>>> + be,pt %xcc, 5f
>>> + mov SUN4V_CHIP_SPARC_M8, %g4
>>
>> Could we use this opportunity to create properly named
>> constants for '7', '8', 'N' etc, rather than harcoding these
>> in some assembler files.
>> (Obviously in a separate patch).
>
> Would this work?
>
> diff --git a/arch/sparc/include/asm/spitfire.h
> b/arch/sparc/include/asm/spitfire.h
> index ba3a655..c23b24e 100644
> --- a/arch/sparc/include/asm/spitfire.h
> +++ b/arch/sparc/include/asm/spitfire.h
> @@ -52,6 +52,17 @@
> #define SUN4V_CHIP_SPARC_SN 0x8b
> #define SUN4V_CHIP_UNKNOWN 0xff
>
> +/* CPU Constants */
> +#define NIAGARA1 1
> +#define NIAGARA2 2
> +#define NIAGARA3 3
> +#define NIAGARA4 4
> +#define NIAGARA5 5
> +#define M6 6
> +#define M7 7
> +#define M8 8
All of the above were character constants in the original.
Regards
Richard
> +#define SONOMA1 ('N')
> +
> #ifndef __ASSEMBLY__
>
> enum ultra_tlb_layout {
> diff --git a/arch/sparc/kernel/head_64.S b/arch/sparc/kernel/head_64.S
> index afcd4ca..46c12d6 100644
> --- a/arch/sparc/kernel/head_64.S
> +++ b/arch/sparc/kernel/head_64.S
> @@ -424,25 +424,25 @@ EXPORT_SYMBOL(sun4v_chip_type)
> nop
>
> 70: ldub [%g1 + 7], %g2
> - cmp %g2, '3'
> + cmp %g2, NIAGARA3
> be,pt %xcc, 5f
> mov SUN4V_CHIP_NIAGARA3, %g4
> - cmp %g2, '4'
> + cmp %g2, NIAGARA4
> be,pt %xcc, 5f
> mov SUN4V_CHIP_NIAGARA4, %g4
> - cmp %g2, '5'
> + cmp %g2, NIAGARA5
> be,pt %xcc, 5f
> mov SUN4V_CHIP_NIAGARA5, %g4
> - cmp %g2, '6'
> + cmp %g2, M6
> be,pt %xcc, 5f
> mov SUN4V_CHIP_SPARC_M6, %g4
> - cmp %g2, '7'
> + cmp %g2, M7
> be,pt %xcc, 5f
> mov SUN4V_CHIP_SPARC_M7, %g4
> - cmp %g2, '8'
> + cmp %g2, M8
> be,pt %xcc, 5f
> mov SUN4V_CHIP_SPARC_M8, %g4
> - cmp %g2, 'N'
> + cmp %g2, SONOMA1
> be,pt %xcc, 5f
> mov SUN4V_CHIP_SPARC_SN, %g4
> ba,pt %xcc, 49f
> @@ -451,10 +451,10 @@ EXPORT_SYMBOL(sun4v_chip_type)
> 91: sethi %hi(prom_cpu_compatible), %g1
> or %g1, %lo(prom_cpu_compatible), %g1
> ldub [%g1 + 17], %g2
> - cmp %g2, '1'
> + cmp %g2, NIAGARA1
> be,pt %xcc, 5f
> mov SUN4V_CHIP_NIAGARA1, %g4
> - cmp %g2, '2'
> + cmp %g2, NIAGARA2
> be,pt %xcc, 5f
> mov SUN4V_CHIP_NIAGARA2, %g4
>
> - Allen
> --
> To unsubscribe from this list: send the line "unsubscribe sparclinux" in
> the body of a message to majordomo@vger.kernel.org
> More majordomo info at http://vger.kernel.org/majordomo-info.html
^ permalink raw reply [flat|nested] 11+ messages in thread
* Re: [PATCH 1/3] sparc64: recognize and support sparc M8 cpu type
2017-07-20 7:52 [PATCH 1/3] sparc64: recognize and support sparc M8 cpu type Allen Pais
` (3 preceding siblings ...)
2017-07-21 10:46 ` Richard Mortimer
@ 2017-07-21 10:55 ` Allen
2017-07-21 16:56 ` Sam Ravnborg
` (4 subsequent siblings)
9 siblings, 0 replies; 11+ messages in thread
From: Allen @ 2017-07-21 10:55 UTC (permalink / raw)
To: sparclinux
Hi Richard,
>> +/* CPU Constants */
>> +#define NIAGARA1 1
>> +#define NIAGARA2 2
>> +#define NIAGARA3 3
>> +#define NIAGARA4 4
>> +#define NIAGARA5 5
>> +#define M6 6
>> +#define M7 7
>> +#define M8 8
> All of the above were character constants in the original.
>
Yep. It was just a rough diff for RFC. If the thought is fine, I'll
clean and send out a patch.
- Allen
^ permalink raw reply [flat|nested] 11+ messages in thread
* Re: [PATCH 1/3] sparc64: recognize and support sparc M8 cpu type
2017-07-20 7:52 [PATCH 1/3] sparc64: recognize and support sparc M8 cpu type Allen Pais
` (4 preceding siblings ...)
2017-07-21 10:55 ` Allen
@ 2017-07-21 16:56 ` Sam Ravnborg
2017-07-21 19:11 ` David Miller
` (3 subsequent siblings)
9 siblings, 0 replies; 11+ messages in thread
From: Sam Ravnborg @ 2017-07-21 16:56 UTC (permalink / raw)
To: sparclinux
On Fri, Jul 21, 2017 at 02:51:59PM +0530, Allen wrote:
>
> Hi Sam,
>
> >>+++ b/arch/sparc/kernel/head_64.S
> >>@@ -439,6 +439,9 @@ EXPORT_SYMBOL(sun4v_chip_type)
> >> cmp %g2, '7'
> >> be,pt %xcc, 5f
> >> mov SUN4V_CHIP_SPARC_M7, %g4
> >>+ cmp %g2, '8'
> >>+ be,pt %xcc, 5f
> >>+ mov SUN4V_CHIP_SPARC_M8, %g4
> >
> >Could we use this opportunity to create properly named
> >constants for '7', '8', 'N' etc, rather than harcoding these
> >in some assembler files.
> >(Obviously in a separate patch).
>
> Would this work?
It is way better than the hardcoded values.
If the vales have any sort of name in the sparc specs
the values shall be prefixed with this.
Otherwise something like
CPU_ID_xxx
And maybe add an intro comment like this:
/* following CPU_ID_xxx constants are used to identify the
* CPU type in the setup phase (see xxx.S)
*/
(As character constants, but that part is obvious).
Sam
^ permalink raw reply [flat|nested] 11+ messages in thread
* Re: [PATCH 1/3] sparc64: recognize and support sparc M8 cpu type
2017-07-20 7:52 [PATCH 1/3] sparc64: recognize and support sparc M8 cpu type Allen Pais
` (5 preceding siblings ...)
2017-07-21 16:56 ` Sam Ravnborg
@ 2017-07-21 19:11 ` David Miller
2017-07-22 8:56 ` Allen
` (2 subsequent siblings)
9 siblings, 0 replies; 11+ messages in thread
From: David Miller @ 2017-07-21 19:11 UTC (permalink / raw)
To: sparclinux
From: Allen <allen.pais@oracle.com>
Date: Fri, 21 Jul 2017 14:51:59 +0530
>
> Hi Sam,
>
>>> +++ b/arch/sparc/kernel/head_64.S
>>> @@ -439,6 +439,9 @@ EXPORT_SYMBOL(sun4v_chip_type)
>>> cmp %g2, '7'
>>> be,pt %xcc, 5f
>>> mov SUN4V_CHIP_SPARC_M7, %g4
>>> + cmp %g2, '8'
>>> + be,pt %xcc, 5f
>>> + mov SUN4V_CHIP_SPARC_M8, %g4
>>
>> Could we use this opportunity to create properly named
>> constants for '7', '8', 'N' etc, rather than harcoding these
>> in some assembler files.
>> (Obviously in a separate patch).
>
> Would this work?
That won't even boot.
You're changing an ASCII character '?' value into a raw
constant.
^ permalink raw reply [flat|nested] 11+ messages in thread
* Re: [PATCH 1/3] sparc64: recognize and support sparc M8 cpu type
2017-07-20 7:52 [PATCH 1/3] sparc64: recognize and support sparc M8 cpu type Allen Pais
` (6 preceding siblings ...)
2017-07-21 19:11 ` David Miller
@ 2017-07-22 8:56 ` Allen
2017-07-22 9:25 ` Sam Ravnborg
2017-07-23 6:35 ` David Miller
9 siblings, 0 replies; 11+ messages in thread
From: Allen @ 2017-07-22 8:56 UTC (permalink / raw)
To: sparclinux
Sam/David,
>
> It is way better than the hardcoded values.
> If the vales have any sort of name in the sparc specs
> the values shall be prefixed with this.
> Otherwise something like
> CPU_ID_xxx
>
> And maybe add an intro comment like this:
> /* following CPU_ID_xxx constants are used to identify the
> * CPU type in the setup phase (see xxx.S)
> */
>
Here's a quick diff. Let me know if this looks good to you guys. I'll
send out the patch. I have tested this on a T4.
diff --git a/arch/sparc/include/asm/spitfire.h
b/arch/sparc/include/asm/spitfire.h
index 1d8321c..1b1286d 100644
--- a/arch/sparc/include/asm/spitfire.h
+++ b/arch/sparc/include/asm/spitfire.h
@@ -47,10 +47,26 @@
+/*
+ * The following CPU_ID_xxx constants are used
+ * to identify the CPU type in the setup phase
+ * (see head_64.S)
+ */
+#define CPU_ID_NIAGARA1 ('1')
+#define CPU_ID_NIAGARA2 ('2')
+#define CPU_ID_NIAGARA3 ('3')
+#define CPU_ID_NIAGARA4 ('4')
+#define CPU_ID_NIAGARA5 ('5')
+#define CPU_ID_M6 ('6')
+#define CPU_ID_M7 ('7')
+#define CPU_ID_M8 ('8')
+#define CPU_ID_SONOMA1 ('N')
+
diff --git a/arch/sparc/kernel/head_64.S b/arch/sparc/kernel/head_64.S
index 41a4073..78e0211 100644
--- a/arch/sparc/kernel/head_64.S
+++ b/arch/sparc/kernel/head_64.S
@@ -424,22 +424,25 @@ EXPORT_SYMBOL(sun4v_chip_type)
nop
70: ldub [%g1 + 7], %g2
- cmp %g2, '3'
+ cmp %g2, CPU_ID_NIAGARA3
be,pt %xcc, 5f
mov SUN4V_CHIP_NIAGARA3, %g4
- cmp %g2, '4'
+ cmp %g2, CPU_ID_NIAGARA4
be,pt %xcc, 5f
mov SUN4V_CHIP_NIAGARA4, %g4
- cmp %g2, '5'
+ cmp %g2, CPU_ID_NIAGARA5
be,pt %xcc, 5f
mov SUN4V_CHIP_NIAGARA5, %g4
- cmp %g2, '6'
+ cmp %g2, CPU_ID_M6
be,pt %xcc, 5f
mov SUN4V_CHIP_SPARC_M6, %g4
- cmp %g2, '7'
+ cmp %g2, CPU_ID_M7
be,pt %xcc, 5f
mov SUN4V_CHIP_SPARC_M7, %g4
- cmp %g2, '8'
+ cmp %g2, CPU_ID_M8
be,pt %xcc, 5f
mov SUN4V_CHIP_SPARC_M8, %g4
- cmp %g2, 'N'
+ cmp %g2, CPU_ID_SONOMA1
be,pt %xcc, 5f
mov SUN4V_CHIP_SPARC_SN, %g4
ba,pt %xcc, 49f
^ permalink raw reply related [flat|nested] 11+ messages in thread
* Re: [PATCH 1/3] sparc64: recognize and support sparc M8 cpu type
2017-07-20 7:52 [PATCH 1/3] sparc64: recognize and support sparc M8 cpu type Allen Pais
` (7 preceding siblings ...)
2017-07-22 8:56 ` Allen
@ 2017-07-22 9:25 ` Sam Ravnborg
2017-07-23 6:35 ` David Miller
9 siblings, 0 replies; 11+ messages in thread
From: Sam Ravnborg @ 2017-07-22 9:25 UTC (permalink / raw)
To: sparclinux
On Sat, Jul 22, 2017 at 02:26:25PM +0530, Allen wrote:
> Sam/David,
> >
> >It is way better than the hardcoded values.
> >If the vales have any sort of name in the sparc specs
> >the values shall be prefixed with this.
> >Otherwise something like
> >CPU_ID_xxx
> >
> >And maybe add an intro comment like this:
> >/* following CPU_ID_xxx constants are used to identify the
> > * CPU type in the setup phase (see xxx.S)
> >*/
> >
>
> Here's a quick diff. Let me know if this looks good to you guys.
> I'll send out the patch. I have tested this on a T4.
Acked-by: Sam Ravnborg <sam@ravnborg.org>
^ permalink raw reply [flat|nested] 11+ messages in thread
* Re: [PATCH 1/3] sparc64: recognize and support sparc M8 cpu type
2017-07-20 7:52 [PATCH 1/3] sparc64: recognize and support sparc M8 cpu type Allen Pais
` (8 preceding siblings ...)
2017-07-22 9:25 ` Sam Ravnborg
@ 2017-07-23 6:35 ` David Miller
9 siblings, 0 replies; 11+ messages in thread
From: David Miller @ 2017-07-23 6:35 UTC (permalink / raw)
To: sparclinux
From: Allen <allen.pais@oracle.com>
Date: Sat, 22 Jul 2017 14:26:25 +0530
> Sam/David,
>>
>> It is way better than the hardcoded values.
>> If the vales have any sort of name in the sparc specs
>> the values shall be prefixed with this.
>> Otherwise something like
>> CPU_ID_xxx
>>
>> And maybe add an intro comment like this:
>> /* following CPU_ID_xxx constants are used to identify the
>> * CPU type in the setup phase (see xxx.S)
>> */
>>
>
> Here's a quick diff. Let me know if this looks good to you guys. I'll
> send out the patch. I have tested this on a T4.
Acked-by: David S. Miller <davem@davemloft.net>
^ permalink raw reply [flat|nested] 11+ messages in thread
end of thread, other threads:[~2017-07-23 6:35 UTC | newest]
Thread overview: 11+ messages (download: mbox.gz follow: Atom feed
-- links below jump to the message on this page --
2017-07-20 7:52 [PATCH 1/3] sparc64: recognize and support sparc M8 cpu type Allen Pais
2017-07-20 19:52 ` Sam Ravnborg
2017-07-21 8:37 ` Allen
2017-07-21 9:33 ` Allen
2017-07-21 10:46 ` Richard Mortimer
2017-07-21 10:55 ` Allen
2017-07-21 16:56 ` Sam Ravnborg
2017-07-21 19:11 ` David Miller
2017-07-22 8:56 ` Allen
2017-07-22 9:25 ` Sam Ravnborg
2017-07-23 6:35 ` David Miller
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