Re: [RFC PATCH 04/28] target/ppc: Move vector merge instructions to decodetree

[Nikhil Kumar Singh <nikhilks@linux.ibm.com>]

Reviewed-by: Nikhil Kumar Singh <nikhilks@linux.ibm.com>

Thanks,
~ Nikhil

On 20/05/26 21:37, Chinmay Rath wrote:
> From: Aboorva Devarajan <aboorvad@linux.ibm.com>
>
> Move below instructions to decodetree specification:
>
>          vmrg{hb, hh, hw, lb, lh, lw}           : VX-form
>
> The individual gen_vmrg* functions generated by GEN_VXFORM are
> replaced by a shared do_vmrg() helper dispatching to the existing
> gen_helper_VMRG* TCG helpers via the TRANS_FLAGS() macro, which
> also handles the ALTIVEC facility check.
>
> The changes were verified by validating that the tcg ops generated by
> those instructions remain the same, which were captured with the '-d
> in_asm,op' flag.
>
> Signed-off-by: Aboorva Devarajan <aboorvad@linux.ibm.com>
> Signed-off-by: Chinmay Rath <rathc@linux.ibm.com>
> ---
>   target/ppc/helper.h                 | 12 ++++++------
>   target/ppc/insn32.decode            |  9 +++++++++
>   target/ppc/int_helper.c             | 12 ++++++------
>   target/ppc/translate/vmx-impl.c.inc | 25 +++++++++++++++++++------
>   target/ppc/translate/vmx-ops.c.inc  |  6 ------
>   5 files changed, 40 insertions(+), 24 deletions(-)
>
> diff --git a/target/ppc/helper.h b/target/ppc/helper.h
> index 37803ebb17..d23260ddd0 100644
> --- a/target/ppc/helper.h
> +++ b/target/ppc/helper.h
> @@ -174,12 +174,12 @@ DEF_HELPER_4(vcmpeqfp_dot, void, env, avr, avr, avr)
>   DEF_HELPER_4(vcmpgefp_dot, void, env, avr, avr, avr)
>   DEF_HELPER_4(vcmpgtfp_dot, void, env, avr, avr, avr)
>   DEF_HELPER_4(vcmpbfp_dot, void, env, avr, avr, avr)
> -DEF_HELPER_FLAGS_3(vmrglb, TCG_CALL_NO_RWG, void, avr, avr, avr)
> -DEF_HELPER_FLAGS_3(vmrglh, TCG_CALL_NO_RWG, void, avr, avr, avr)
> -DEF_HELPER_FLAGS_3(vmrglw, TCG_CALL_NO_RWG, void, avr, avr, avr)
> -DEF_HELPER_FLAGS_3(vmrghb, TCG_CALL_NO_RWG, void, avr, avr, avr)
> -DEF_HELPER_FLAGS_3(vmrghh, TCG_CALL_NO_RWG, void, avr, avr, avr)
> -DEF_HELPER_FLAGS_3(vmrghw, TCG_CALL_NO_RWG, void, avr, avr, avr)
> +DEF_HELPER_FLAGS_3(VMRGLB, TCG_CALL_NO_RWG, void, avr, avr, avr)
> +DEF_HELPER_FLAGS_3(VMRGLH, TCG_CALL_NO_RWG, void, avr, avr, avr)
> +DEF_HELPER_FLAGS_3(VMRGLW, TCG_CALL_NO_RWG, void, avr, avr, avr)
> +DEF_HELPER_FLAGS_3(VMRGHB, TCG_CALL_NO_RWG, void, avr, avr, avr)
> +DEF_HELPER_FLAGS_3(VMRGHH, TCG_CALL_NO_RWG, void, avr, avr, avr)
> +DEF_HELPER_FLAGS_3(VMRGHW, TCG_CALL_NO_RWG, void, avr, avr, avr)
>   DEF_HELPER_FLAGS_3(VMULESB, TCG_CALL_NO_RWG, void, avr, avr, avr)
>   DEF_HELPER_FLAGS_3(VMULESH, TCG_CALL_NO_RWG, void, avr, avr, avr)
>   DEF_HELPER_FLAGS_3(VMULESW, TCG_CALL_NO_RWG, void, avr, avr, avr)
> diff --git a/target/ppc/insn32.decode b/target/ppc/insn32.decode
> index 0fbabefba9..d9cc191de5 100644
> --- a/target/ppc/insn32.decode
> +++ b/target/ppc/insn32.decode
> @@ -795,6 +795,15 @@ VNOR            000100 ..... ..... ..... 10100000100    @VX
>   VXOR            000100 ..... ..... ..... 10011000100    @VX
>   VEQV            000100 ..... ..... ..... 11010000100    @VX
>   
> +## Vector Merge Instructions
> +
> +VMRGHB          000100 ..... ..... ..... 00000001100    @VX
> +VMRGHH          000100 ..... ..... ..... 00001001100    @VX
> +VMRGHW          000100 ..... ..... ..... 00010001100    @VX
> +VMRGLB          000100 ..... ..... ..... 00100001100    @VX
> +VMRGLH          000100 ..... ..... ..... 00101001100    @VX
> +VMRGLW          000100 ..... ..... ..... 00110001100    @VX
> +
>   ## Vector Integer Average Instructions
>   
>   VAVGSB          000100 ..... ..... ..... 10100000010    @VX
> diff --git a/target/ppc/int_helper.c b/target/ppc/int_helper.c
> index ef4b2e75d6..a3adf746bd 100644
> --- a/target/ppc/int_helper.c
> +++ b/target/ppc/int_helper.c
> @@ -950,7 +950,7 @@ void helper_VMLADDUHM(ppc_avr_t *r, ppc_avr_t *a, ppc_avr_t *b, ppc_avr_t *c,
>   }
>   
>   #define VMRG_DO(name, element, access, ofs)                                  \
> -    void helper_v##name(ppc_avr_t *r, ppc_avr_t *a, ppc_avr_t *b)            \
> +    void helper_V##name(ppc_avr_t *r, ppc_avr_t *a, ppc_avr_t *b)            \
>       {                                                                        \
>           ppc_avr_t result;                                                    \
>           int i, half = ARRAY_SIZE(r->element) / 2;                            \
> @@ -963,11 +963,11 @@ void helper_VMLADDUHM(ppc_avr_t *r, ppc_avr_t *a, ppc_avr_t *b, ppc_avr_t *c,
>       }
>   
>   #define VMRG(suffix, element, access)          \
> -    VMRG_DO(mrgl##suffix, element, access, half)   \
> -    VMRG_DO(mrgh##suffix, element, access, 0)
> -VMRG(b, u8, VsrB)
> -VMRG(h, u16, VsrH)
> -VMRG(w, u32, VsrW)
> +    VMRG_DO(MRGL##suffix, element, access, half)   \
> +    VMRG_DO(MRGH##suffix, element, access, 0)
> +VMRG(B, u8, VsrB)
> +VMRG(H, u16, VsrH)
> +VMRG(W, u32, VsrW)
>   #undef VMRG_DO
>   #undef VMRG
>   
> diff --git a/target/ppc/translate/vmx-impl.c.inc b/target/ppc/translate/vmx-impl.c.inc
> index 92d6e8c603..00b359f031 100644
> --- a/target/ppc/translate/vmx-impl.c.inc
> +++ b/target/ppc/translate/vmx-impl.c.inc
> @@ -350,12 +350,25 @@ GEN_VXFORM_V(vsububm, MO_8, tcg_gen_gvec_sub, 0, 16);
>   GEN_VXFORM_V(vsubuhm, MO_16, tcg_gen_gvec_sub, 0, 17);
>   GEN_VXFORM_V(vsubuwm, MO_32, tcg_gen_gvec_sub, 0, 18);
>   GEN_VXFORM_V(vsubudm, MO_64, tcg_gen_gvec_sub, 0, 19);
> -GEN_VXFORM(vmrghb, 6, 0);
> -GEN_VXFORM(vmrghh, 6, 1);
> -GEN_VXFORM(vmrghw, 6, 2);
> -GEN_VXFORM(vmrglb, 6, 4);
> -GEN_VXFORM(vmrglh, 6, 5);
> -GEN_VXFORM(vmrglw, 6, 6);
> +
> +static bool do_vmrg(DisasContext *ctx, arg_VX *a,
> +                    void (*helper)(TCGv_ptr, TCGv_ptr, TCGv_ptr))
> +{
> +    TCGv_ptr ra, rb, rd;
> +    REQUIRE_VECTOR(ctx);
> +    ra = gen_avr_ptr(a->vra);
> +    rb = gen_avr_ptr(a->vrb);
> +    rd = gen_avr_ptr(a->vrt);
> +    helper(rd, ra, rb);
> +    return true;
> +}
> +
> +TRANS_FLAGS(ALTIVEC, VMRGHB, do_vmrg, gen_helper_VMRGHB);
> +TRANS_FLAGS(ALTIVEC, VMRGHH, do_vmrg, gen_helper_VMRGHH);
> +TRANS_FLAGS(ALTIVEC, VMRGHW, do_vmrg, gen_helper_VMRGHW);
> +TRANS_FLAGS(ALTIVEC, VMRGLB, do_vmrg, gen_helper_VMRGLB);
> +TRANS_FLAGS(ALTIVEC, VMRGLH, do_vmrg, gen_helper_VMRGLH);
> +TRANS_FLAGS(ALTIVEC, VMRGLW, do_vmrg, gen_helper_VMRGLW);
>   
>   static void trans_vmrgew(DisasContext *ctx)
>   {
> diff --git a/target/ppc/translate/vmx-ops.c.inc b/target/ppc/translate/vmx-ops.c.inc
> index e28958a126..b8f77d3d2c 100644
> --- a/target/ppc/translate/vmx-ops.c.inc
> +++ b/target/ppc/translate/vmx-ops.c.inc
> @@ -33,12 +33,6 @@ GEN_VXFORM_DUAL(vsubuhm, bcdsub, 0, 17, PPC_ALTIVEC, PPC_NONE),
>   GEN_VXFORM_DUAL(vsubuwm, bcdus, 0, 18, PPC_ALTIVEC, PPC2_ISA300),
>   GEN_VXFORM_DUAL(vsubudm, bcds, 0, 19, PPC2_ALTIVEC_207, PPC2_ISA300),
>   GEN_VXFORM_300(bcds, 0, 27),
> -GEN_VXFORM(vmrghb, 6, 0),
> -GEN_VXFORM(vmrghh, 6, 1),
> -GEN_VXFORM(vmrghw, 6, 2),
> -GEN_VXFORM(vmrglb, 6, 4),
> -GEN_VXFORM(vmrglh, 6, 5),
> -GEN_VXFORM(vmrglw, 6, 6),
>   GEN_VXFORM_300(vextublx, 6, 24),
>   GEN_VXFORM_300(vextuhlx, 6, 25),
>   GEN_VXFORM_DUAL(vmrgow, vextuwlx, 6, 26, PPC_NONE, PPC2_ALTIVEC_207),