From: Nikhil Kumar Singh <nikhilks@linux.ibm.com>
To: Chinmay Rath <rathc@linux.ibm.com>,
qemu-devel@nongnu.org, qemu-ppc@nongnu.org, npiggin@gmail.com,
harshpb@linux.ibm.com, richard.henderson@linaro.org,
peter.maydell@linaro.org, stefanha@redhat.com
Cc: milesg@linux.ibm.com, vishalc@linux.ibm.com, tshah@linux.ibm.com,
shivangu@linux.ibm.com, ojaswin@linux.ibm.com,
aboorvad@linux.ibm.com, amachhiw@linux.ibm.com, sv@linux.ibm.com,
shivani@linux.ibm.com, mkchauras@gmail.com, uverma@linux.ibm.com
Subject: Re: [RFC PATCH 12/28] target/ppc: Move GPR atomic load/store instructions to decodetree
Date: Tue, 7 Jul 2026 10:25:59 +0530 [thread overview]
Message-ID: <a6deadff-708a-40ed-8e5a-fb8b332a64c9@linux.ibm.com> (raw)
In-Reply-To: <20260520160728.2283628-13-rathc@linux.ibm.com>
Reviewed-by: Nikhil Kumar Singh <nikhilks@linux.ibm.com>
Thanks,
~ Nikhil
On 20/05/26 21:37, Chinmay Rath wrote:
> From: Aboorva Devarajan <aboorvad@linux.ibm.com>
>
> Move below instructions to decodetree specification:
>
> lwat, stwat : X-form (word atomic, ISA 3.0)
> ldat, stdat : X-form (doubleword atomic, ISA 3.0)
>
> The legacy gen_ld_atomic()/gen_st_atomic() functions that read register
> fields and the function code from ctx->opcode are replaced by new
> do_ld_atomic()/do_st_atomic() helpers in fixedpoint-impl.c.inc that
> use the pre-extracted decodetree argument fields (a->rt, a->ra, a->rb)
> directly. The RB field carries the Function Code (FC) selecting the
> atomic operation.
>
> gen_fetch_inc_conditional() is similarly moved and refactored to accept
> the destination register number as an explicit parameter instead of
> extracting it from ctx->opcode.
>
> Checked with '-d in_asm,op'. The printed TCG ops may differ from the
> pre-refactor log because EA now uses do_ea_calc(ctx, ra, 0), which lowers
> as GPR[ra] + 0 (then narrow in 32-bit mode) instead of mov/ext32u from ra
> alone.
>
> Signed-off-by: Aboorva Devarajan <aboorvad@linux.ibm.com>
> Signed-off-by: Chinmay Rath <rathc@linux.ibm.com>
> ---
> target/ppc/insn32.decode | 7 +
> target/ppc/translate.c | 212 --------------------
> target/ppc/translate/fixedpoint-impl.c.inc | 215 +++++++++++++++++++++
> 3 files changed, 222 insertions(+), 212 deletions(-)
>
> diff --git a/target/ppc/insn32.decode b/target/ppc/insn32.decode
> index 4a28fad64b..f35f7113a0 100644
> --- a/target/ppc/insn32.decode
> +++ b/target/ppc/insn32.decode
> @@ -343,6 +343,13 @@ LSKU 111010 ..... ..... ............. 0 11 @DD
> LCXU 111010 ..... ..... ............. 1 11 @DD
>
>
> +### Fixed-Point Atomic Load/Store Instructions
> +
> +LWAT 011111 ..... ..... ..... 1001000110 - @X
> +STWAT 011111 ..... ..... ..... 1011000110 - @X
> +LDAT 011111 ..... ..... ..... 1001100110 - @X
> +STDAT 011111 ..... ..... ..... 1011100110 - @X
> +
> ### Fixed-Point Store Instructions
>
> STB 100110 ..... ..... ................ @D
> diff --git a/target/ppc/translate.c b/target/ppc/translate.c
> index 7bfbba85d0..2345bf8867 100644
> --- a/target/ppc/translate.c
> +++ b/target/ppc/translate.c
> @@ -2741,212 +2741,6 @@ static void gen_isync(DisasContext *ctx)
> ctx->base.is_jmp = DISAS_EXIT_UPDATE;
> }
>
> -static void gen_fetch_inc_conditional(DisasContext *ctx, MemOp memop,
> - TCGv EA, TCGCond cond, int addend)
> -{
> - TCGv t = tcg_temp_new();
> - TCGv t2 = tcg_temp_new();
> - TCGv u = tcg_temp_new();
> -
> - tcg_gen_qemu_ld_tl(t, EA, ctx->mem_idx, memop);
> - tcg_gen_addi_tl(t2, EA, memop_size(memop));
> - tcg_gen_qemu_ld_tl(t2, t2, ctx->mem_idx, memop);
> - tcg_gen_addi_tl(u, t, addend);
> -
> - /* E.g. for fetch and increment bounded... */
> - /* mem(EA,s) = (t != t2 ? u = t + 1 : t) */
> - tcg_gen_movcond_tl(cond, u, t, t2, u, t);
> - tcg_gen_qemu_st_tl(u, EA, ctx->mem_idx, memop);
> -
> - /* RT = (t != t2 ? t : u = 1<<(s*8-1)) */
> - tcg_gen_movcond_tl(cond, cpu_gpr[rD(ctx->opcode)], t, t2, t,
> - tcg_constant_tl(1 << (memop_size(memop) * 8 - 1)));
> -}
> -
> -static void gen_ld_atomic(DisasContext *ctx, MemOp memop)
> -{
> - uint32_t gpr_FC = FC(ctx->opcode);
> - TCGv EA = tcg_temp_new();
> - int rt = rD(ctx->opcode);
> - bool need_serial;
> - TCGv src, dst;
> -
> - gen_addr_register(ctx, EA);
> - dst = cpu_gpr[rt];
> - src = cpu_gpr[(rt + 1) & 31];
> -
> - need_serial = false;
> - memop |= MO_ALIGN;
> - switch (gpr_FC) {
> - case 0: /* Fetch and add */
> - tcg_gen_atomic_fetch_add_tl(dst, EA, src, ctx->mem_idx, memop);
> - break;
> - case 1: /* Fetch and xor */
> - tcg_gen_atomic_fetch_xor_tl(dst, EA, src, ctx->mem_idx, memop);
> - break;
> - case 2: /* Fetch and or */
> - tcg_gen_atomic_fetch_or_tl(dst, EA, src, ctx->mem_idx, memop);
> - break;
> - case 3: /* Fetch and 'and' */
> - tcg_gen_atomic_fetch_and_tl(dst, EA, src, ctx->mem_idx, memop);
> - break;
> - case 4: /* Fetch and max unsigned */
> - tcg_gen_atomic_fetch_umax_tl(dst, EA, src, ctx->mem_idx, memop);
> - break;
> - case 5: /* Fetch and max signed */
> - tcg_gen_atomic_fetch_smax_tl(dst, EA, src, ctx->mem_idx, memop);
> - break;
> - case 6: /* Fetch and min unsigned */
> - tcg_gen_atomic_fetch_umin_tl(dst, EA, src, ctx->mem_idx, memop);
> - break;
> - case 7: /* Fetch and min signed */
> - tcg_gen_atomic_fetch_smin_tl(dst, EA, src, ctx->mem_idx, memop);
> - break;
> - case 8: /* Swap */
> - tcg_gen_atomic_xchg_tl(dst, EA, src, ctx->mem_idx, memop);
> - break;
> -
> - case 16: /* Compare and swap not equal */
> - if (tb_cflags(ctx->base.tb) & CF_PARALLEL) {
> - need_serial = true;
> - } else {
> - TCGv t0 = tcg_temp_new();
> - TCGv t1 = tcg_temp_new();
> -
> - tcg_gen_qemu_ld_tl(t0, EA, ctx->mem_idx, memop);
> - if ((memop & MO_SIZE) == MO_64 || TARGET_LONG_BITS == 32) {
> - tcg_gen_mov_tl(t1, src);
> - } else {
> - tcg_gen_ext32u_tl(t1, src);
> - }
> - tcg_gen_movcond_tl(TCG_COND_NE, t1, t0, t1,
> - cpu_gpr[(rt + 2) & 31], t0);
> - tcg_gen_qemu_st_tl(t1, EA, ctx->mem_idx, memop);
> - tcg_gen_mov_tl(dst, t0);
> - }
> - break;
> -
> - case 24: /* Fetch and increment bounded */
> - if (tb_cflags(ctx->base.tb) & CF_PARALLEL) {
> - need_serial = true;
> - } else {
> - gen_fetch_inc_conditional(ctx, memop, EA, TCG_COND_NE, 1);
> - }
> - break;
> - case 25: /* Fetch and increment equal */
> - if (tb_cflags(ctx->base.tb) & CF_PARALLEL) {
> - need_serial = true;
> - } else {
> - gen_fetch_inc_conditional(ctx, memop, EA, TCG_COND_EQ, 1);
> - }
> - break;
> - case 28: /* Fetch and decrement bounded */
> - if (tb_cflags(ctx->base.tb) & CF_PARALLEL) {
> - need_serial = true;
> - } else {
> - gen_fetch_inc_conditional(ctx, memop, EA, TCG_COND_NE, -1);
> - }
> - break;
> -
> - default:
> - /* invoke data storage error handler */
> - gen_exception_err(ctx, POWERPC_EXCP_DSI, POWERPC_EXCP_INVAL);
> - }
> -
> - if (need_serial) {
> - /* Restart with exclusive lock. */
> - gen_helper_exit_atomic(tcg_env);
> - ctx->base.is_jmp = DISAS_NORETURN;
> - }
> -}
> -
> -static void gen_lwat(DisasContext *ctx)
> -{
> - gen_ld_atomic(ctx, DEF_MEMOP(MO_UL));
> -}
> -
> -#ifdef TARGET_PPC64
> -static void gen_ldat(DisasContext *ctx)
> -{
> - gen_ld_atomic(ctx, DEF_MEMOP(MO_UQ));
> -}
> -#endif
> -
> -static void gen_st_atomic(DisasContext *ctx, MemOp memop)
> -{
> - uint32_t gpr_FC = FC(ctx->opcode);
> - TCGv EA = tcg_temp_new();
> - TCGv src, discard;
> -
> - gen_addr_register(ctx, EA);
> - src = cpu_gpr[rD(ctx->opcode)];
> - discard = tcg_temp_new();
> -
> - memop |= MO_ALIGN;
> - switch (gpr_FC) {
> - case 0: /* add and Store */
> - tcg_gen_atomic_add_fetch_tl(discard, EA, src, ctx->mem_idx, memop);
> - break;
> - case 1: /* xor and Store */
> - tcg_gen_atomic_xor_fetch_tl(discard, EA, src, ctx->mem_idx, memop);
> - break;
> - case 2: /* Or and Store */
> - tcg_gen_atomic_or_fetch_tl(discard, EA, src, ctx->mem_idx, memop);
> - break;
> - case 3: /* 'and' and Store */
> - tcg_gen_atomic_and_fetch_tl(discard, EA, src, ctx->mem_idx, memop);
> - break;
> - case 4: /* Store max unsigned */
> - tcg_gen_atomic_umax_fetch_tl(discard, EA, src, ctx->mem_idx, memop);
> - break;
> - case 5: /* Store max signed */
> - tcg_gen_atomic_smax_fetch_tl(discard, EA, src, ctx->mem_idx, memop);
> - break;
> - case 6: /* Store min unsigned */
> - tcg_gen_atomic_umin_fetch_tl(discard, EA, src, ctx->mem_idx, memop);
> - break;
> - case 7: /* Store min signed */
> - tcg_gen_atomic_smin_fetch_tl(discard, EA, src, ctx->mem_idx, memop);
> - break;
> - case 24: /* Store twin */
> - if (tb_cflags(ctx->base.tb) & CF_PARALLEL) {
> - /* Restart with exclusive lock. */
> - gen_helper_exit_atomic(tcg_env);
> - ctx->base.is_jmp = DISAS_NORETURN;
> - } else {
> - TCGv t = tcg_temp_new();
> - TCGv t2 = tcg_temp_new();
> - TCGv s = tcg_temp_new();
> - TCGv s2 = tcg_temp_new();
> - TCGv ea_plus_s = tcg_temp_new();
> -
> - tcg_gen_qemu_ld_tl(t, EA, ctx->mem_idx, memop);
> - tcg_gen_addi_tl(ea_plus_s, EA, memop_size(memop));
> - tcg_gen_qemu_ld_tl(t2, ea_plus_s, ctx->mem_idx, memop);
> - tcg_gen_movcond_tl(TCG_COND_EQ, s, t, t2, src, t);
> - tcg_gen_movcond_tl(TCG_COND_EQ, s2, t, t2, src, t2);
> - tcg_gen_qemu_st_tl(s, EA, ctx->mem_idx, memop);
> - tcg_gen_qemu_st_tl(s2, ea_plus_s, ctx->mem_idx, memop);
> - }
> - break;
> - default:
> - /* invoke data storage error handler */
> - gen_exception_err(ctx, POWERPC_EXCP_DSI, POWERPC_EXCP_INVAL);
> - }
> -}
> -
> -static void gen_stwat(DisasContext *ctx)
> -{
> - gen_st_atomic(ctx, DEF_MEMOP(MO_UL));
> -}
> -
> -#ifdef TARGET_PPC64
> -static void gen_stdat(DisasContext *ctx)
> -{
> - gen_st_atomic(ctx, DEF_MEMOP(MO_UQ));
> -}
> -#endif
> -
> /* wait */
> static void gen_wait(DisasContext *ctx)
> {
> @@ -5608,12 +5402,6 @@ GEN_HANDLER(lswx, 0x1F, 0x15, 0x10, 0x00000001, PPC_STRING),
> GEN_HANDLER(stswi, 0x1F, 0x15, 0x16, 0x00000001, PPC_STRING),
> GEN_HANDLER(stswx, 0x1F, 0x15, 0x14, 0x00000001, PPC_STRING),
> GEN_HANDLER(isync, 0x13, 0x16, 0x04, 0x03FFF801, PPC_MEM),
> -GEN_HANDLER_E(lwat, 0x1F, 0x06, 0x12, 0x00000001, PPC_NONE, PPC2_ISA300),
> -GEN_HANDLER_E(stwat, 0x1F, 0x06, 0x16, 0x00000001, PPC_NONE, PPC2_ISA300),
> -#if defined(TARGET_PPC64)
> -GEN_HANDLER_E(ldat, 0x1F, 0x06, 0x13, 0x00000001, PPC_NONE, PPC2_ISA300),
> -GEN_HANDLER_E(stdat, 0x1F, 0x06, 0x17, 0x00000001, PPC_NONE, PPC2_ISA300),
> -#endif
> /* ISA v3.0 changed the extended opcode from 62 to 30 */
> GEN_HANDLER(wait, 0x1F, 0x1E, 0x01, 0x039FF801, PPC_WAIT),
> GEN_HANDLER_E(wait, 0x1F, 0x1E, 0x00, 0x039CF801, PPC_NONE, PPC2_ISA300),
> diff --git a/target/ppc/translate/fixedpoint-impl.c.inc b/target/ppc/translate/fixedpoint-impl.c.inc
> index 25a60d3d3a..4d35133adc 100644
> --- a/target/ppc/translate/fixedpoint-impl.c.inc
> +++ b/target/ppc/translate/fixedpoint-impl.c.inc
> @@ -1646,3 +1646,218 @@ static bool trans_SRAWI(DisasContext *ctx, arg_SRAWI *a)
> }
> return true;
> }
> +
> +static void do_fetch_inc_conditional(DisasContext *ctx, MemOp memop,
> + TCGv EA, int rt,
> + TCGCond cond, int addend)
> +{
> + TCGv t = tcg_temp_new();
> + TCGv t2 = tcg_temp_new();
> + TCGv u = tcg_temp_new();
> +
> + tcg_gen_qemu_ld_tl(t, EA, ctx->mem_idx, memop);
> + tcg_gen_addi_tl(t2, EA, memop_size(memop));
> + tcg_gen_qemu_ld_tl(t2, t2, ctx->mem_idx, memop);
> + tcg_gen_addi_tl(u, t, addend);
> +
> + /* mem(EA,s) = (t cond t2 ? u = t + addend : t) */
> + tcg_gen_movcond_tl(cond, u, t, t2, u, t);
> + tcg_gen_qemu_st_tl(u, EA, ctx->mem_idx, memop);
> +
> + /* RT = (t cond t2 ? t : 1<<(s*8-1)) */
> + tcg_gen_movcond_tl(cond, cpu_gpr[rt], t, t2, t,
> + tcg_constant_tl(1 << (memop_size(memop) * 8 - 1)));
> +}
> +
> +/*
> + * Fixed-Point Atomic Load/Store Instructions
> + *
> + * In the X-form encoding the RB field carries the Function Code (FC)
> + * that selects the atomic operation. EA is computed from RA alone.
> + */
> +static bool do_ld_atomic(DisasContext *ctx, arg_X *a, MemOp memop)
> +{
> + TCGv EA, dst, src;
> + bool need_serial;
> +
> + REQUIRE_INSNS_FLAGS2(ctx, ISA300);
> +
> + EA = do_ea_calc(ctx, a->ra, tcg_constant_tl(0));
> + dst = cpu_gpr[a->rt];
> + src = cpu_gpr[(a->rt + 1) & 31];
> +
> + need_serial = false;
> + memop |= MO_ALIGN;
> + switch (a->rb) {
> + case 0: /* Fetch and add */
> + tcg_gen_atomic_fetch_add_tl(dst, EA, src, ctx->mem_idx, memop);
> + break;
> + case 1: /* Fetch and xor */
> + tcg_gen_atomic_fetch_xor_tl(dst, EA, src, ctx->mem_idx, memop);
> + break;
> + case 2: /* Fetch and or */
> + tcg_gen_atomic_fetch_or_tl(dst, EA, src, ctx->mem_idx, memop);
> + break;
> + case 3: /* Fetch and 'and' */
> + tcg_gen_atomic_fetch_and_tl(dst, EA, src, ctx->mem_idx, memop);
> + break;
> + case 4: /* Fetch and max unsigned */
> + tcg_gen_atomic_fetch_umax_tl(dst, EA, src, ctx->mem_idx, memop);
> + break;
> + case 5: /* Fetch and max signed */
> + tcg_gen_atomic_fetch_smax_tl(dst, EA, src, ctx->mem_idx, memop);
> + break;
> + case 6: /* Fetch and min unsigned */
> + tcg_gen_atomic_fetch_umin_tl(dst, EA, src, ctx->mem_idx, memop);
> + break;
> + case 7: /* Fetch and min signed */
> + tcg_gen_atomic_fetch_smin_tl(dst, EA, src, ctx->mem_idx, memop);
> + break;
> + case 8: /* Swap */
> + tcg_gen_atomic_xchg_tl(dst, EA, src, ctx->mem_idx, memop);
> + break;
> +
> + case 16: /* Compare and swap not equal */
> + if (tb_cflags(ctx->base.tb) & CF_PARALLEL) {
> + need_serial = true;
> + } else {
> + TCGv t0 = tcg_temp_new();
> + TCGv t1 = tcg_temp_new();
> +
> + tcg_gen_qemu_ld_tl(t0, EA, ctx->mem_idx, memop);
> + if ((memop & MO_SIZE) == MO_64 || TARGET_LONG_BITS == 32) {
> + tcg_gen_mov_tl(t1, src);
> + } else {
> + tcg_gen_ext32u_tl(t1, src);
> + }
> + tcg_gen_movcond_tl(TCG_COND_NE, t1, t0, t1,
> + cpu_gpr[(a->rt + 2) & 31], t0);
> + tcg_gen_qemu_st_tl(t1, EA, ctx->mem_idx, memop);
> + tcg_gen_mov_tl(dst, t0);
> + }
> + break;
> +
> + case 24: /* Fetch and increment bounded */
> + if (tb_cflags(ctx->base.tb) & CF_PARALLEL) {
> + need_serial = true;
> + } else {
> + do_fetch_inc_conditional(ctx, memop, EA, a->rt, TCG_COND_NE, 1);
> + }
> + break;
> + case 25: /* Fetch and increment equal */
> + if (tb_cflags(ctx->base.tb) & CF_PARALLEL) {
> + need_serial = true;
> + } else {
> + do_fetch_inc_conditional(ctx, memop, EA, a->rt, TCG_COND_EQ, 1);
> + }
> + break;
> + case 28: /* Fetch and decrement bounded */
> + if (tb_cflags(ctx->base.tb) & CF_PARALLEL) {
> + need_serial = true;
> + } else {
> + do_fetch_inc_conditional(ctx, memop, EA, a->rt, TCG_COND_NE, -1);
> + }
> + break;
> +
> + default:
> + /* invoke data storage error handler */
> + gen_exception_err(ctx, POWERPC_EXCP_DSI, POWERPC_EXCP_INVAL);
> + return true;
> + }
> +
> + if (need_serial) {
> + /* Restart with exclusive lock. */
> + gen_helper_exit_atomic(tcg_env);
> + ctx->base.is_jmp = DISAS_NORETURN;
> + }
> + return true;
> +}
> +
> +static bool do_st_atomic(DisasContext *ctx, arg_X *a, MemOp memop)
> +{
> + TCGv EA, src, discard;
> +
> + REQUIRE_INSNS_FLAGS2(ctx, ISA300);
> +
> + EA = do_ea_calc(ctx, a->ra, tcg_constant_tl(0));
> + src = cpu_gpr[a->rt];
> + discard = tcg_temp_new();
> +
> + memop |= MO_ALIGN;
> + switch (a->rb) {
> + case 0: /* add and Store */
> + tcg_gen_atomic_add_fetch_tl(discard, EA, src, ctx->mem_idx, memop);
> + break;
> + case 1: /* xor and Store */
> + tcg_gen_atomic_xor_fetch_tl(discard, EA, src, ctx->mem_idx, memop);
> + break;
> + case 2: /* Or and Store */
> + tcg_gen_atomic_or_fetch_tl(discard, EA, src, ctx->mem_idx, memop);
> + break;
> + case 3: /* 'and' and Store */
> + tcg_gen_atomic_and_fetch_tl(discard, EA, src, ctx->mem_idx, memop);
> + break;
> + case 4: /* Store max unsigned */
> + tcg_gen_atomic_umax_fetch_tl(discard, EA, src, ctx->mem_idx, memop);
> + break;
> + case 5: /* Store max signed */
> + tcg_gen_atomic_smax_fetch_tl(discard, EA, src, ctx->mem_idx, memop);
> + break;
> + case 6: /* Store min unsigned */
> + tcg_gen_atomic_umin_fetch_tl(discard, EA, src, ctx->mem_idx, memop);
> + break;
> + case 7: /* Store min signed */
> + tcg_gen_atomic_smin_fetch_tl(discard, EA, src, ctx->mem_idx, memop);
> + break;
> + case 24: /* Store twin */
> + if (tb_cflags(ctx->base.tb) & CF_PARALLEL) {
> + /* Restart with exclusive lock. */
> + gen_helper_exit_atomic(tcg_env);
> + ctx->base.is_jmp = DISAS_NORETURN;
> + } else {
> + TCGv t = tcg_temp_new();
> + TCGv t2 = tcg_temp_new();
> + TCGv s = tcg_temp_new();
> + TCGv s2 = tcg_temp_new();
> + TCGv ea_plus_s = tcg_temp_new();
> +
> + tcg_gen_qemu_ld_tl(t, EA, ctx->mem_idx, memop);
> + tcg_gen_addi_tl(ea_plus_s, EA, memop_size(memop));
> + tcg_gen_qemu_ld_tl(t2, ea_plus_s, ctx->mem_idx, memop);
> + tcg_gen_movcond_tl(TCG_COND_EQ, s, t, t2, src, t);
> + tcg_gen_movcond_tl(TCG_COND_EQ, s2, t, t2, src, t2);
> + tcg_gen_qemu_st_tl(s, EA, ctx->mem_idx, memop);
> + tcg_gen_qemu_st_tl(s2, ea_plus_s, ctx->mem_idx, memop);
> + }
> + break;
> + default:
> + /* invoke data storage error handler */
> + gen_exception_err(ctx, POWERPC_EXCP_DSI, POWERPC_EXCP_INVAL);
> + }
> + return true;
> +}
> +
> +TRANS(LWAT, do_ld_atomic, DEF_MEMOP(MO_UL))
> +TRANS(STWAT, do_st_atomic, DEF_MEMOP(MO_UL))
> +
> +static bool trans_LDAT(DisasContext *ctx, arg_LDAT *a)
> +{
> + REQUIRE_64BIT(ctx);
> +#if defined(TARGET_PPC64)
> + return do_ld_atomic(ctx, a, DEF_MEMOP(MO_UQ));
> +#else
> + qemu_build_not_reached();
> +#endif
> + return true;
> +}
> +
> +static bool trans_STDAT(DisasContext *ctx, arg_STDAT *a)
> +{
> + REQUIRE_64BIT(ctx);
> +#if defined(TARGET_PPC64)
> + return do_st_atomic(ctx, a, DEF_MEMOP(MO_UQ));
> +#else
> + qemu_build_not_reached();
> +#endif
> + return true;
> +}
next prev parent reply other threads:[~2026-07-07 4:56 UTC|newest]
Thread overview: 70+ messages / expand[flat|nested] mbox.gz Atom feed top
2026-05-20 16:07 [RFC PATCH 00/28] target/ppc: Moving instructions to decodetree specification Chinmay Rath
2026-05-20 16:07 ` [RFC PATCH 01/28] target/ppc: Migrate extswsli to decodetree Chinmay Rath
2026-05-20 16:07 ` [RFC PATCH 02/28] target/ppc: Migrate atomic loads " Chinmay Rath
2026-07-06 8:45 ` Chinmay Rath
2026-05-20 16:07 ` [RFC PATCH 03/28] target/ppc: Convert cache instructions " Chinmay Rath
2026-06-01 16:06 ` Shivang Upadhyay
2026-06-30 14:42 ` [RFC PATCH v2] " Nikhil Kumar Singh
2026-06-30 15:17 ` Shivang Upadhyay
2026-07-08 12:11 ` Chinmay Rath
2026-05-20 16:07 ` [RFC PATCH 04/28] target/ppc: Move vector merge " Chinmay Rath
2026-07-07 4:46 ` Nikhil Kumar Singh
2026-05-20 16:07 ` [RFC PATCH 05/28] target/ppc: Move vector pack " Chinmay Rath
2026-07-07 4:47 ` Nikhil Kumar Singh
2026-05-20 16:07 ` [RFC PATCH 06/28] target/ppc: Move st{b, h, w, d, q}cx " Chinmay Rath
2026-07-07 4:49 ` Nikhil Kumar Singh
2026-05-20 16:07 ` [RFC PATCH 07/28] target/ppc: convert slw, srw instruction via decode spec Chinmay Rath
2026-05-20 16:07 ` [RFC PATCH 08/28] target/ppc: convert sraw[i] " Chinmay Rath
2026-05-20 16:07 ` [RFC PATCH 09/28] target/ppc : Convert mcrf to decode tree Chinmay Rath
2026-06-12 8:38 ` Shivang Upadhyay
2026-05-20 16:07 ` [RFC PATCH 10/28] target/ppc: Move fixed-point Shift insns to decodetree Chinmay Rath
2026-05-20 16:07 ` [RFC PATCH 11/28] target/ppc: Move fixed-point byte-reversal store " Chinmay Rath
2026-06-12 15:16 ` Shivang Upadhyay
2026-07-08 8:41 ` Amit Machhiwal
2026-07-06 16:21 ` Nikhil Kumar Singh
2026-07-08 8:42 ` Amit Machhiwal
2026-05-20 16:07 ` [RFC PATCH 12/28] target/ppc: Move GPR atomic load/store instructions " Chinmay Rath
2026-07-07 4:55 ` Nikhil Kumar Singh [this message]
2026-05-20 16:07 ` [RFC PATCH 13/28] target/ppc: Move isync instruction " Chinmay Rath
2026-07-07 4:57 ` Nikhil Kumar Singh
2026-05-20 16:07 ` [RFC PATCH 14/28] target/ppc: Convert b{a, l, la} to decode tree Chinmay Rath
2026-07-07 4:58 ` Nikhil Kumar Singh
2026-05-20 16:07 ` [RFC PATCH 15/28] target/ppc: move various conditional branch insns to decodetree Chinmay Rath
2026-07-06 17:20 ` Nikhil Kumar Singh
2026-05-20 16:07 ` [RFC PATCH 16/28] target/ppc: Fix TRANS* macro variadic arguments handling Chinmay Rath
2026-05-20 16:07 ` [RFC PATCH 17/28] target/ppc: Move wait instruction to decodetree Chinmay Rath
2026-05-20 16:07 ` [RFC PATCH 18/28] target/ppc: Move sleep & friends " Chinmay Rath
2026-07-06 17:48 ` Nikhil Kumar Singh
2026-07-07 5:09 ` Nikhil Kumar Singh
2026-05-20 16:07 ` [RFC PATCH 19/28] target/ppc: Refactor sleep and its variants to use a common helper Chinmay Rath
2026-05-20 16:07 ` [RFC PATCH 20/28] target/ppc: Move Condition Register access instructions to decodetree Chinmay Rath
2026-05-20 16:07 ` [RFC PATCH 21/28] target/ppc: Move Condition Register logical " Chinmay Rath
2026-05-20 16:07 ` [RFC PATCH 22/28] target/ppc: Move Fixed-Point Load/Store String " Chinmay Rath
2026-07-06 8:54 ` Chinmay Rath
2026-07-06 14:01 ` Shivang Upadhyay
2026-07-06 18:09 ` Nikhil Kumar Singh
2026-07-07 10:36 ` Shivang Upadhyay
2026-07-08 7:41 ` Chinmay Rath
2026-07-08 8:46 ` Shivang Upadhyay
2026-05-20 16:07 ` [RFC PATCH 23/28] target/ppc: Move VMX integer arithmetic and BCD " Chinmay Rath
2026-07-06 15:22 ` Chinmay Rath
2026-07-07 10:41 ` Shivang Upadhyay
2026-05-20 16:07 ` [RFC PATCH 24/28] target/ppc: Move rlwimi, rlwinm " Chinmay Rath
2026-05-20 16:07 ` [RFC PATCH 25/28] target/ppc: Move lmw, stmw " Chinmay Rath
2026-05-20 16:07 ` [RFC PATCH 26/28] target/ppc: Move mfmsr, mtmsr[d] " Chinmay Rath
2026-05-20 16:07 ` [RFC PATCH 27/28] target/ppc: Move byte-reverse " Chinmay Rath
2026-05-20 16:07 ` [RFC PATCH 28/28] target/ppc: Move system call and rfi " Chinmay Rath
2026-05-22 8:29 ` [RFC PATCH 00/28] target/ppc: Moving instructions to decodetree specification Vishal Chourasia
2026-05-28 10:59 ` [RFC PATCH v2] target/ppc: Move system call and rfi instructions to decodetree Vishal Chourasia
2026-07-06 10:14 ` Chinmay Rath
2026-07-13 22:01 ` Vishal Chourasia
2026-07-13 22:23 ` [RFC PATCH v3] " Vishal Chourasia
2026-05-28 11:08 ` [RFC PATCH 00/28] target/ppc: Moving instructions to decodetree specification Vishal Chourasia
2026-06-03 11:39 ` Chinmay Rath
2026-06-03 14:10 ` Miles Glenn
2026-06-04 10:29 ` Chinmay Rath
2026-06-11 19:18 ` Miles Glenn
2026-06-30 5:42 ` Chinmay Rath
2026-07-08 11:30 ` Chinmay Rath
2026-06-03 14:30 ` Richard Henderson
2026-06-04 10:27 ` Chinmay Rath
Reply instructions:
You may reply publicly to this message via plain-text email
using any one of the following methods:
* Save the following mbox file, import it into your mail client,
and reply-to-all from there: mbox
Avoid top-posting and favor interleaved quoting:
https://en.wikipedia.org/wiki/Posting_style#Interleaved_style
* Reply using the --to, --cc, and --in-reply-to
switches of git-send-email(1):
git send-email \
--in-reply-to=a6deadff-708a-40ed-8e5a-fb8b332a64c9@linux.ibm.com \
--to=nikhilks@linux.ibm.com \
--cc=aboorvad@linux.ibm.com \
--cc=amachhiw@linux.ibm.com \
--cc=harshpb@linux.ibm.com \
--cc=milesg@linux.ibm.com \
--cc=mkchauras@gmail.com \
--cc=npiggin@gmail.com \
--cc=ojaswin@linux.ibm.com \
--cc=peter.maydell@linaro.org \
--cc=qemu-devel@nongnu.org \
--cc=qemu-ppc@nongnu.org \
--cc=rathc@linux.ibm.com \
--cc=richard.henderson@linaro.org \
--cc=shivangu@linux.ibm.com \
--cc=shivani@linux.ibm.com \
--cc=stefanha@redhat.com \
--cc=sv@linux.ibm.com \
--cc=tshah@linux.ibm.com \
--cc=uverma@linux.ibm.com \
--cc=vishalc@linux.ibm.com \
/path/to/YOUR_REPLY
https://kernel.org/pub/software/scm/git/docs/git-send-email.html
* If your mail client supports setting the In-Reply-To header
via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line
before the message body.
This is an external index of several public inboxes,
see mirroring instructions on how to clone and mirror
all data and code used by this external index.