* [PATCH] drm/amd/amdgpu: add vega10/raven mmhub/athub golden settings
@ 2017-09-21 2:56 Evan Quan
[not found] ` <1505962614-15022-1-git-send-email-evan.quan-5C7GfCeVMHo@public.gmane.org>
0 siblings, 1 reply; 2+ messages in thread
From: Evan Quan @ 2017-09-21 2:56 UTC (permalink / raw)
To: amd-gfx-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW
Cc: Jerry.Zhang-5C7GfCeVMHo, Evan Quan
Change-Id: I28e9ca38b68234d0325a5b8a01d135649939c0af
Signed-off-by: Evan Quan <evan.quan@amd.com>
---
drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c | 23 +++++++++++++++++++++++
1 file changed, 23 insertions(+)
diff --git a/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c b/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c
index 99147f5..6216993 100644
--- a/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c
@@ -32,6 +32,8 @@
#include "vega10/DC/dce_12_0_offset.h"
#include "vega10/DC/dce_12_0_sh_mask.h"
#include "vega10/vega10_enum.h"
+#include "vega10/MMHUB/mmhub_1_0_offset.h"
+#include "vega10/ATHUB/athub_1_0_offset.h"
#include "soc15_common.h"
@@ -71,6 +73,18 @@ static const u32 golden_settings_vega10_hdp[] =
0xf6e, 0x0fffffff, 0x00000000,
};
+static const u32 golden_settings_mmhub_1_0_0[] =
+{
+ SOC15_REG_OFFSET(MMHUB, 0, mmDAGB1_WRCLI2), 0x00000007, 0xfe5fe0fa,
+ SOC15_REG_OFFSET(MMHUB, 0, mmMMEA1_DRAM_WR_CLI2GRP_MAP0), 0x00000030, 0x55555565
+};
+
+static const u32 golden_settings_athub_1_0_0[] =
+{
+ SOC15_REG_OFFSET(ATHUB, 0, mmRPB_ARB_CNTL), 0x0000ff00, 0x00000800,
+ SOC15_REG_OFFSET(ATHUB, 0, mmRPB_ARB_CNTL2), 0x00ff00ff, 0x00080008
+};
+
static int gmc_v9_0_vm_fault_interrupt_state(struct amdgpu_device *adev,
struct amdgpu_irq_src *src,
unsigned type,
@@ -665,8 +679,17 @@ static void gmc_v9_0_init_golden_registers(struct amdgpu_device *adev)
{
switch (adev->asic_type) {
case CHIP_VEGA10:
+ amdgpu_program_register_sequence(adev,
+ golden_settings_mmhub_1_0_0,
+ (const u32)ARRAY_SIZE(golden_settings_mmhub_1_0_0));
+ amdgpu_program_register_sequence(adev,
+ golden_settings_athub_1_0_0,
+ (const u32)ARRAY_SIZE(golden_settings_athub_1_0_0));
break;
case CHIP_RAVEN:
+ amdgpu_program_register_sequence(adev,
+ golden_settings_athub_1_0_0,
+ (const u32)ARRAY_SIZE(golden_settings_athub_1_0_0));
break;
default:
break;
--
2.7.4
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^ permalink raw reply related [flat|nested] 2+ messages in thread
* Re: [PATCH] drm/amd/amdgpu: add vega10/raven mmhub/athub golden settings
[not found] ` <1505962614-15022-1-git-send-email-evan.quan-5C7GfCeVMHo@public.gmane.org>
@ 2017-09-21 3:28 ` Zhang, Jerry (Junwei)
0 siblings, 0 replies; 2+ messages in thread
From: Zhang, Jerry (Junwei) @ 2017-09-21 3:28 UTC (permalink / raw)
To: Evan Quan, amd-gfx-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW
On 09/21/2017 10:56 AM, Evan Quan wrote:
> Change-Id: I28e9ca38b68234d0325a5b8a01d135649939c0af
> Signed-off-by: Evan Quan <evan.quan@amd.com>
Reviewed-by: Junwei Zhang <Jerry.Zhang@amd.com>
> ---
> drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c | 23 +++++++++++++++++++++++
> 1 file changed, 23 insertions(+)
>
> diff --git a/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c b/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c
> index 99147f5..6216993 100644
> --- a/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c
> +++ b/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c
> @@ -32,6 +32,8 @@
> #include "vega10/DC/dce_12_0_offset.h"
> #include "vega10/DC/dce_12_0_sh_mask.h"
> #include "vega10/vega10_enum.h"
> +#include "vega10/MMHUB/mmhub_1_0_offset.h"
> +#include "vega10/ATHUB/athub_1_0_offset.h"
>
> #include "soc15_common.h"
>
> @@ -71,6 +73,18 @@ static const u32 golden_settings_vega10_hdp[] =
> 0xf6e, 0x0fffffff, 0x00000000,
> };
>
> +static const u32 golden_settings_mmhub_1_0_0[] =
> +{
> + SOC15_REG_OFFSET(MMHUB, 0, mmDAGB1_WRCLI2), 0x00000007, 0xfe5fe0fa,
> + SOC15_REG_OFFSET(MMHUB, 0, mmMMEA1_DRAM_WR_CLI2GRP_MAP0), 0x00000030, 0x55555565
> +};
> +
> +static const u32 golden_settings_athub_1_0_0[] =
> +{
> + SOC15_REG_OFFSET(ATHUB, 0, mmRPB_ARB_CNTL), 0x0000ff00, 0x00000800,
> + SOC15_REG_OFFSET(ATHUB, 0, mmRPB_ARB_CNTL2), 0x00ff00ff, 0x00080008
> +};
> +
> static int gmc_v9_0_vm_fault_interrupt_state(struct amdgpu_device *adev,
> struct amdgpu_irq_src *src,
> unsigned type,
> @@ -665,8 +679,17 @@ static void gmc_v9_0_init_golden_registers(struct amdgpu_device *adev)
> {
> switch (adev->asic_type) {
> case CHIP_VEGA10:
> + amdgpu_program_register_sequence(adev,
> + golden_settings_mmhub_1_0_0,
> + (const u32)ARRAY_SIZE(golden_settings_mmhub_1_0_0));
> + amdgpu_program_register_sequence(adev,
> + golden_settings_athub_1_0_0,
> + (const u32)ARRAY_SIZE(golden_settings_athub_1_0_0));
> break;
> case CHIP_RAVEN:
> + amdgpu_program_register_sequence(adev,
> + golden_settings_athub_1_0_0,
> + (const u32)ARRAY_SIZE(golden_settings_athub_1_0_0));
> break;
> default:
> break;
>
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amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx
^ permalink raw reply [flat|nested] 2+ messages in thread
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2017-09-21 2:56 [PATCH] drm/amd/amdgpu: add vega10/raven mmhub/athub golden settings Evan Quan
[not found] ` <1505962614-15022-1-git-send-email-evan.quan-5C7GfCeVMHo@public.gmane.org>
2017-09-21 3:28 ` Zhang, Jerry (Junwei)
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