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From: Chanwoo Choi <cw00.choi@samsung.com>
To: Sylwester Nawrocki <s.nawrocki@samsung.com>, linux-clk@vger.kernel.org
Cc: mturquette@baylibre.com, sboyd@kernel.org,
	linux-samsung-soc@vger.kernel.org,
	linux-arm-kernel@lists.infradead.org, b.zolnierkie@samsung.com,
	m.szyprowski@samsung.com
Subject: Re: [PATCH] clk: samsung: exynos5420: Add more entries to EPLL rate table
Date: Thu, 08 Mar 2018 10:55:06 +0900	[thread overview]
Message-ID: <5AA097FA.5070704@samsung.com> (raw)
In-Reply-To: <20180307164656.12194-2-s.nawrocki@samsung.com>

On 2018년 03월 08일 01:46, Sylwester Nawrocki wrote:
> Adding these EPLL output frequency entries allows to support all required
> audio sample rates on the CODEC and the HDMI interface on Peach-Pit
> Chromebook.
> 
> Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com>
> ---
>  drivers/clk/samsung/clk-exynos5420.c | 3 +++
>  1 file changed, 3 insertions(+)
> 
> diff --git a/drivers/clk/samsung/clk-exynos5420.c b/drivers/clk/samsung/clk-exynos5420.c
> index 1f204ba37f0f..f2607cb97a97 100644
> --- a/drivers/clk/samsung/clk-exynos5420.c
> +++ b/drivers/clk/samsung/clk-exynos5420.c
> @@ -1360,8 +1360,11 @@ static const struct samsung_pll_rate_table exynos5420_epll_24mhz_tbl[] = {
>  	PLL_36XX_RATE(180633609U, 301, 5, 3, 3671),
>  	PLL_36XX_RATE(131072006U, 131, 3, 3, 4719),
>  	PLL_36XX_RATE(100000000U, 200, 3, 4, 0),
> +	PLL_36XX_RATE( 73728000U, 98, 2, 4, 19923),
> +	PLL_36XX_RATE( 67737602U, 90, 2, 4, 20762),
>  	PLL_36XX_RATE( 65536003U, 131, 3, 4, 4719),
>  	PLL_36XX_RATE( 49152000U, 197, 3, 5, -25690),
> +	PLL_36XX_RATE( 45158401U, 90, 3, 4, 20762),
>  	PLL_36XX_RATE( 32768001U, 131, 3, 5, 4719),
>  };
>  
> 

Looks good to me.
Acked-by: Chanwoo Choi <cw00.choi@samsung.com>

-- 
Best Regards,
Chanwoo Choi
Samsung Electronics

WARNING: multiple messages have this Message-ID (diff)
From: Chanwoo Choi <cw00.choi@samsung.com>
To: Sylwester Nawrocki <s.nawrocki@samsung.com>, linux-clk@vger.kernel.org
Cc: linux-samsung-soc@vger.kernel.org, b.zolnierkie@samsung.com,
	sboyd@kernel.org, mturquette@baylibre.com,
	linux-arm-kernel@lists.infradead.org, m.szyprowski@samsung.com
Subject: Re: [PATCH] clk: samsung: exynos5420: Add more entries to EPLL rate table
Date: Thu, 08 Mar 2018 10:55:06 +0900	[thread overview]
Message-ID: <5AA097FA.5070704@samsung.com> (raw)
In-Reply-To: <20180307164656.12194-2-s.nawrocki@samsung.com>

On 2018년 03월 08일 01:46, Sylwester Nawrocki wrote:
> Adding these EPLL output frequency entries allows to support all required
> audio sample rates on the CODEC and the HDMI interface on Peach-Pit
> Chromebook.
> 
> Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com>
> ---
>  drivers/clk/samsung/clk-exynos5420.c | 3 +++
>  1 file changed, 3 insertions(+)
> 
> diff --git a/drivers/clk/samsung/clk-exynos5420.c b/drivers/clk/samsung/clk-exynos5420.c
> index 1f204ba37f0f..f2607cb97a97 100644
> --- a/drivers/clk/samsung/clk-exynos5420.c
> +++ b/drivers/clk/samsung/clk-exynos5420.c
> @@ -1360,8 +1360,11 @@ static const struct samsung_pll_rate_table exynos5420_epll_24mhz_tbl[] = {
>  	PLL_36XX_RATE(180633609U, 301, 5, 3, 3671),
>  	PLL_36XX_RATE(131072006U, 131, 3, 3, 4719),
>  	PLL_36XX_RATE(100000000U, 200, 3, 4, 0),
> +	PLL_36XX_RATE( 73728000U, 98, 2, 4, 19923),
> +	PLL_36XX_RATE( 67737602U, 90, 2, 4, 20762),
>  	PLL_36XX_RATE( 65536003U, 131, 3, 4, 4719),
>  	PLL_36XX_RATE( 49152000U, 197, 3, 5, -25690),
> +	PLL_36XX_RATE( 45158401U, 90, 3, 4, 20762),
>  	PLL_36XX_RATE( 32768001U, 131, 3, 5, 4719),
>  };
>  
> 

Looks good to me.
Acked-by: Chanwoo Choi <cw00.choi@samsung.com>

-- 
Best Regards,
Chanwoo Choi
Samsung Electronics

_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel

WARNING: multiple messages have this Message-ID (diff)
From: cw00.choi@samsung.com (Chanwoo Choi)
To: linux-arm-kernel@lists.infradead.org
Subject: [PATCH] clk: samsung: exynos5420: Add more entries to EPLL rate table
Date: Thu, 08 Mar 2018 10:55:06 +0900	[thread overview]
Message-ID: <5AA097FA.5070704@samsung.com> (raw)
In-Reply-To: <20180307164656.12194-2-s.nawrocki@samsung.com>

On 2018? 03? 08? 01:46, Sylwester Nawrocki wrote:
> Adding these EPLL output frequency entries allows to support all required
> audio sample rates on the CODEC and the HDMI interface on Peach-Pit
> Chromebook.
> 
> Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com>
> ---
>  drivers/clk/samsung/clk-exynos5420.c | 3 +++
>  1 file changed, 3 insertions(+)
> 
> diff --git a/drivers/clk/samsung/clk-exynos5420.c b/drivers/clk/samsung/clk-exynos5420.c
> index 1f204ba37f0f..f2607cb97a97 100644
> --- a/drivers/clk/samsung/clk-exynos5420.c
> +++ b/drivers/clk/samsung/clk-exynos5420.c
> @@ -1360,8 +1360,11 @@ static const struct samsung_pll_rate_table exynos5420_epll_24mhz_tbl[] = {
>  	PLL_36XX_RATE(180633609U, 301, 5, 3, 3671),
>  	PLL_36XX_RATE(131072006U, 131, 3, 3, 4719),
>  	PLL_36XX_RATE(100000000U, 200, 3, 4, 0),
> +	PLL_36XX_RATE( 73728000U, 98, 2, 4, 19923),
> +	PLL_36XX_RATE( 67737602U, 90, 2, 4, 20762),
>  	PLL_36XX_RATE( 65536003U, 131, 3, 4, 4719),
>  	PLL_36XX_RATE( 49152000U, 197, 3, 5, -25690),
> +	PLL_36XX_RATE( 45158401U, 90, 3, 4, 20762),
>  	PLL_36XX_RATE( 32768001U, 131, 3, 5, 4719),
>  };
>  
> 

Looks good to me.
Acked-by: Chanwoo Choi <cw00.choi@samsung.com>

-- 
Best Regards,
Chanwoo Choi
Samsung Electronics

  reply	other threads:[~2018-03-08  1:55 UTC|newest]

Thread overview: 18+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
     [not found] <CGME20180307164708epcas1p27e6599e85617f559c5c4c8eb92a70a47@epcas1p2.samsung.com>
2018-03-07 16:46 ` [PATCH] clk: samsung: exynos5420: Add CLK_SET_RATE_PARENT flag to mout_mau_epll_clk Sylwester Nawrocki
2018-03-07 16:46   ` Sylwester Nawrocki
2018-03-07 16:46   ` Sylwester Nawrocki
2018-03-07 16:46   ` [PATCH] clk: samsung: exynos5420: Add more entries to EPLL rate table Sylwester Nawrocki
2018-03-07 16:46     ` Sylwester Nawrocki
2018-03-07 16:46     ` Sylwester Nawrocki
2018-03-08  1:55     ` Chanwoo Choi [this message]
2018-03-08  1:55       ` Chanwoo Choi
2018-03-08  1:55       ` Chanwoo Choi
2018-03-12 10:31       ` Sylwester Nawrocki
2018-03-12 10:31         ` Sylwester Nawrocki
2018-03-12 10:31         ` Sylwester Nawrocki
2018-03-08  2:25   ` [PATCH] clk: samsung: exynos5420: Add CLK_SET_RATE_PARENT flag to mout_mau_epll_clk Chanwoo Choi
2018-03-08  2:25     ` Chanwoo Choi
2018-03-08  2:25     ` Chanwoo Choi
2018-03-12 10:29     ` Sylwester Nawrocki
2018-03-12 10:29       ` Sylwester Nawrocki
2018-03-12 10:29       ` Sylwester Nawrocki

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