[PATCH v3 0/3] A-core no-SPL Boot Support

[PATCH v3 0/3] A-core no-SPL Boot Support

[Gokul Praveen]

A-Core no-SPL Mode is a boot approach that bypasses
the A Core SPL while retaining U-Boot in the boot flow.
This mode provides faster boot times compared to normal boot
while maintaining U-Boot's flexibility for kernel loading
and system configuration..

v3<==> v2
===========
* Updated the naming convention used from "no-spl" to "A-core no-spl" to
* make it more specific and clear..
* Link to v2:https://lore.kernel.org/all/20260818115322.101705-1-g-praveen@ti.com/

v2<==> v1
===========
* Updated the naming convention used from "semi-falcon" to "no-spl".
* Link to v1: https://lore.kernel.org/all/20260814102153.44487-1-g-praveen@ti.com/

Boot logs link :
https://gist.github.com/GokulPraveen2001/fef407a482e2dad30272006de557627c

Gokul Praveen (3):
  configs: add A-core no-SPL mode fragment for k3 devices
  arm: k3-binman: add tinospl.bin for direct U-Boot boot
  doc: ti: document A Core no-SPL boot mode for J784S4 EVM

 Makefile                               |   2 +-
 arch/arm/dts/k3-binman.dtsi            |  47 ++++++++
 arch/arm/dts/k3-j784s4-binman.dtsi     |  65 +++++++++++
 arch/arm/dts/k3-j784s4-evm-u-boot.dtsi |  14 +++
 configs/k3_a72_nospl.config            |   1 +
 configs/k3_r5_nospl.config             |   1 +
 doc/board/ti/j784s4_evm.rst            | 143 +++++++++++++++++++++++++
 7 files changed, 272 insertions(+), 1 deletion(-)
 create mode 100644 configs/k3_a72_nospl.config
 create mode 100644 configs/k3_r5_nospl.config

-- 
2.34.1

[PATCH v3 1/3] configs: add A-core no-SPL mode fragment for k3 devices

[Gokul Praveen]

This fragment enables a boot mode for K3 platforms where the R5 SPL
directly loads U-Boot proper, bypassing the A Core SPL stage

The R5 config modifies the payload filename to load tinospl.bin
instead of tispl.bin. The A Core config updates the U-Boot load
address to match the A Core SPL load address, allowing R5 SPL to
load U-Boot directly from that location since A Core SPL is not
present in this boot flow.

This reduces boot time by eliminating the A Core SPL stage.

Signed-off-by: Gokul Praveen <g-praveen@ti.com>
Reviewed-by Neha Malcom Francis <n-francis@ti.com>
---
 configs/k3_a72_nospl.config | 1 +
 configs/k3_r5_nospl.config  | 1 +
 2 files changed, 2 insertions(+)
 create mode 100644 configs/k3_a72_nospl.config
 create mode 100644 configs/k3_r5_nospl.config

diff --git a/configs/k3_a72_nospl.config b/configs/k3_a72_nospl.config
new file mode 100644
index 00000000000..7522acab950
--- /dev/null
+++ b/configs/k3_a72_nospl.config
@@ -0,0 +1 @@
+CONFIG_TEXT_BASE=0x80080000
diff --git a/configs/k3_r5_nospl.config b/configs/k3_r5_nospl.config
new file mode 100644
index 00000000000..94931bf8798
--- /dev/null
+++ b/configs/k3_r5_nospl.config
@@ -0,0 +1 @@
+CONFIG_SPL_FS_LOAD_PAYLOAD_NAME="tinospl.bin"
-- 
2.34.1

Re: [PATCH v3 1/3] configs: add A-core no-SPL mode fragment for k3 devices

[Andrew Davis]

On 8/19/26 5:19 AM, Gokul Praveen wrote:
> This fragment enables a boot mode for K3 platforms where the R5 SPL
> directly loads U-Boot proper, bypassing the A Core SPL stage
> 
> The R5 config modifies the payload filename to load tinospl.bin
> instead of tispl.bin. The A Core config updates the U-Boot load
> address to match the A Core SPL load address, allowing R5 SPL to
> load U-Boot directly from that location since A Core SPL is not
> present in this boot flow.
> 
> This reduces boot time by eliminating the A Core SPL stage.
> 

Is there any downside to this approach to look out for? If this
is strictly better, then why not make this the default and not
add yet another boot flow combination (to the already long list
of combinations..)?

Andrew

> Signed-off-by: Gokul Praveen <g-praveen@ti.com>
> Reviewed-by Neha Malcom Francis <n-francis@ti.com>
> ---
>   configs/k3_a72_nospl.config | 1 +
>   configs/k3_r5_nospl.config  | 1 +
>   2 files changed, 2 insertions(+)
>   create mode 100644 configs/k3_a72_nospl.config
>   create mode 100644 configs/k3_r5_nospl.config
> 
> diff --git a/configs/k3_a72_nospl.config b/configs/k3_a72_nospl.config
> new file mode 100644
> index 00000000000..7522acab950
> --- /dev/null
> +++ b/configs/k3_a72_nospl.config
> @@ -0,0 +1 @@
> +CONFIG_TEXT_BASE=0x80080000
> diff --git a/configs/k3_r5_nospl.config b/configs/k3_r5_nospl.config
> new file mode 100644
> index 00000000000..94931bf8798
> --- /dev/null
> +++ b/configs/k3_r5_nospl.config
> @@ -0,0 +1 @@
> +CONFIG_SPL_FS_LOAD_PAYLOAD_NAME="tinospl.bin"

[PATCH v3 2/3] arm: k3-binman: add tinospl.bin for direct U-Boot boot

[Gokul Praveen]

This patch adds creation of tinospl.bin for J784S4 EVM.

The contents are similar to the existing tispl.bin but the A72 SPL
and its FDT have been removed and replaced with U-Boot proper and its
FDT. This binary is used in a boot mode where R5 SPL directly loads
U-Boot, bypassing the A Core SPL stage.

This reduces boot time by eliminating the A Core SPL stage.

tispl.bin   = TFA + TEE + DM + A72 SPL + FDT(A72 SPL)
tinospl.bin = TFA + TEE + DM + U-Boot  + FDT(U-Boot)

Signed-off-by: Gokul Praveen <g-praveen@ti.com>
Reviewed-by: Neha Malcom Francis <n-francis@ti.com>
---
 Makefile                               |  2 +-
 arch/arm/dts/k3-binman.dtsi            | 47 +++++++++++++++++++
 arch/arm/dts/k3-j784s4-binman.dtsi     | 65 ++++++++++++++++++++++++++
 arch/arm/dts/k3-j784s4-evm-u-boot.dtsi | 14 ++++++
 4 files changed, 127 insertions(+), 1 deletion(-)

diff --git a/Makefile b/Makefile
index c6253670a94..c6723d63f59 100644
--- a/Makefile
+++ b/Makefile
@@ -2556,7 +2556,7 @@ CLEAN_FILES += include/autoconf.mk* include/bmp_logo.h include/bmp_logo_data.h \
 	       idbloader-spi.img lib/efi_loader/helloworld_efi.S *.itb \
 	       Test* capsule*.*.efi-capsule capsule*.map mkimage.imx-boot.spl \
 	       mkimage.imx-boot.u-boot mkimage-out.imx-boot.spl mkimage-out.imx-boot.u-boot \
-	       imx9image* m33-oei-ddrfw* tifalcon.bin
+	       imx9image* m33-oei-ddrfw* tifalcon.bin tinospl.bin
 
 # Directories & files removed with 'make mrproper'
 MRPROPER_FILES  += include/config include/generated spl tpl vpl \
diff --git a/arch/arm/dts/k3-binman.dtsi b/arch/arm/dts/k3-binman.dtsi
index ad127663d03..aa8479bc0f6 100644
--- a/arch/arm/dts/k3-binman.dtsi
+++ b/arch/arm/dts/k3-binman.dtsi
@@ -543,6 +543,53 @@
 		};
 	};
 
+	ti_nospl_template: template-16 {
+		filename = "tinospl.bin";
+		pad-byte = <0xff>;
+
+		fit {
+			description = "Configuration for no-SPL boot";
+			#address-cells = <1>;
+
+			images {
+				atf {
+					description = "ARM Trusted Firmware";
+					type = "firmware";
+					arch = "arm64";
+					compression = "none";
+					os = "arm-trusted-firmware";
+					load = <CONFIG_K3_ATF_LOAD_ADDR>;
+					entry = <CONFIG_K3_ATF_LOAD_ADDR>;
+					atf-bl31 {
+						filename = "bl31.bin";
+					};
+				};
+				tee {
+					description = "OP-TEE";
+					type = "tee";
+					arch = "arm64";
+					compression = "none";
+					os = "tee";
+					load = <CONFIG_K3_OPTEE_LOAD_ADDR>;
+					entry = <CONFIG_K3_OPTEE_LOAD_ADDR>;
+					tee-os {
+						filename = "tee-raw.bin";
+						optional;
+					};
+				};
+				dm {
+					description = "DM binary";
+					type = "firmware";
+					arch = "arm32";
+					compression = "none";
+					os = "DM";
+					load = <0x89000000>;
+					entry = <0x89000000>;
+				};
+			};
+		};
+	};
+
 };
 
 #endif
diff --git a/arch/arm/dts/k3-j784s4-binman.dtsi b/arch/arm/dts/k3-j784s4-binman.dtsi
index 34b2cc1e681..0dec4316d6b 100644
--- a/arch/arm/dts/k3-j784s4-binman.dtsi
+++ b/arch/arm/dts/k3-j784s4-binman.dtsi
@@ -317,4 +317,69 @@
 		};
 	};
 };
+
+&binman{
+	ti_nospl: template-17{
+		insert-template = <&ti_nospl_template>;
+
+		fit {
+			images {
+				dm {
+					ti-dm {
+					};
+				};
+
+				uboot {
+					description = UBOOT_BOARD_DESCRIPTION;
+					type = "firmware";
+					os = "u-boot";
+					arch = "arm";
+					compression = "none";
+					load = <CONFIG_TEXT_BASE>;
+					ti-secure {
+						content = <&u_boot_nodtb_nospl>;
+						keyfile = "custMpk.pem";
+					};
+					u_boot_nodtb_nospl: blob-ext {
+						filename = "u-boot-nodtb.bin";
+					};
+					hash {
+						algo = "crc32";
+					};
+				};
+
+				fdt-0 {
+					description = BOARD_DESCRIPTION;
+					type = "flat_dt";
+					arch = "arm";
+					compression = "none";
+
+					ti-secure {
+						content = <&j784s4_evm_dtb_nospl>;
+						keyfile = "custMpk.pem";
+					};
+
+					j784s4_evm_dtb_nospl: blob-ext {
+						filename = "u-boot.dtb";
+					};
+
+					hash {
+						algo = "crc32";
+					};
+				};
+			};
+
+			configurations {
+				default = "conf-0";
+
+				conf-0 {
+					description = BOARD_DESCRIPTION;
+					firmware = "atf";
+					loadables = "tee", "dm", "uboot";
+					fdt = "fdt-0";
+				};
+			};
+		};
+	};
+};
 #endif
diff --git a/arch/arm/dts/k3-j784s4-evm-u-boot.dtsi b/arch/arm/dts/k3-j784s4-evm-u-boot.dtsi
index cc0b562d27e..fc6f23736ae 100644
--- a/arch/arm/dts/k3-j784s4-evm-u-boot.dtsi
+++ b/arch/arm/dts/k3-j784s4-evm-u-boot.dtsi
@@ -87,6 +87,20 @@
 	u-boot-unsigned {
 		insert-template = <&u_boot_unsigned>;
 	};
+
+	ti-nospl {
+		insert-template = <&ti_nospl>;
+
+		fit {
+			images {
+				dm {
+					ti-dm {
+						filename = "ti-dm/j784s4/ipc_echo_testb_mcu1_0_release_strip.xer5f";
+					};
+				};
+			};
+		};
+	};
 };
 
 #endif
-- 
2.34.1

[PATCH v3 3/3] doc: ti: document A Core no-SPL boot mode for J784S4 EVM

[Gokul Praveen]

This patch adds user documentation for the A Core no-SPL boot mode
on J784S4 EVM, where R5 SPL directly loads U-Boot proper, bypassing
the A Core SPL stage.

The documentation covers the boot flow, build steps, and usage
instructions for this boot mode using tinospl.bin.

Signed-off-by: Gokul Praveen <g-praveen@ti.com>
---
 doc/board/ti/j784s4_evm.rst | 143 ++++++++++++++++++++++++++++++++++++
 1 file changed, 143 insertions(+)

diff --git a/doc/board/ti/j784s4_evm.rst b/doc/board/ti/j784s4_evm.rst
index ec82228ab90..cf870066291 100644
--- a/doc/board/ti/j784s4_evm.rst
+++ b/doc/board/ti/j784s4_evm.rst
@@ -637,6 +637,149 @@ to the J784S4 endpoint:
 This program copies the boot image to the PCIe endpoint's memory region and
 writes the necessary control words to signal image transfer completion.
 
+A-Core No-SPL Boot Mode
+----------------
+
+A-Core No-SPL Boot Mode on J784S4 platforms is a boot approach that bypasses
+the A72 SPL while retaining U-Boot in the boot flow. This mode provides faster
+boot times compared to normal boot while maintaining U-Boot's flexibility for
+kernel loading and system configuration.
+
+**Key differences from Normal Boot:**
+
+* Skips A72 SPL execution
+* U-Boot binary included in tinospl.bin alongside TFA, OP-TEE, and DM
+* U-Boot loads at CONFIG_TEXT_BASE=0x80080000 (A72 SPL's earlier load location)
+
+Boot Flow
+^^^^^^^^^
+
+**Normal boot flow:**
+
+.. code-block::
+
+             | tiboot3.bin |         tispl.bin          | u-boot.img |  Image  |
+             |-------------+----------------------------+------------+---------|
+    R5 Core  |    SPL      |                            |            |         |
+    ---------|       \     |                            |            |         |
+    A72 Core |        ------> TFA -> OP-TEE -> A72 SPL -->  U-Boot  --> Kernel |
+
+**With  A-Core no-SPL boot mode:**
+
+.. code-block::
+
+             | tiboot3.bin |        tinospl.bin          |  Image  |
+             |-------------+-----------------------------+---------|
+    R5 Core  |    SPL      |                             |         |
+    ---------|       \     |                             |         |
+    A72 Core |        ------> TFA -> OP-TEE -> DM -> U-Boot --> Kernel |
+
+Build Process
+^^^^^^^^^^^^^
+
+Enabling A-Core no-SPL boot mode requires re-building U-Boot as follows:
+
+0. Setup environment variables:
+"""""""""""""""""""""""""""""""
+
+Refer to the build procedure above for setting up the environment variables.
+
+1. U-Boot:
+""""""""""
+
+* **1.1 R5:**
+
+.. prompt:: bash $
+
+ # use the no-SPL config fragment for K3 platforms
+ export UBOOT_NOSPL_CFG_FRAGMENTR="k3_r5_nospl.config"
+ export UBOOT_CFG_CORTEXR="${UBOOT_CFG_CORTEXR} ${UBOOT_NOSPL_CFG_FRAGMENTR}"
+
+.. include::  k3.rst
+    :start-after: .. k3_rst_include_start_build_steps_spl_r5
+    :end-before: .. k3_rst_include_end_build_steps_spl_r5
+
+* **1.2 A72:**
+
+.. prompt:: bash $
+
+ # use the no-SPL config fragment for A72
+ export UBOOT_NOSPL_CFG_FRAGMENTA="k3_a72_nospl.config"
+ export UBOOT_CFG_CORTEXA="${UBOOT_CFG_CORTEXA} ${UBOOT_NOSPL_CFG_FRAGMENTA}"
+
+.. include::  k3.rst
+    :start-after: .. k3_rst_include_start_build_steps_uboot
+    :end-before: .. k3_rst_include_end_build_steps_uboot
+
+.. note::
+
+    The ``tinospl.bin`` file is automatically generated by binman during
+    the A72 U-Boot build process. This binary contains TFA, OP-TEE, DM, and
+    the U-Boot binary with its device tree.
+
+Usage
+^^^^^
+
+A-Core No-SPL Boot Mode uses a specialized binary called ``tinospl.bin`` which
+contains all necessary components to boot directly to U-Boot without loading
+the A72 SPL.
+
+**tinospl.bin structure:**
+
+The tinospl.bin is a FIT image containing:
+
+* **ATF (ARM Trusted Firmware)** - loaded at CONFIG_K3_ATF_LOAD_ADDR
+* **OP-TEE** - loaded at CONFIG_K3_OPTEE_LOAD_ADDR
+* **DM (Device Manager)** - loaded at 0x89000000
+* **U-Boot** - loaded at CONFIG_TEXT_BASE (0x80080000)
+* **DTB (Device Tree Blob)** - U-Boot device tree
+
+The R5 SPL requires both ``tiboot3.bin`` and ``tinospl.bin`` to be present
+in the boot partition (first partition) of the MMC device. By default, the SD
+card boot partition is used (``mmcdev=1``). The ``bootpart`` environment variable
+defaults to 1:2, specifying the second partition of the SD card.
+
+To use eMMC instead of SD as the boot media, rebuild the R5 SPL with the
+following diff:
+
+.. code-block:: diff
+
+    diff --git a/board/ti/j784s4/j784s4.env b/board/ti/j784s4/j784s4.env
+    index 82b9f0741bb..73d59ac425c 100644
+    --- a/board/ti/j784s4/j784s4.env
+    +++ b/board/ti/j784s4/j784s4.env
+    @@ -17,8 +17,8 @@ run_kern=booti ${loadaddr} ${rd_spec} ${fdtaddr}
+
+     boot_targets=mmc1 mmc0 usb pxe dhcp
+     boot=mmc
+    -mmcdev=1
+    -bootpart=1:2
+    +mmcdev=0
+    +bootpart=0:2
+     bootdir=/boot
+     rd_spec=-
+
+**List of files required on SD/eMMC for A-Core No-SPL Boot Mode:**
+
+.. list-table::
+   :widths: 10 15 10 25
+   :header-rows: 1
+
+   * - File
+     - Copy path on SD/eMMC
+     - Partition
+     - Description
+
+   * - ``tiboot3.bin``
+     - Boot partition (raw)
+     - 1st partition (FAT32)
+     - R5 SPL binary
+
+   * - ``tinospl.bin``
+     - Boot partition (raw)
+     - 1st partition (FAT32)
+     - Combined binary with TFA, OP-TEE, DM, and U-Boot
+
 Debugging U-Boot
 ----------------
 
-- 
2.34.1

Re: [PATCH v3 3/3] doc: ti: document A Core no-SPL boot mode for J784S4 EVM

[Bryan Brattlof]

On August 19, 2026 thus sayeth Gokul Praveen:
> This patch adds user documentation for the A Core no-SPL boot mode
> on J784S4 EVM, where R5 SPL directly loads U-Boot proper, bypassing
> the A Core SPL stage.
> 
> The documentation covers the boot flow, build steps, and usage
> instructions for this boot mode using tinospl.bin.
> 
> Signed-off-by: Gokul Praveen <g-praveen@ti.com>
> ---
>  doc/board/ti/j784s4_evm.rst | 143 ++++++++++++++++++++++++++++++++++++
>  1 file changed, 143 insertions(+)
> 
> diff --git a/doc/board/ti/j784s4_evm.rst b/doc/board/ti/j784s4_evm.rst
> index ec82228ab90..cf870066291 100644
> --- a/doc/board/ti/j784s4_evm.rst
> +++ b/doc/board/ti/j784s4_evm.rst
> @@ -637,6 +637,149 @@ to the J784S4 endpoint:
>  This program copies the boot image to the PCIe endpoint's memory region and
>  writes the necessary control words to signal image transfer completion.
>  
> +A-Core No-SPL Boot Mode
> +----------------
> +
> +A-Core No-SPL Boot Mode on J784S4 platforms is a boot approach that bypasses
> +the A72 SPL while retaining U-Boot in the boot flow. This mode provides faster
> +boot times compared to normal boot while maintaining U-Boot's flexibility for
> +kernel loading and system configuration.
> +
> +**Key differences from Normal Boot:**
> +
> +* Skips A72 SPL execution
> +* U-Boot binary included in tinospl.bin alongside TFA, OP-TEE, and DM
> +* U-Boot loads at CONFIG_TEXT_BASE=0x80080000 (A72 SPL's earlier load location)
> +
> +Boot Flow
> +^^^^^^^^^
> +
> +**Normal boot flow:**
> +
> +.. code-block::
> +
> +             | tiboot3.bin |         tispl.bin          | u-boot.img |  Image  |
> +             |-------------+----------------------------+------------+---------|
> +    R5 Core  |    SPL      |                            |            |         |
> +    ---------|       \     |                            |            |         |
> +    A72 Core |        ------> TFA -> OP-TEE -> A72 SPL -->  U-Boot  --> Kernel |
> +
> +**With  A-Core no-SPL boot mode:**
> +
> +.. code-block::
> +
> +             | tiboot3.bin |        tinospl.bin          |  Image  |
> +             |-------------+-----------------------------+---------|
> +    R5 Core  |    SPL      |                             |         |
> +    ---------|       \     |                             |         |
> +    A72 Core |        ------> TFA -> OP-TEE -> DM -> U-Boot --> Kernel |

Why would DM need to run on any of the Cortex-A cores in this boot mode?

> +
> +Build Process
> +^^^^^^^^^^^^^
> +
> +Enabling A-Core no-SPL boot mode requires re-building U-Boot as follows:
> +
> +0. Setup environment variables:
> +"""""""""""""""""""""""""""""""
> +
> +Refer to the build procedure above for setting up the environment variables.
> +
> +1. U-Boot:
> +""""""""""
> +
> +* **1.1 R5:**
> +
> +.. prompt:: bash $
> +
> + # use the no-SPL config fragment for K3 platforms
> + export UBOOT_NOSPL_CFG_FRAGMENTR="k3_r5_nospl.config"
> + export UBOOT_CFG_CORTEXR="${UBOOT_CFG_CORTEXR} ${UBOOT_NOSPL_CFG_FRAGMENTR}"
> +
> +.. include::  k3.rst
> +    :start-after: .. k3_rst_include_start_build_steps_spl_r5
> +    :end-before: .. k3_rst_include_end_build_steps_spl_r5
> +
> +* **1.2 A72:**
> +
> +.. prompt:: bash $
> +
> + # use the no-SPL config fragment for A72
> + export UBOOT_NOSPL_CFG_FRAGMENTA="k3_a72_nospl.config"
> + export UBOOT_CFG_CORTEXA="${UBOOT_CFG_CORTEXA} ${UBOOT_NOSPL_CFG_FRAGMENTA}"
> +
> +.. include::  k3.rst
> +    :start-after: .. k3_rst_include_start_build_steps_uboot
> +    :end-before: .. k3_rst_include_end_build_steps_uboot
> +
> +.. note::
> +
> +    The ``tinospl.bin`` file is automatically generated by binman during
> +    the A72 U-Boot build process. This binary contains TFA, OP-TEE, DM, and
> +    the U-Boot binary with its device tree.
> +
> +Usage
> +^^^^^
> +
> +A-Core No-SPL Boot Mode uses a specialized binary called ``tinospl.bin`` which
> +contains all necessary components to boot directly to U-Boot without loading
> +the A72 SPL.
> +
> +**tinospl.bin structure:**
> +
> +The tinospl.bin is a FIT image containing:
> +
> +* **ATF (ARM Trusted Firmware)** - loaded at CONFIG_K3_ATF_LOAD_ADDR
> +* **OP-TEE** - loaded at CONFIG_K3_OPTEE_LOAD_ADDR
> +* **DM (Device Manager)** - loaded at 0x89000000
> +* **U-Boot** - loaded at CONFIG_TEXT_BASE (0x80080000)
> +* **DTB (Device Tree Blob)** - U-Boot device tree
> +
> +The R5 SPL requires both ``tiboot3.bin`` and ``tinospl.bin`` to be present
> +in the boot partition (first partition) of the MMC device. By default, the SD
> +card boot partition is used (``mmcdev=1``). The ``bootpart`` environment variable
> +defaults to 1:2, specifying the second partition of the SD card.
> +
> +To use eMMC instead of SD as the boot media, rebuild the R5 SPL with the
> +following diff:
> +
> +.. code-block:: diff
> +
> +    diff --git a/board/ti/j784s4/j784s4.env b/board/ti/j784s4/j784s4.env
> +    index 82b9f0741bb..73d59ac425c 100644
> +    --- a/board/ti/j784s4/j784s4.env
> +    +++ b/board/ti/j784s4/j784s4.env
> +    @@ -17,8 +17,8 @@ run_kern=booti ${loadaddr} ${rd_spec} ${fdtaddr}
> +
> +     boot_targets=mmc1 mmc0 usb pxe dhcp
> +     boot=mmc
> +    -mmcdev=1
> +    -bootpart=1:2
> +    +mmcdev=0
> +    +bootpart=0:2
> +     bootdir=/boot
> +     rd_spec=-
> +

Does this still work? Long ago we moved all of TI's reference boards to 
use the stdboot flow[0].

~Bryan

[0] https://git.u-boot-project.org/u-boot/u-boot/-/blob/main/configs/j784s4_evm_a72_defconfig?ref_type=heads#L34

Re: [PATCH v3 3/3] doc: ti: document A Core no-SPL boot mode for J784S4 EVM

[Gokul Praveen]

Hi Bryan,

On 01/09/26 21:50, Bryan Brattlof wrote:
> On August 19, 2026 thus sayeth Gokul Praveen:
>> This patch adds user documentation for the A Core no-SPL boot mode
>> on J784S4 EVM, where R5 SPL directly loads U-Boot proper, bypassing
>> the A Core SPL stage.
>>
>> The documentation covers the boot flow, build steps, and usage
>> instructions for this boot mode using tinospl.bin.
>>
>> Signed-off-by: Gokul Praveen <g-praveen@ti.com>
>> ---
>>   doc/board/ti/j784s4_evm.rst | 143 ++++++++++++++++++++++++++++++++++++
>>   1 file changed, 143 insertions(+)
>>
>> diff --git a/doc/board/ti/j784s4_evm.rst b/doc/board/ti/j784s4_evm.rst
>> index ec82228ab90..cf870066291 100644
>> --- a/doc/board/ti/j784s4_evm.rst
>> +++ b/doc/board/ti/j784s4_evm.rst
>> @@ -637,6 +637,149 @@ to the J784S4 endpoint:
>>   This program copies the boot image to the PCIe endpoint's memory region and
>>   writes the necessary control words to signal image transfer completion.
>>   
>> +A-Core No-SPL Boot Mode
>> +----------------
>> +
>> +A-Core No-SPL Boot Mode on J784S4 platforms is a boot approach that bypasses
>> +the A72 SPL while retaining U-Boot in the boot flow. This mode provides faster
>> +boot times compared to normal boot while maintaining U-Boot's flexibility for
>> +kernel loading and system configuration.
>> +
>> +**Key differences from Normal Boot:**
>> +
>> +* Skips A72 SPL execution
>> +* U-Boot binary included in tinospl.bin alongside TFA, OP-TEE, and DM
>> +* U-Boot loads at CONFIG_TEXT_BASE=0x80080000 (A72 SPL's earlier load location)
>> +
>> +Boot Flow
>> +^^^^^^^^^
>> +
>> +**Normal boot flow:**
>> +
>> +.. code-block::
>> +
>> +             | tiboot3.bin |         tispl.bin          | u-boot.img |  Image  |
>> +             |-------------+----------------------------+------------+---------|
>> +    R5 Core  |    SPL      |                            |            |         |
>> +    ---------|       \     |                            |            |         |
>> +    A72 Core |        ------> TFA -> OP-TEE -> A72 SPL -->  U-Boot  --> Kernel |
>> +
>> +**With  A-Core no-SPL boot mode:**
>> +
>> +.. code-block::
>> +
>> +             | tiboot3.bin |        tinospl.bin          |  Image  |
>> +             |-------------+-----------------------------+---------|
>> +    R5 Core  |    SPL      |                             |         |
>> +    ---------|       \     |                             |         |
>> +    A72 Core |        ------> TFA -> OP-TEE -> DM -> U-Boot --> Kernel |
> Why would DM need to run on any of the Cortex-A cores in this boot mode?
Appologies for that, it was a mistake in the documentation. I will 
update that.
>> +
>> +Build Process
>> +^^^^^^^^^^^^^
>> +
>> +Enabling A-Core no-SPL boot mode requires re-building U-Boot as follows:
>> +
>> +0. Setup environment variables:
>> +"""""""""""""""""""""""""""""""
>> +
>> +Refer to the build procedure above for setting up the environment variables.
>> +
>> +1. U-Boot:
>> +""""""""""
>> +
>> +* **1.1 R5:**
>> +
>> +.. prompt:: bash $
>> +
>> + # use the no-SPL config fragment for K3 platforms
>> + export UBOOT_NOSPL_CFG_FRAGMENTR="k3_r5_nospl.config"
>> + export UBOOT_CFG_CORTEXR="${UBOOT_CFG_CORTEXR} ${UBOOT_NOSPL_CFG_FRAGMENTR}"
>> +
>> +.. include::  k3.rst
>> +    :start-after: .. k3_rst_include_start_build_steps_spl_r5
>> +    :end-before: .. k3_rst_include_end_build_steps_spl_r5
>> +
>> +* **1.2 A72:**
>> +
>> +.. prompt:: bash $
>> +
>> + # use the no-SPL config fragment for A72
>> + export UBOOT_NOSPL_CFG_FRAGMENTA="k3_a72_nospl.config"
>> + export UBOOT_CFG_CORTEXA="${UBOOT_CFG_CORTEXA} ${UBOOT_NOSPL_CFG_FRAGMENTA}"
>> +
>> +.. include::  k3.rst
>> +    :start-after: .. k3_rst_include_start_build_steps_uboot
>> +    :end-before: .. k3_rst_include_end_build_steps_uboot
>> +
>> +.. note::
>> +
>> +    The ``tinospl.bin`` file is automatically generated by binman during
>> +    the A72 U-Boot build process. This binary contains TFA, OP-TEE, DM, and
>> +    the U-Boot binary with its device tree.
>> +
>> +Usage
>> +^^^^^
>> +
>> +A-Core No-SPL Boot Mode uses a specialized binary called ``tinospl.bin`` which
>> +contains all necessary components to boot directly to U-Boot without loading
>> +the A72 SPL.
>> +
>> +**tinospl.bin structure:**
>> +
>> +The tinospl.bin is a FIT image containing:
>> +
>> +* **ATF (ARM Trusted Firmware)** - loaded at CONFIG_K3_ATF_LOAD_ADDR
>> +* **OP-TEE** - loaded at CONFIG_K3_OPTEE_LOAD_ADDR
>> +* **DM (Device Manager)** - loaded at 0x89000000
>> +* **U-Boot** - loaded at CONFIG_TEXT_BASE (0x80080000)
>> +* **DTB (Device Tree Blob)** - U-Boot device tree
>> +
>> +The R5 SPL requires both ``tiboot3.bin`` and ``tinospl.bin`` to be present
>> +in the boot partition (first partition) of the MMC device. By default, the SD
>> +card boot partition is used (``mmcdev=1``). The ``bootpart`` environment variable
>> +defaults to 1:2, specifying the second partition of the SD card.
>> +
>> +To use eMMC instead of SD as the boot media, rebuild the R5 SPL with the
>> +following diff:
>> +
>> +.. code-block:: diff
>> +
>> +    diff --git a/board/ti/j784s4/j784s4.env b/board/ti/j784s4/j784s4.env
>> +    index 82b9f0741bb..73d59ac425c 100644
>> +    --- a/board/ti/j784s4/j784s4.env
>> +    +++ b/board/ti/j784s4/j784s4.env
>> +    @@ -17,8 +17,8 @@ run_kern=booti ${loadaddr} ${rd_spec} ${fdtaddr}
>> +
>> +     boot_targets=mmc1 mmc0 usb pxe dhcp
>> +     boot=mmc
>> +    -mmcdev=1
>> +    -bootpart=1:2
>> +    +mmcdev=0
>> +    +bootpart=0:2
>> +     bootdir=/boot
>> +     rd_spec=-
>> +
> Does this still work? Long ago we moved all of TI's reference boards to
> use the stdboot flow[0].

Yes, this still works, Bryan.

Regards

Gokul Praveen

> ~Bryan
>
> [0] https://git.u-boot-project.org/u-boot/u-boot/-/blob/main/configs/j784s4_evm_a72_defconfig?ref_type=heads#L34

Re: [PATCH v3 0/3] A-core no-SPL Boot Support

[Gokul Praveen]

Hi Tom,

Apologies for the reminder. Hope I have clarified your queries.

Best Regards

Gokul Praveen

On 19/08/26 15:49, Gokul Praveen wrote:
> A-Core no-SPL Mode is a boot approach that bypasses
> the A Core SPL while retaining U-Boot in the boot flow.
> This mode provides faster boot times compared to normal boot
> while maintaining U-Boot's flexibility for kernel loading
> and system configuration..
>
> v3<==> v2
> ===========
> * Updated the naming convention used from "no-spl" to "A-core no-spl" to
> * make it more specific and clear..
> * Link to v2:https://lore.kernel.org/all/20260818115322.101705-1-g-praveen@ti.com/
>
> v2<==> v1
> ===========
> * Updated the naming convention used from "semi-falcon" to "no-spl".
> * Link to v1: https://lore.kernel.org/all/20260814102153.44487-1-g-praveen@ti.com/
>
> Boot logs link :
> https://gist.github.com/GokulPraveen2001/fef407a482e2dad30272006de557627c
>
> Gokul Praveen (3):
>    configs: add A-core no-SPL mode fragment for k3 devices
>    arm: k3-binman: add tinospl.bin for direct U-Boot boot
>    doc: ti: document A Core no-SPL boot mode for J784S4 EVM
>
>   Makefile                               |   2 +-
>   arch/arm/dts/k3-binman.dtsi            |  47 ++++++++
>   arch/arm/dts/k3-j784s4-binman.dtsi     |  65 +++++++++++
>   arch/arm/dts/k3-j784s4-evm-u-boot.dtsi |  14 +++
>   configs/k3_a72_nospl.config            |   1 +
>   configs/k3_r5_nospl.config             |   1 +
>   doc/board/ti/j784s4_evm.rst            | 143 +++++++++++++++++++++++++
>   7 files changed, 272 insertions(+), 1 deletion(-)
>   create mode 100644 configs/k3_a72_nospl.config
>   create mode 100644 configs/k3_r5_nospl.config
>

Re: [PATCH v3 0/3] A-core no-SPL Boot Support

[Bryan Brattlof]

On August 19, 2026 thus sayeth Gokul Praveen:
> A-Core no-SPL Mode is a boot approach that bypasses
> the A Core SPL while retaining U-Boot in the boot flow.
> This mode provides faster boot times compared to normal boot
> while maintaining U-Boot's flexibility for kernel loading
> and system configuration..
> 
> v3<==> v2
> ===========
> * Updated the naming convention used from "no-spl" to "A-core no-spl" to
> * make it more specific and clear..
> * Link to v2:https://lore.kernel.org/all/20260818115322.101705-1-g-praveen@ti.com/
> 
> v2<==> v1
> ===========
> * Updated the naming convention used from "semi-falcon" to "no-spl".
> * Link to v1: https://lore.kernel.org/all/20260814102153.44487-1-g-praveen@ti.com/
> 
> Boot logs link :
> https://gist.github.com/GokulPraveen2001/fef407a482e2dad30272006de557627c
> 
> Gokul Praveen (3):
>   configs: add A-core no-SPL mode fragment for k3 devices
>   arm: k3-binman: add tinospl.bin for direct U-Boot boot
>   doc: ti: document A Core no-SPL boot mode for J784S4 EVM
> 
>  Makefile                               |   2 +-
>  arch/arm/dts/k3-binman.dtsi            |  47 ++++++++
>  arch/arm/dts/k3-j784s4-binman.dtsi     |  65 +++++++++++
>  arch/arm/dts/k3-j784s4-evm-u-boot.dtsi |  14 +++
>  configs/k3_a72_nospl.config            |   1 +
>  configs/k3_r5_nospl.config             |   1 +

Please make sure to update the board/ti/*/MAINTAINERS entries for these 
config fragments.

~Bryan

Re: [PATCH v3 0/3] A-core no-SPL Boot Support

[Gokul Praveen]

Hi Bryan,

On 01/09/26 21:53, Bryan Brattlof wrote:
> On August 19, 2026 thus sayeth Gokul Praveen:
>> A-Core no-SPL Mode is a boot approach that bypasses
>> the A Core SPL while retaining U-Boot in the boot flow.
>> This mode provides faster boot times compared to normal boot
>> while maintaining U-Boot's flexibility for kernel loading
>> and system configuration..
>>
>> v3<==> v2
>> ===========
>> * Updated the naming convention used from "no-spl" to "A-core no-spl" to
>> * make it more specific and clear..
>> * Link to v2:https://lore.kernel.org/all/20260818115322.101705-1-g-praveen@ti.com/
>>
>> v2<==> v1
>> ===========
>> * Updated the naming convention used from "semi-falcon" to "no-spl".
>> * Link to v1: https://lore.kernel.org/all/20260814102153.44487-1-g-praveen@ti.com/
>>
>> Boot logs link :
>> https://gist.github.com/GokulPraveen2001/fef407a482e2dad30272006de557627c
>>
>> Gokul Praveen (3):
>>    configs: add A-core no-SPL mode fragment for k3 devices
>>    arm: k3-binman: add tinospl.bin for direct U-Boot boot
>>    doc: ti: document A Core no-SPL boot mode for J784S4 EVM
>>
>>   Makefile                               |   2 +-
>>   arch/arm/dts/k3-binman.dtsi            |  47 ++++++++
>>   arch/arm/dts/k3-j784s4-binman.dtsi     |  65 +++++++++++
>>   arch/arm/dts/k3-j784s4-evm-u-boot.dtsi |  14 +++
>>   configs/k3_a72_nospl.config            |   1 +
>>   configs/k3_r5_nospl.config             |   1 +
> Please make sure to update the board/ti/*/MAINTAINERS entries for these
> config fragments.

Got it, do you recommend creating a separate MAINTAINERS folder

in the board/ti folder and adding my name under some TI BOOTFLOWS 
heading with subheading as

A-Core no-SPL mode or do you instead  recommend adding TI BOOTFLOWS 
heading with subheading as

A-Core no-SPL mode inside all the board/ti/*/MAINTAINERS files.

Best Regards

Gokul Praveen

>
> ~Bryan

Re: [PATCH v3 0/3] A-core no-SPL Boot Support

[Bryan Brattlof]

On September  2, 2026 thus sayeth Gokul Praveen:
> Hi Bryan,
> 
> On 01/09/26 21:53, Bryan Brattlof wrote:
> > On August 19, 2026 thus sayeth Gokul Praveen:
> > > A-Core no-SPL Mode is a boot approach that bypasses
> > > the A Core SPL while retaining U-Boot in the boot flow.
> > > This mode provides faster boot times compared to normal boot
> > > while maintaining U-Boot's flexibility for kernel loading
> > > and system configuration..
> > > 
> > > v3<==> v2
> > > ===========
> > > * Updated the naming convention used from "no-spl" to "A-core no-spl" to
> > > * make it more specific and clear..
> > > * Link to v2:https://lore.kernel.org/all/20260818115322.101705-1-g-praveen@ti.com/
> > > 
> > > v2<==> v1
> > > ===========
> > > * Updated the naming convention used from "semi-falcon" to "no-spl".
> > > * Link to v1: https://lore.kernel.org/all/20260814102153.44487-1-g-praveen@ti.com/
> > > 
> > > Boot logs link :
> > > https://gist.github.com/GokulPraveen2001/fef407a482e2dad30272006de557627c
> > > 
> > > Gokul Praveen (3):
> > >    configs: add A-core no-SPL mode fragment for k3 devices
> > >    arm: k3-binman: add tinospl.bin for direct U-Boot boot
> > >    doc: ti: document A Core no-SPL boot mode for J784S4 EVM
> > > 
> > >   Makefile                               |   2 +-
> > >   arch/arm/dts/k3-binman.dtsi            |  47 ++++++++
> > >   arch/arm/dts/k3-j784s4-binman.dtsi     |  65 +++++++++++
> > >   arch/arm/dts/k3-j784s4-evm-u-boot.dtsi |  14 +++
> > >   configs/k3_a72_nospl.config            |   1 +
> > >   configs/k3_r5_nospl.config             |   1 +
> > Please make sure to update the board/ti/*/MAINTAINERS entries for these
> > config fragments.
> 
> Got it, do you recommend creating a separate MAINTAINERS folder
> 
> in the board/ti folder and adding my name under some TI BOOTFLOWS heading
> with subheading as
> 
> A-Core no-SPL mode or do you instead  recommend adding TI BOOTFLOWS heading
> with subheading as
> 
> A-Core no-SPL mode inside all the board/ti/*/MAINTAINERS files.

As long as one board has it covered we should be good. Because this 
looks to only be for the J784S4-EVM I would suggest adding them to the 
EVM block inside board/ti/j784s4/MAINTAINERS

~Bryan

Re: [PATCH v3 0/3] A-core no-SPL Boot Support

[Gokul Praveen]

Hi Bryan.

On 02/09/26 19:15, Bryan Brattlof wrote:
> On September  2, 2026 thus sayeth Gokul Praveen:
>> Hi Bryan,
>>
>> On 01/09/26 21:53, Bryan Brattlof wrote:
>>> On August 19, 2026 thus sayeth Gokul Praveen:
>>>> A-Core no-SPL Mode is a boot approach that bypasses
>>>> the A Core SPL while retaining U-Boot in the boot flow.
>>>> This mode provides faster boot times compared to normal boot
>>>> while maintaining U-Boot's flexibility for kernel loading
>>>> and system configuration..
>>>>
>>>> v3<==> v2
>>>> ===========
>>>> * Updated the naming convention used from "no-spl" to "A-core no-spl" to
>>>> * make it more specific and clear..
>>>> * Link to v2:https://lore.kernel.org/all/20260818115322.101705-1-g-praveen@ti.com/
>>>>
>>>> v2<==> v1
>>>> ===========
>>>> * Updated the naming convention used from "semi-falcon" to "no-spl".
>>>> * Link to v1: https://lore.kernel.org/all/20260814102153.44487-1-g-praveen@ti.com/
>>>>
>>>> Boot logs link :
>>>> https://gist.github.com/GokulPraveen2001/fef407a482e2dad30272006de557627c
>>>>
>>>> Gokul Praveen (3):
>>>>     configs: add A-core no-SPL mode fragment for k3 devices
>>>>     arm: k3-binman: add tinospl.bin for direct U-Boot boot
>>>>     doc: ti: document A Core no-SPL boot mode for J784S4 EVM
>>>>
>>>>    Makefile                               |   2 +-
>>>>    arch/arm/dts/k3-binman.dtsi            |  47 ++++++++
>>>>    arch/arm/dts/k3-j784s4-binman.dtsi     |  65 +++++++++++
>>>>    arch/arm/dts/k3-j784s4-evm-u-boot.dtsi |  14 +++
>>>>    configs/k3_a72_nospl.config            |   1 +
>>>>    configs/k3_r5_nospl.config             |   1 +
>>> Please make sure to update the board/ti/*/MAINTAINERS entries for these
>>> config fragments.
>> Got it, do you recommend creating a separate MAINTAINERS folder
>>
>> in the board/ti folder and adding my name under some TI BOOTFLOWS heading
>> with subheading as
>>
>> A-Core no-SPL mode or do you instead  recommend adding TI BOOTFLOWS heading
>> with subheading as
>>
>> A-Core no-SPL mode inside all the board/ti/*/MAINTAINERS files.
> As long as one board has it covered we should be good. Because this
> looks to only be for the J784S4-EVM I would suggest adding them to the
> EVM block inside board/ti/j784s4/MAINTAINERS

Sure , I will do that. Can you also put a "reviewed by" if possible

so that I can add that while sending the v4 patch.

Regards

Gokul Praveen

>
> ~Bryan