From: "Hajda, Andrzej" <andrzej.hajda@intel.com>
To: Sujaritha Sundaresan <sujaritha.sundaresan@intel.com>,
<igt-dev@lists.freedesktop.org>
Cc: <zbigniew.kempczynski@intel.com>
Subject: Re: [PATCH i-g-t 1/2] lib/intel_pat: add intel_pat_has_wt()
Date: Tue, 8 Sep 2026 08:09:14 +0200 [thread overview]
Message-ID: <5deb564d-42cf-4cf1-acdc-d82f763481cf@intel.com> (raw)
In-Reply-To: <20260904085650.98553-2-sujaritha.sundaresan@intel.com>
W dniu 4.09.2026 o 10:56, Sujaritha Sundaresan pisze:
> Not every platform has a write-through entry in its PAT table. Where
> there is none the KMD reports the UC index for XE_CACHE_WT, so a test
> which asks for write-through quietly gets uncached instead. Spotting
> that currently means enumerating IP versions in the test, which needs
> touching again for every platform added.
>
> Add intel_pat_has_wt(), which answers the same question from the PAT
> config itself: a WT index which aliases UC means there is no distinct
> write-through entry to test. No functional change; the first user is
> the next patch.
>
> Signed-off-by: Sujaritha Sundaresan <sujaritha.sundaresan@intel.com>
> ---
> lib/intel_pat.c | 22 ++++++++++++++++++++++
> lib/intel_pat.h | 2 ++
> 2 files changed, 24 insertions(+)
>
> diff --git a/lib/intel_pat.c b/lib/intel_pat.c
> index 2f35bb772..782201029 100644
> --- a/lib/intel_pat.c
> +++ b/lib/intel_pat.c
> @@ -284,6 +284,28 @@ uint8_t intel_get_pat_idx_uc_comp(int fd)
> return pat.uc_comp;
> }
>
> +/**
> + * intel_pat_has_wt - Check whether the platform has a write-through PAT index
> + *
> + * @fd: DRM device fd
> + *
> + * Platforms with no write-through entry in their PAT table report the UC
> + * index for XE_CACHE_WT, so a WT index which aliases UC means there is no
> + * write-through mode to exercise. Deriving this from the PAT config rather
> + * than from a list of IP versions keeps it working for platforms added
> + * later.
> + *
> + * Returns: true if the platform has a distinct write-through pat_index
> + */
> +bool intel_pat_has_wt(int fd)
For getters convention is intel_get_pat_idx_*
So maybe intel_has_pat_wt ?
Up to you.
Reviewed-by: Andrzej Hajda <andrzej.hajda@intel.com>
Regards
Andrzej
> +{
> + struct intel_pat_cache pat = {};
> +
> + intel_get_pat_idx(fd, &pat);
> +
> + return pat.wt != pat.uc;
> +}
> +
> uint8_t intel_get_pat_idx_wt(int fd)
> {
> struct intel_pat_cache pat = {};
> diff --git a/lib/intel_pat.h b/lib/intel_pat.h
> index a31b60e86..824f8931e 100644
> --- a/lib/intel_pat.h
> +++ b/lib/intel_pat.h
> @@ -37,6 +37,8 @@ uint8_t intel_get_pat_idx_wb(int fd);
>
> uint8_t intel_get_pat_idx_uc_comp(int fd);
>
> +bool intel_pat_has_wt(int fd);
> +
> int32_t xe_get_pat_sw_config(int drm_fd, struct intel_pat_cache *xe_pat_cache, int gt);
> int32_t xe_get_pat_hw_config(int drm_fd, struct intel_pat_cache *xe_pat_cache, int gt);
>
next prev parent reply other threads:[~2026-09-08 6:10 UTC|newest]
Thread overview: 9+ messages / expand[flat|nested] mbox.gz Atom feed top
2026-09-04 8:56 [PATCH i-g-t 0/2] Derive write-through availability from the PAT config Sujaritha Sundaresan
2026-09-04 8:56 ` [PATCH i-g-t 1/2] lib/intel_pat: add intel_pat_has_wt() Sujaritha Sundaresan
2026-09-08 6:09 ` Hajda, Andrzej [this message]
2026-09-08 6:21 ` Sundaresan, Sujaritha
2026-09-04 8:56 ` [PATCH i-g-t 2/2] tests/intel/xe_pat: skip the write-through checks without a WT index Sujaritha Sundaresan
2026-09-08 6:18 ` Hajda, Andrzej
2026-09-04 9:33 ` ✓ Xe.CI.BAT: success for Derive write-through availability from the PAT config Patchwork
2026-09-04 9:43 ` ✗ i915.CI.BAT: failure " Patchwork
2026-09-04 20:10 ` ✗ Xe.CI.FULL: " Patchwork
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