Re: [PATCH i-g-t 2/2] tests/intel/xe_pat: skip the write-through checks without a WT index

["Hajda, Andrzej" <andrzej.hajda@intel.com>]

W dniu 4.09.2026 o 10:56, Sujaritha Sundaresan pisze:
> On platforms with no write-through entry in the PAT table
> intel_get_pat_idx_wt() hands back the UC index, so userptr-coh-none,
> pat-index-all and l2-flush-opt-svm-pat-restrict each repeat their UC
> check under a "wt" label and report coverage they do not have.
> 
> Gate those three on intel_pat_has_wt() so the write-through checks only
> run where a distinct write-through index exists. Platforms which do have
> one are unaffected.
> 
> Signed-off-by: Sujaritha Sundaresan <sujaritha.sundaresan@intel.com>

Reviewed-by: Andrzej Hajda <andrzej.hajda@intel.com>

Regards
Andrzej

> ---
>   tests/intel/xe_pat.c | 38 ++++++++++++++++++++++----------------
>   1 file changed, 22 insertions(+), 16 deletions(-)
> 
> diff --git a/tests/intel/xe_pat.c b/tests/intel/xe_pat.c
> index 9dd4ffb69..060e65aa0 100644
> --- a/tests/intel/xe_pat.c
> +++ b/tests/intel/xe_pat.c
> @@ -86,10 +86,11 @@ static void userptr_coh_none(int fd)
>   				   size, DRM_XE_VM_BIND_OP_MAP_USERPTR, 0, NULL, 0, 0,
>   				   intel_get_pat_idx_uc(fd), 0),
>   		      -EINVAL);
> -	igt_assert_eq(__xe_vm_bind(fd, vm, 0, 0, to_user_pointer(data), 0x40000,
> -				   size, DRM_XE_VM_BIND_OP_MAP_USERPTR, 0, NULL, 0, 0,
> -				   intel_get_pat_idx_wt(fd), 0),
> -		      -EINVAL);
> +	if (intel_pat_has_wt(fd))
> +		igt_assert_eq(__xe_vm_bind(fd, vm, 0, 0, to_user_pointer(data), 0x40000,
> +					   size, DRM_XE_VM_BIND_OP_MAP_USERPTR, 0, NULL, 0, 0,
> +					   intel_get_pat_idx_wt(fd), 0),
> +			      -EINVAL);
>   	igt_assert_eq(__xe_vm_bind(fd, vm, 0, 0, to_user_pointer(data), 0x40000,
>   				   size, DRM_XE_VM_BIND_OP_MAP_USERPTR, 0, NULL, 0, 0,
>   				   XE_PAT_IDX_XA_UC, 0),
> @@ -323,6 +324,7 @@ static void pat_sw_hw_compare(int fd, enum pat_test_opts opts)
>    */
>   static void pat_index_all(int fd)
>   {
> +	bool has_wt = intel_pat_has_wt(fd);
>   	size_t size = xe_get_default_alignment(fd);
>   	struct intel_pat_cache pat_sw_config = {};
>   	uint32_t vm, bo;
> @@ -339,11 +341,13 @@ static void pat_index_all(int fd)
>   		      0);
>   	xe_vm_unbind_sync(fd, vm, 0, 0x40000, size);
>   
> -	igt_assert_eq(__xe_vm_bind(fd, vm, 0, bo, 0, 0x40000,
> -				   size, DRM_XE_VM_BIND_OP_MAP, 0, NULL, 0, 0,
> -				   intel_get_pat_idx_wt(fd), 0),
> -		      0);
> -	xe_vm_unbind_sync(fd, vm, 0, 0x40000, size);
> +	if (has_wt) {
> +		igt_assert_eq(__xe_vm_bind(fd, vm, 0, bo, 0, 0x40000,
> +					   size, DRM_XE_VM_BIND_OP_MAP, 0, NULL, 0, 0,
> +					   intel_get_pat_idx_wt(fd), 0),
> +			      0);
> +		xe_vm_unbind_sync(fd, vm, 0, 0x40000, size);
> +	}
>   
>   	igt_assert_eq(__xe_vm_bind(fd, vm, 0, bo, 0, 0x40000,
>   				   size, DRM_XE_VM_BIND_OP_MAP, 0, NULL, 0, 0,
> @@ -413,10 +417,11 @@ static void pat_index_all(int fd)
>   				   intel_get_pat_idx_uc(fd), 0),
>   		      -EINVAL);
>   
> -	igt_assert_eq(__xe_vm_bind(fd, vm, 0, bo, 0, 0x40000,
> -				   size, DRM_XE_VM_BIND_OP_MAP, 0, NULL, 0, 0,
> -				   intel_get_pat_idx_wt(fd), 0),
> -		      -EINVAL);
> +	if (has_wt)
> +		igt_assert_eq(__xe_vm_bind(fd, vm, 0, bo, 0, 0x40000,
> +					   size, DRM_XE_VM_BIND_OP_MAP, 0, NULL, 0, 0,
> +					   intel_get_pat_idx_wt(fd), 0),
> +			      -EINVAL);
>   
>   	igt_assert_eq(__xe_vm_bind(fd, vm, 0, bo, 0, 0x40000,
>   				   size, DRM_XE_VM_BIND_OP_MAP, 0, NULL, 0, 0,
> @@ -878,9 +883,10 @@ static void l2_flush_opt_svm_pat_restrict(int fd)
>   					0, DRM_XE_MEM_RANGE_ATTR_PAT,
>   					intel_get_pat_idx_uc(fd), 0, 0), -EINVAL);
>   
> -	igt_assert_eq(__xe_vm_madvise(fd, vm, to_user_pointer(buffer), size,
> -					0, DRM_XE_MEM_RANGE_ATTR_PAT,
> -					intel_get_pat_idx_wt(fd), 0, 0), -EINVAL);
> +	if (intel_pat_has_wt(fd))
> +		igt_assert_eq(__xe_vm_madvise(fd, vm, to_user_pointer(buffer), size,
> +					      0, DRM_XE_MEM_RANGE_ATTR_PAT,
> +					      intel_get_pat_idx_wt(fd), 0, 0), -EINVAL);
>   
>   	igt_assert_eq(__xe_vm_madvise(fd, vm, to_user_pointer(buffer), size,
>   					0, DRM_XE_MEM_RANGE_ATTR_PAT,