Re: [PATCH 5/7] media: verisilicon: Add Rockchip VPU720 JPEG decoder

From: Nicolas Dufresne <nicolas.dufresne@collabora.com>
To: Sascha Hauer <s.hauer@pengutronix.de>
Cc: Benjamin Gaignard <benjamin.gaignard@collabora.com>,
	Philipp Zabel	 <p.zabel@pengutronix.de>,
	Mauro Carvalho Chehab <mchehab@kernel.org>,
	Heiko Stuebner <heiko@sntech.de>,
	Ezequiel Garcia <ezequiel@vanguardiasur.com.ar>,
	Andrzej Pietrasiewicz	 <andrzej.p@collabora.com>,
	Hans Verkuil <hverkuil@kernel.org>,
	Chen-Yu Tsai <wenst@chromium.org>, Rob Herring <robh@kernel.org>,
	Krzysztof Kozlowski	 <krzk+dt@kernel.org>,
	Conor Dooley <conor+dt@kernel.org>,
	Lucas Sinn	 <lucas.sinn@wolfvision.net>,
	Mauro Carvalho Chehab <mchehab+huawei@kernel.org>,
		linux-media@vger.kernel.org, linux-rockchip@lists.infradead.org,
		linux-kernel@vger.kernel.org,
	linux-arm-kernel@lists.infradead.org,
		devicetree@vger.kernel.org
Subject: Re: [PATCH 5/7] media: verisilicon: Add Rockchip VPU720 JPEG decoder
Date: Thu, 20 Aug 2026 12:02:20 -0400	[thread overview]
Message-ID: <61537689daa428a577e6bdab794d044f5405128e.camel@collabora.com> (raw)
In-Reply-To: <5436875c-9724-41f3-aaf9-76d43e05f0a8@pengutronix.de>

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Hi Sascha,

Le jeudi 20 août 2026 à 10:03 +0000, Sascha Hauer a écrit :
> On 2026-08-19 11:48, Nicolas Dufresne wrote:
> > Hi Sascha,
> > 
> > Le mercredi 19 août 2026 à 12:37 +0200, Sascha Hauer a écrit :
> > > +/* ------------------------------------------------------------------ */
> > > +/* Register byte offsets from dec_base                                 */
> > > +/* ------------------------------------------------------------------ */
> > > +
> > > +/* REG0: IP version / product ID */
> > > +#define VDPU720_REG_VERSION		0x000
> > > +#define VDPU720_PROD_NUM		GENMASK(31, 16)
> > > +#define VDPU720_BIT_DEPTH		BIT(8)
> > 
> > Can you share a dump and share these register reset values. Looking at the
> > layout, clearly its highly modified, but probably derived from VSI multi-codec,
> > but I'm thinking perhaps we'll learn more from that. Its always nice to justify
> > when adding more chips that are not strictly VSI designs (or maybe it is) to the
> > hantro dirver.
> 
> Here's a full register dump right after reset:
> 
> 00000000: db1f0005 00000004 00120000 00000000

I've look around as much as I could, and could not find any indication that this
is an IP from VSI or derived from a VSI core. It is entirely different from
vdpu1 in mpp (proper G1, rk3288 and similar) and vdpu2 (modified G1 / VDPU121).
In short, this is not a multi-codec core.

So that ball is on your end to show that this driver belongs to hantro rather
then its own driver. In absence of evidence, this driver should be part of
rockchip vendor folder, not vsi. Don't read me wrong, I trust that you have
tested what the LLM have chosen, but anything can be implement in Hantro really,
it does not mean it should be there.

Nicolas

> 00000010: 00004400 00000000 00000000 00000000
> 00000020: 00000000 00000000 00000000 00000000
> 00000030: 00000000 00000000 00000000 00000000
> 00000040: 000000ff 00000000 00000000 00000000
> 00000050: 00000000 00000000 00000000 00000000
> 00000060: 00000000 00000000 00000000 00000000
> 00000070: 00000000 00000000 000000a8 00000001
> 00000080: 00200000 00080f06 00000000 00000000
> 00000090: 00000000 00000000 00000000 00000000
> 000000a0: 00040000 00001556 00000000 00000000
> 000000b0: 00000000 00000000 00000000 00000000
> ...
> 000003f0: 00000000 00000000 00000000 00000000
> 
> Sascha

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