From: Krzysztof Kozlowski <krzk@kernel.org>
To: chuan.liu@amlogic.com, Neil Armstrong <neil.armstrong@linaro.org>,
Michael Turquette <mturquette@baylibre.com>,
Stephen Boyd <sboyd@kernel.org>, Rob Herring <robh@kernel.org>,
Krzysztof Kozlowski <krzk+dt@kernel.org>,
Conor Dooley <conor+dt@kernel.org>
Cc: linux-amlogic@lists.infradead.org, linux-clk@vger.kernel.org,
devicetree@vger.kernel.org, linux-kernel@vger.kernel.org
Subject: Re: [PATCH 05/13] clk: amlogic: Add composite clock driver
Date: Mon, 9 Feb 2026 14:18:03 +0100 [thread overview]
Message-ID: <63b2b403-53ea-465c-832d-8ee6099239aa@kernel.org> (raw)
In-Reply-To: <20260209-a9_clock_driver-v1-5-a9198dc03d2a@amlogic.com>
On 09/02/2026 06:48, Chuan Liu via B4 Relay wrote:
> From: Chuan Liu <chuan.liu@amlogic.com>
>
> Implement clk_ops support for Amlogic composite clocks. Composite clocks
> are commonly used clock control units in Amlogic SoCs that integrate
> multiplexer, divider, and gate functionality into a single block.
>
> Signed-off-by: Chuan Liu <chuan.liu@amlogic.com>
> ---
> drivers/clk/amlogic/Makefile | 1 +
> drivers/clk/amlogic/clk-composite.c | 280 ++++++++++++++++++++++++++++++++++++
> drivers/clk/amlogic/clk-composite.h | 20 +++
> drivers/clk/amlogic/clk.c | 7 +
> drivers/clk/amlogic/clk.h | 1 +
Why did you duplicate the directory? It's already there under name
meson. That's your vendor.
Best regards,
Krzysztof
_______________________________________________
linux-amlogic mailing list
linux-amlogic@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-amlogic
WARNING: multiple messages have this Message-ID (diff)
From: Krzysztof Kozlowski <krzk@kernel.org>
To: chuan.liu@amlogic.com, Neil Armstrong <neil.armstrong@linaro.org>,
Michael Turquette <mturquette@baylibre.com>,
Stephen Boyd <sboyd@kernel.org>, Rob Herring <robh@kernel.org>,
Krzysztof Kozlowski <krzk+dt@kernel.org>,
Conor Dooley <conor+dt@kernel.org>
Cc: linux-amlogic@lists.infradead.org, linux-clk@vger.kernel.org,
devicetree@vger.kernel.org, linux-kernel@vger.kernel.org
Subject: Re: [PATCH 05/13] clk: amlogic: Add composite clock driver
Date: Mon, 9 Feb 2026 14:18:03 +0100 [thread overview]
Message-ID: <63b2b403-53ea-465c-832d-8ee6099239aa@kernel.org> (raw)
In-Reply-To: <20260209-a9_clock_driver-v1-5-a9198dc03d2a@amlogic.com>
On 09/02/2026 06:48, Chuan Liu via B4 Relay wrote:
> From: Chuan Liu <chuan.liu@amlogic.com>
>
> Implement clk_ops support for Amlogic composite clocks. Composite clocks
> are commonly used clock control units in Amlogic SoCs that integrate
> multiplexer, divider, and gate functionality into a single block.
>
> Signed-off-by: Chuan Liu <chuan.liu@amlogic.com>
> ---
> drivers/clk/amlogic/Makefile | 1 +
> drivers/clk/amlogic/clk-composite.c | 280 ++++++++++++++++++++++++++++++++++++
> drivers/clk/amlogic/clk-composite.h | 20 +++
> drivers/clk/amlogic/clk.c | 7 +
> drivers/clk/amlogic/clk.h | 1 +
Why did you duplicate the directory? It's already there under name
meson. That's your vendor.
Best regards,
Krzysztof
next prev parent reply other threads:[~2026-02-09 13:18 UTC|newest]
Thread overview: 76+ messages / expand[flat|nested] mbox.gz Atom feed top
2026-02-09 5:48 [PATCH 00/13] clk: amlogic: Introduce A9 PLL and CCU driver support Chuan Liu
2026-02-09 5:48 ` Chuan Liu via B4 Relay
2026-02-09 5:48 ` Chuan Liu via B4 Relay
2026-02-09 5:48 ` [PATCH 01/13] dt-bindings: clock: Add Amlogic A9 standardized model clock control units Chuan Liu
2026-02-09 5:48 ` Chuan Liu via B4 Relay
2026-02-09 5:48 ` Chuan Liu via B4 Relay
2026-02-09 13:14 ` Krzysztof Kozlowski
2026-02-09 13:14 ` Krzysztof Kozlowski
2026-04-08 14:37 ` Chuan Liu
2026-04-08 14:37 ` Chuan Liu
2026-02-09 13:18 ` Krzysztof Kozlowski
2026-02-09 13:18 ` Krzysztof Kozlowski
2026-02-09 5:48 ` [PATCH 02/13] dt-bindings: clock: Add Amlogic A9 PLL controllers Chuan Liu
2026-02-09 5:48 ` Chuan Liu via B4 Relay
2026-02-09 5:48 ` Chuan Liu via B4 Relay
2026-02-09 5:48 ` [PATCH 03/13] dt-bindings: clock: Add Amlogic A9 misc clock control units Chuan Liu
2026-02-09 5:48 ` Chuan Liu via B4 Relay
2026-02-09 5:48 ` Chuan Liu via B4 Relay
2026-02-09 13:15 ` Krzysztof Kozlowski
2026-02-09 13:15 ` Krzysztof Kozlowski
2026-02-09 5:48 ` [PATCH 04/13] clk: amlogic: Add basic clock driver Chuan Liu
2026-02-09 5:48 ` Chuan Liu via B4 Relay
2026-02-09 5:48 ` Chuan Liu via B4 Relay
2026-02-09 13:17 ` Krzysztof Kozlowski
2026-02-09 13:17 ` Krzysztof Kozlowski
2026-04-08 14:32 ` Chuan Liu
2026-04-08 14:32 ` Chuan Liu
2026-04-08 17:34 ` Jerome Brunet
2026-04-08 17:34 ` Jerome Brunet
2026-04-15 12:21 ` Chuan Liu
2026-04-15 12:21 ` Chuan Liu
2026-04-09 6:12 ` Krzysztof Kozlowski
2026-04-09 6:12 ` Krzysztof Kozlowski
2026-04-15 11:40 ` Chuan Liu
2026-04-15 11:40 ` Chuan Liu
2026-04-15 12:58 ` Krzysztof Kozlowski
2026-04-15 12:58 ` Krzysztof Kozlowski
2026-02-09 5:48 ` [PATCH 05/13] clk: amlogic: Add composite " Chuan Liu
2026-02-09 5:48 ` Chuan Liu via B4 Relay
2026-02-09 5:48 ` Chuan Liu via B4 Relay
2026-02-09 13:18 ` Krzysztof Kozlowski [this message]
2026-02-09 13:18 ` Krzysztof Kozlowski
2026-02-09 5:48 ` [PATCH 06/13] clk: amlogic: Add noglitch " Chuan Liu
2026-02-09 5:48 ` Chuan Liu via B4 Relay
2026-02-09 5:48 ` Chuan Liu via B4 Relay
2026-02-09 21:51 ` Martin Blumenstingl
2026-02-09 21:51 ` Martin Blumenstingl
2026-04-08 14:44 ` Chuan Liu
2026-04-08 14:44 ` Chuan Liu
2026-02-09 5:48 ` [PATCH 07/13] clk: amlogic: Add duandiv " Chuan Liu
2026-02-09 5:48 ` Chuan Liu via B4 Relay
2026-02-09 5:48 ` Chuan Liu via B4 Relay
2026-02-09 5:48 ` [PATCH 08/13] clk: amlogic: Add PLL driver Chuan Liu
2026-02-09 5:48 ` Chuan Liu via B4 Relay
2026-02-09 5:48 ` Chuan Liu via B4 Relay
2026-02-09 15:37 ` kernel test robot
2026-02-09 15:37 ` kernel test robot
2026-02-09 17:35 ` kernel test robot
2026-02-09 17:35 ` kernel test robot
2026-02-09 5:48 ` [PATCH 09/13] clk: amlogic: Add DT-based clock registration functions Chuan Liu
2026-02-09 5:48 ` Chuan Liu via B4 Relay
2026-02-09 5:48 ` Chuan Liu via B4 Relay
2026-02-09 5:48 ` [PATCH 10/13] clk: amlogic: Add A9 standardized model clock control units driver Chuan Liu
2026-02-09 5:48 ` Chuan Liu via B4 Relay
2026-02-09 5:48 ` Chuan Liu via B4 Relay
2026-02-09 5:48 ` [PATCH 11/13] clk: amlogic: Add A9 PLL controllers driver Chuan Liu
2026-02-09 5:48 ` Chuan Liu via B4 Relay
2026-02-09 5:48 ` Chuan Liu via B4 Relay
2026-02-09 5:48 ` [PATCH 12/13] clk: amlogic: Add A9 misc clock control units driver Chuan Liu
2026-02-09 5:48 ` Chuan Liu via B4 Relay
2026-02-09 5:48 ` Chuan Liu via B4 Relay
2026-02-09 5:48 ` [PATCH 13/13] clk: amlogic: Add support for building as combined kernel module Chuan Liu
2026-02-09 5:48 ` Chuan Liu via B4 Relay
2026-02-09 5:48 ` Chuan Liu via B4 Relay
2026-02-11 8:34 ` [PATCH 00/13] clk: amlogic: Introduce A9 PLL and CCU driver support Jerome Brunet
2026-02-11 8:34 ` Jerome Brunet
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