From: Chuan Liu <chuan.liu@amlogic.com>
To: Krzysztof Kozlowski <krzk@kernel.org>,
Neil Armstrong <neil.armstrong@linaro.org>,
Michael Turquette <mturquette@baylibre.com>,
Stephen Boyd <sboyd@kernel.org>, Rob Herring <robh@kernel.org>,
Krzysztof Kozlowski <krzk+dt@kernel.org>,
Conor Dooley <conor+dt@kernel.org>
Cc: linux-amlogic@lists.infradead.org, linux-clk@vger.kernel.org,
devicetree@vger.kernel.org, linux-kernel@vger.kernel.org,
Martin Blumenstingl <martin.blumenstingl@googlemail.com>
Subject: Re: [PATCH 04/13] clk: amlogic: Add basic clock driver
Date: Wed, 8 Apr 2026 22:32:56 +0800 [thread overview]
Message-ID: <76ef272c-e09a-400e-b381-82d7f29760ca@amlogic.com> (raw)
In-Reply-To: <89cc0724-32a8-4da5-8070-c128cafcfc82@kernel.org>
Hi Krzysztof (& ALL),
Thanks for review.
On 2/9/2026 9:17 PM, Krzysztof Kozlowski wrote:
> [ EXTERNAL EMAIL ]
>
> On 09/02/2026 06:48, Chuan Liu via B4 Relay wrote:
>> From: Chuan Liu <chuan.liu@amlogic.com>
>>
>> Implement core clock driver for Amlogic SoC platforms, supporting
>
> So how did all existing Amlogic SoC platforms work so far without basic
> clock driver? Really, how?
>
> You are suppose to grow existing code, not add your completely new
> "basic" driver just because you have it that way in downstream.
>
Firstly, apologies for the delayed response. I had intended to
consolidate the V1 review feedback and come back with a clearer plan for
V2 changes. In the meantime, Martin has provided many detailed and
valuable suggestions - much appreciated.
The original goal of optimizing the HW based on A9 and introducing a new
clock driver is to reduce unnecessary complexity in the driver. On A9,
we optimized the Clock/PLL controller HW to simplify driver performance,
complexity, memory footprint, and reusability. Improvements on the HW
side can also help drive corresponding enhancements in the driver:
- Performance: Encapsulates sub-clock functions, reducing call paths
- Complexity: Standardized register bits eliminate a large number of
bit definitions (~1/3 of original code is defined register bit [1])
- Memory: Object-oriented design avoids copy/paste for repeated clocks
- Reusability: Same controller works across SoCs without driver
changes (or with minimal changes)
The old meson driver required compromises to unify legacy controller
characteristics and driver styles. On A9, we want a fresh start.
> Best regards,
> Krzysztof
--
Best regards,
Chuan
_______________________________________________
linux-amlogic mailing list
linux-amlogic@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-amlogic
WARNING: multiple messages have this Message-ID (diff)
From: Chuan Liu <chuan.liu@amlogic.com>
To: Krzysztof Kozlowski <krzk@kernel.org>,
Neil Armstrong <neil.armstrong@linaro.org>,
Michael Turquette <mturquette@baylibre.com>,
Stephen Boyd <sboyd@kernel.org>, Rob Herring <robh@kernel.org>,
Krzysztof Kozlowski <krzk+dt@kernel.org>,
Conor Dooley <conor+dt@kernel.org>
Cc: linux-amlogic@lists.infradead.org, linux-clk@vger.kernel.org,
devicetree@vger.kernel.org, linux-kernel@vger.kernel.org,
Martin Blumenstingl <martin.blumenstingl@googlemail.com>
Subject: Re: [PATCH 04/13] clk: amlogic: Add basic clock driver
Date: Wed, 8 Apr 2026 22:32:56 +0800 [thread overview]
Message-ID: <76ef272c-e09a-400e-b381-82d7f29760ca@amlogic.com> (raw)
In-Reply-To: <89cc0724-32a8-4da5-8070-c128cafcfc82@kernel.org>
Hi Krzysztof (& ALL),
Thanks for review.
On 2/9/2026 9:17 PM, Krzysztof Kozlowski wrote:
> [ EXTERNAL EMAIL ]
>
> On 09/02/2026 06:48, Chuan Liu via B4 Relay wrote:
>> From: Chuan Liu <chuan.liu@amlogic.com>
>>
>> Implement core clock driver for Amlogic SoC platforms, supporting
>
> So how did all existing Amlogic SoC platforms work so far without basic
> clock driver? Really, how?
>
> You are suppose to grow existing code, not add your completely new
> "basic" driver just because you have it that way in downstream.
>
Firstly, apologies for the delayed response. I had intended to
consolidate the V1 review feedback and come back with a clearer plan for
V2 changes. In the meantime, Martin has provided many detailed and
valuable suggestions - much appreciated.
The original goal of optimizing the HW based on A9 and introducing a new
clock driver is to reduce unnecessary complexity in the driver. On A9,
we optimized the Clock/PLL controller HW to simplify driver performance,
complexity, memory footprint, and reusability. Improvements on the HW
side can also help drive corresponding enhancements in the driver:
- Performance: Encapsulates sub-clock functions, reducing call paths
- Complexity: Standardized register bits eliminate a large number of
bit definitions (~1/3 of original code is defined register bit [1])
- Memory: Object-oriented design avoids copy/paste for repeated clocks
- Reusability: Same controller works across SoCs without driver
changes (or with minimal changes)
The old meson driver required compromises to unify legacy controller
characteristics and driver styles. On A9, we want a fresh start.
> Best regards,
> Krzysztof
--
Best regards,
Chuan
next prev parent reply other threads:[~2026-04-08 14:33 UTC|newest]
Thread overview: 76+ messages / expand[flat|nested] mbox.gz Atom feed top
2026-02-09 5:48 [PATCH 00/13] clk: amlogic: Introduce A9 PLL and CCU driver support Chuan Liu
2026-02-09 5:48 ` Chuan Liu via B4 Relay
2026-02-09 5:48 ` Chuan Liu via B4 Relay
2026-02-09 5:48 ` [PATCH 01/13] dt-bindings: clock: Add Amlogic A9 standardized model clock control units Chuan Liu
2026-02-09 5:48 ` Chuan Liu via B4 Relay
2026-02-09 5:48 ` Chuan Liu via B4 Relay
2026-02-09 13:14 ` Krzysztof Kozlowski
2026-02-09 13:14 ` Krzysztof Kozlowski
2026-04-08 14:37 ` Chuan Liu
2026-04-08 14:37 ` Chuan Liu
2026-02-09 13:18 ` Krzysztof Kozlowski
2026-02-09 13:18 ` Krzysztof Kozlowski
2026-02-09 5:48 ` [PATCH 02/13] dt-bindings: clock: Add Amlogic A9 PLL controllers Chuan Liu
2026-02-09 5:48 ` Chuan Liu via B4 Relay
2026-02-09 5:48 ` Chuan Liu via B4 Relay
2026-02-09 5:48 ` [PATCH 03/13] dt-bindings: clock: Add Amlogic A9 misc clock control units Chuan Liu
2026-02-09 5:48 ` Chuan Liu via B4 Relay
2026-02-09 5:48 ` Chuan Liu via B4 Relay
2026-02-09 13:15 ` Krzysztof Kozlowski
2026-02-09 13:15 ` Krzysztof Kozlowski
2026-02-09 5:48 ` [PATCH 04/13] clk: amlogic: Add basic clock driver Chuan Liu
2026-02-09 5:48 ` Chuan Liu via B4 Relay
2026-02-09 5:48 ` Chuan Liu via B4 Relay
2026-02-09 13:17 ` Krzysztof Kozlowski
2026-02-09 13:17 ` Krzysztof Kozlowski
2026-04-08 14:32 ` Chuan Liu [this message]
2026-04-08 14:32 ` Chuan Liu
2026-04-08 17:34 ` Jerome Brunet
2026-04-08 17:34 ` Jerome Brunet
2026-04-15 12:21 ` Chuan Liu
2026-04-15 12:21 ` Chuan Liu
2026-04-09 6:12 ` Krzysztof Kozlowski
2026-04-09 6:12 ` Krzysztof Kozlowski
2026-04-15 11:40 ` Chuan Liu
2026-04-15 11:40 ` Chuan Liu
2026-04-15 12:58 ` Krzysztof Kozlowski
2026-04-15 12:58 ` Krzysztof Kozlowski
2026-02-09 5:48 ` [PATCH 05/13] clk: amlogic: Add composite " Chuan Liu
2026-02-09 5:48 ` Chuan Liu via B4 Relay
2026-02-09 5:48 ` Chuan Liu via B4 Relay
2026-02-09 13:18 ` Krzysztof Kozlowski
2026-02-09 13:18 ` Krzysztof Kozlowski
2026-02-09 5:48 ` [PATCH 06/13] clk: amlogic: Add noglitch " Chuan Liu
2026-02-09 5:48 ` Chuan Liu via B4 Relay
2026-02-09 5:48 ` Chuan Liu via B4 Relay
2026-02-09 21:51 ` Martin Blumenstingl
2026-02-09 21:51 ` Martin Blumenstingl
2026-04-08 14:44 ` Chuan Liu
2026-04-08 14:44 ` Chuan Liu
2026-02-09 5:48 ` [PATCH 07/13] clk: amlogic: Add duandiv " Chuan Liu
2026-02-09 5:48 ` Chuan Liu via B4 Relay
2026-02-09 5:48 ` Chuan Liu via B4 Relay
2026-02-09 5:48 ` [PATCH 08/13] clk: amlogic: Add PLL driver Chuan Liu
2026-02-09 5:48 ` Chuan Liu via B4 Relay
2026-02-09 5:48 ` Chuan Liu via B4 Relay
2026-02-09 15:37 ` kernel test robot
2026-02-09 15:37 ` kernel test robot
2026-02-09 17:35 ` kernel test robot
2026-02-09 17:35 ` kernel test robot
2026-02-09 5:48 ` [PATCH 09/13] clk: amlogic: Add DT-based clock registration functions Chuan Liu
2026-02-09 5:48 ` Chuan Liu via B4 Relay
2026-02-09 5:48 ` Chuan Liu via B4 Relay
2026-02-09 5:48 ` [PATCH 10/13] clk: amlogic: Add A9 standardized model clock control units driver Chuan Liu
2026-02-09 5:48 ` Chuan Liu via B4 Relay
2026-02-09 5:48 ` Chuan Liu via B4 Relay
2026-02-09 5:48 ` [PATCH 11/13] clk: amlogic: Add A9 PLL controllers driver Chuan Liu
2026-02-09 5:48 ` Chuan Liu via B4 Relay
2026-02-09 5:48 ` Chuan Liu via B4 Relay
2026-02-09 5:48 ` [PATCH 12/13] clk: amlogic: Add A9 misc clock control units driver Chuan Liu
2026-02-09 5:48 ` Chuan Liu via B4 Relay
2026-02-09 5:48 ` Chuan Liu via B4 Relay
2026-02-09 5:48 ` [PATCH 13/13] clk: amlogic: Add support for building as combined kernel module Chuan Liu
2026-02-09 5:48 ` Chuan Liu via B4 Relay
2026-02-09 5:48 ` Chuan Liu via B4 Relay
2026-02-11 8:34 ` [PATCH 00/13] clk: amlogic: Introduce A9 PLL and CCU driver support Jerome Brunet
2026-02-11 8:34 ` Jerome Brunet
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