Re: [PATCH v2 01/16] KVM: x86/pmu: Remove redundant Perf Global Status MSR bit definitions

["Mi, Dapeng" <dapeng1.mi@linux.intel.com>]

Thanks for this clean-up. This was what I intended to do for long time. :)

Reviewed-by: Dapeng Mi <dapeng1.mi@linux.intel.com>


On 8/28/2026 6:37 AM, Zide Chen wrote:
> IA32_PERF_GLOBAL_STATUS and its SET/RESET counterparts share bit
> definitions with perf_event.h, which is the canonical home for Intel
> PMU bit definitions (e.g., PERFEVTSEL, FIXED_CTR_CTRL, GLOBAL_STATUS).
> Drop the duplicate definitions from msr-index.h and update KVM code to
> use the macros from perf_event.h.
>
> Drop the comment as well, since the macros now match the MSR
> naming.
>
> No functional change intended.
>
> Signed-off-by: Zide Chen <zide.chen@intel.com>
> ---
>  arch/x86/include/asm/msr-index.h |  8 --------
>  arch/x86/kvm/vmx/pmu_intel.c     | 11 ++---------
>  arch/x86/kvm/vmx/vmx.c           |  2 +-
>  3 files changed, 3 insertions(+), 18 deletions(-)
>
> diff --git a/arch/x86/include/asm/msr-index.h b/arch/x86/include/asm/msr-index.h
> index 18c4be75e927..11b99d237e05 100644
> --- a/arch/x86/include/asm/msr-index.h
> +++ b/arch/x86/include/asm/msr-index.h
> @@ -1243,14 +1243,6 @@
>  
>  #define MSR_PERF_METRICS		0x00000329
>  
> -/* PERF_GLOBAL_OVF_CTL bits */
> -#define MSR_CORE_PERF_GLOBAL_OVF_CTRL_TRACE_TOPA_PMI_BIT	55
> -#define MSR_CORE_PERF_GLOBAL_OVF_CTRL_TRACE_TOPA_PMI		(1ULL << MSR_CORE_PERF_GLOBAL_OVF_CTRL_TRACE_TOPA_PMI_BIT)
> -#define MSR_CORE_PERF_GLOBAL_OVF_CTRL_OVF_BUF_BIT		62
> -#define MSR_CORE_PERF_GLOBAL_OVF_CTRL_OVF_BUF			(1ULL <<  MSR_CORE_PERF_GLOBAL_OVF_CTRL_OVF_BUF_BIT)
> -#define MSR_CORE_PERF_GLOBAL_OVF_CTRL_COND_CHGD_BIT		63
> -#define MSR_CORE_PERF_GLOBAL_OVF_CTRL_COND_CHGD			(1ULL << MSR_CORE_PERF_GLOBAL_OVF_CTRL_COND_CHGD_BIT)
> -
>  /* Geode defined MSRs */
>  #define MSR_GEODE_BUSCONT_CONF0		0x00001900
>  
> diff --git a/arch/x86/kvm/vmx/pmu_intel.c b/arch/x86/kvm/vmx/pmu_intel.c
> index bfa8612fb450..e71ddd51ae56 100644
> --- a/arch/x86/kvm/vmx/pmu_intel.c
> +++ b/arch/x86/kvm/vmx/pmu_intel.c
> @@ -576,17 +576,10 @@ static void intel_pmu_refresh(struct kvm_vcpu *vcpu)
>  			 ((BIT_ULL(pmu->nr_arch_fixed_counters) - 1) << KVM_FIXED_PMC_BASE_IDX));
>  	pmu->global_ctrl_rsvd = counter_rsvd;
>  
> -	/*
> -	 * GLOBAL_STATUS and GLOBAL_OVF_CONTROL (a.k.a. GLOBAL_STATUS_RESET)
> -	 * share reserved bit definitions.  The kernel just happens to use
> -	 * OVF_CTRL for the names.
> -	 */
>  	pmu->global_status_rsvd = pmu->global_ctrl_rsvd
> -			& ~(MSR_CORE_PERF_GLOBAL_OVF_CTRL_OVF_BUF |
> -			    MSR_CORE_PERF_GLOBAL_OVF_CTRL_COND_CHGD);
> +			& ~(GLOBAL_STATUS_BUFFER_OVF | GLOBAL_STATUS_COND_CHG);
>  	if (vmx_pt_mode_is_host_guest())
> -		pmu->global_status_rsvd &=
> -				~MSR_CORE_PERF_GLOBAL_OVF_CTRL_TRACE_TOPA_PMI;
> +		pmu->global_status_rsvd &= ~GLOBAL_STATUS_TRACE_TOPAPMI;
>  
>  	if (perf_capabilities & PERF_CAP_PEBS_FORMAT) {
>  		if (perf_capabilities & PERF_CAP_PEBS_BASELINE) {
> diff --git a/arch/x86/kvm/vmx/vmx.c b/arch/x86/kvm/vmx/vmx.c
> index e3bfe6aca1a0..d3789b2ee18e 100644
> --- a/arch/x86/kvm/vmx/vmx.c
> +++ b/arch/x86/kvm/vmx/vmx.c
> @@ -8612,7 +8612,7 @@ static unsigned int vmx_handle_intel_pt_intr(void)
>  		return 0;
>  
>  	kvm_make_request(KVM_REQ_PMI, vcpu);
> -	__set_bit(MSR_CORE_PERF_GLOBAL_OVF_CTRL_TRACE_TOPA_PMI_BIT,
> +	__set_bit(GLOBAL_STATUS_TRACE_TOPAPMI_BIT,
>  		  (unsigned long *)&vcpu->arch.pmu.global_status);
>  	return 1;
>  }