All of lore.kernel.org
 help / color / mirror / Atom feed
From: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
To: Konrad Dybcio <konrad.dybcio@linaro.org>,
	Rob Clark <robdclark@gmail.com>,
	dri-devel@lists.freedesktop.org
Cc: linux-arm-msm@vger.kernel.org, freedreno@lists.freedesktop.org,
	Rob Clark <robdclark@chromium.org>
Subject: Re: [PATCH 09/12] drm/msm/adreno: Add adreno family
Date: Fri, 7 Jul 2023 06:16:17 +0300	[thread overview]
Message-ID: <688c5dc3-ad46-2dfe-e418-c1b1cba767b8@linaro.org> (raw)
In-Reply-To: <c41b8ce0-8149-911b-0c6e-f963c830ac92@linaro.org>

On 07/07/2023 02:35, Konrad Dybcio wrote:
> On 6.07.2023 23:10, Rob Clark wrote:
>> From: Rob Clark <robdclark@chromium.org>
>>
>> Sometimes it is useful to know the sub-generation (or "family").  And in
>> any case, this helps us get away from infering the generation from the
>> numerical chip-id.
>>
>> Signed-off-by: Rob Clark <robdclark@chromium.org>
>> ---
> [...]
> 
>>   		.rev   = ADRENO_REV(5, 0, 8, ANY_ID),
>> +		.family = ADRENO_5XX,
>>   		.revn = 508,
> 508 is from 530 fam
> 
>>   		.fw = {
>>   			[ADRENO_FW_PM4] = "a530_pm4.fw",
>> @@ -156,6 +168,7 @@ static const struct adreno_info gpulist[] = {
>>   		.zapfw = "a508_zap.mdt",
>>   	}, {
>>   		.rev   = ADRENO_REV(5, 0, 9, ANY_ID),
>> +		.family = ADRENO_5XX,
>>   		.revn = 509,
> 509 and 512 are from 540 fam
> 
>>   		.fw = {
>>   			[ADRENO_FW_PM4] = "a530_pm4.fw",
>> @@ -173,6 +186,7 @@ static const struct adreno_info gpulist[] = {
>>   		.zapfw = "a512_zap.mdt",
>>   	}, {
>>   		.rev   = ADRENO_REV(5, 1, 0, ANY_ID),
>> +		.family = ADRENO_5XX,
>>   		.revn = 510,
> 510 is 530ish but I think it's closer to 505 or whatever the
> 8953 gpu was called

I'd say, there were following generations here:

- a505 / a506 / a508
- a509 / a512
- a510
- a530
- a540

Indeed a50x were close to a530 in some aspects and a509/512 being closer 
to a540, but I don't think they were the same family.

> 
> [...]
> 
>> -	priv->is_a2xx = config.rev.core == 2;
>> +	priv->is_a2xx = info->family < ADRENO_3XX;
> is this variable even needed now that there are explicit family values?
> 
> Konrad
>>   	priv->has_cached_coherent =
>>   		!!(info->quirks & ADRENO_QUIRK_HAS_CACHED_COHERENT);
>>   
>> diff --git a/drivers/gpu/drm/msm/adreno/adreno_gpu.c b/drivers/gpu/drm/msm/adreno/adreno_gpu.c
>> index 2e62a7ce9f13..75ff7fb46099 100644
>> --- a/drivers/gpu/drm/msm/adreno/adreno_gpu.c
>> +++ b/drivers/gpu/drm/msm/adreno/adreno_gpu.c
>> @@ -1079,8 +1079,13 @@ int adreno_gpu_init(struct drm_device *drm, struct platform_device *pdev,
>>   	u32 speedbin;
>>   	int ret;
>>   
>> +	adreno_gpu->funcs = funcs;
>> +	adreno_gpu->info = adreno_info(config->rev);
>> +	adreno_gpu->rev = *rev;
>> +
>>   	/* Only handle the core clock when GMU is not in use (or is absent). */
>> -	if (adreno_has_gmu_wrapper(adreno_gpu) || config->rev.core < 6) {
>> +	if (adreno_has_gmu_wrapper(adreno_gpu) ||
>> +	    adreno_gpu->info->family < ADRENO_6XX_GEN1) {
>>   		/*
>>   		 * This can only be done before devm_pm_opp_of_add_table(), or
>>   		 * dev_pm_opp_set_config() will WARN_ON()
>> @@ -1096,10 +1101,6 @@ int adreno_gpu_init(struct drm_device *drm, struct platform_device *pdev,
>>   			devm_pm_opp_set_clkname(dev, "core");
>>   	}
>>   
>> -	adreno_gpu->funcs = funcs;
>> -	adreno_gpu->info = adreno_info(config->rev);
>> -	adreno_gpu->rev = *rev;
>> -
>>   	if (adreno_read_speedbin(dev, &speedbin) || !speedbin)
>>   		speedbin = 0xffff;
>>   	adreno_gpu->speedbin = (uint16_t) (0xffff & speedbin);
>> diff --git a/drivers/gpu/drm/msm/adreno/adreno_gpu.h b/drivers/gpu/drm/msm/adreno/adreno_gpu.h
>> index 6066cfaaea52..2fa14dcd4e40 100644
>> --- a/drivers/gpu/drm/msm/adreno/adreno_gpu.h
>> +++ b/drivers/gpu/drm/msm/adreno/adreno_gpu.h
>> @@ -29,6 +29,25 @@ enum {
>>   	ADRENO_FW_MAX,
>>   };
>>   
>> +/**
>> + * @enum adreno_family: identify generation and possibly sub-generation
>> + *
>> + * In some cases there are distinct sub-generations within a major revision
>> + * so it helps to be able to group the GPU devices by generation and if
>> + * necessary sub-generation.
>> + */
>> +enum adreno_family {
>> +	ADRENO_2XX_GEN1,  /* a20x */
>> +	ADRENO_2XX_GEN2,  /* a22x */
>> +	ADRENO_3XX,
>> +	ADRENO_4XX,
>> +	ADRENO_5XX,
>> +	ADRENO_6XX_GEN1,  /* a630 family */
>> +	ADRENO_6XX_GEN2,  /* a640 family */
>> +	ADRENO_6XX_GEN3,  /* a650 family */
>> +	ADRENO_6XX_GEN4,  /* a660 family */
>> +};
>> +
>>   #define ADRENO_QUIRK_TWO_PASS_USE_WFI		BIT(0)
>>   #define ADRENO_QUIRK_FAULT_DETECT_MASK		BIT(1)
>>   #define ADRENO_QUIRK_LMLOADKILL_DISABLE		BIT(2)
>> @@ -63,6 +82,7 @@ extern const struct adreno_reglist a660_hwcg[], a690_hwcg[];
>>   struct adreno_info {
>>   	const char *machine;
>>   	struct adreno_rev rev;
>> +	enum adreno_family family;
>>   	uint32_t revn;
>>   	const char *fw[ADRENO_FW_MAX];
>>   	uint32_t gmem;
>> @@ -188,14 +208,14 @@ static inline bool adreno_is_a2xx(const struct adreno_gpu *gpu)
>>   {
>>   	if (WARN_ON_ONCE(!gpu->info))
>>   		return false;
>> -	return (gpu->info->revn < 300);
>> +	return gpu->info->family < ADRENO_2XX_GEN2;
>>   }
>>   
>>   static inline bool adreno_is_a20x(const struct adreno_gpu *gpu)
>>   {
>>   	if (WARN_ON_ONCE(!gpu->info))
>>   		return false;
>> -	return (gpu->info->revn < 210);
>> +	return gpu->info->family == ADRENO_2XX_GEN1;
>>   }
>>   
>>   static inline bool adreno_is_a225(const struct adreno_gpu *gpu)
>> @@ -338,29 +358,31 @@ static inline int adreno_is_a690(const struct adreno_gpu *gpu)
>>   /* check for a615, a616, a618, a619 or any a630 derivatives */
>>   static inline int adreno_is_a630_family(const struct adreno_gpu *gpu)
>>   {
>> -	return adreno_is_revn(gpu, 630) ||
>> -		adreno_is_revn(gpu, 615) ||
>> -		adreno_is_revn(gpu, 616) ||
>> -		adreno_is_revn(gpu, 618) ||
>> -		adreno_is_revn(gpu, 619);
>> +	if (WARN_ON_ONCE(!gpu->info))
>> +		return false;
>> +	return gpu->info->family == ADRENO_6XX_GEN1;
>>   }
>>   
>>   static inline int adreno_is_a660_family(const struct adreno_gpu *gpu)
>>   {
>> -	return adreno_is_a660(gpu) || adreno_is_a690(gpu) || adreno_is_7c3(gpu);
>> +	if (WARN_ON_ONCE(!gpu->info))
>> +		return false;
>> +	return gpu->info->family == ADRENO_6XX_GEN4;
>>   }
>>   
>>   /* check for a650, a660, or any derivatives */
>>   static inline int adreno_is_a650_family(const struct adreno_gpu *gpu)
>>   {
>> -	return adreno_is_revn(gpu, 650) ||
>> -		adreno_is_revn(gpu, 620) ||
>> -		adreno_is_a660_family(gpu);
>> +	if (WARN_ON_ONCE(!gpu->info))
>> +		return false;
>> +	return gpu->info->family >= ADRENO_6XX_GEN3;
>>   }
>>   
>>   static inline int adreno_is_a640_family(const struct adreno_gpu *gpu)
>>   {
>> -	return adreno_is_a640(gpu) || adreno_is_a680(gpu);
>> +	if (WARN_ON_ONCE(!gpu->info))
>> +		return false;
>> +	return gpu->info->family == ADRENO_6XX_GEN2;
>>   }
>>   
>>   u64 adreno_private_address_space_size(struct msm_gpu *gpu);

-- 
With best wishes
Dmitry


WARNING: multiple messages have this Message-ID (diff)
From: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
To: Konrad Dybcio <konrad.dybcio@linaro.org>,
	Rob Clark <robdclark@gmail.com>,
	dri-devel@lists.freedesktop.org
Cc: Rob Clark <robdclark@chromium.org>,
	linux-arm-msm@vger.kernel.org, freedreno@lists.freedesktop.org
Subject: Re: [PATCH 09/12] drm/msm/adreno: Add adreno family
Date: Fri, 7 Jul 2023 06:16:17 +0300	[thread overview]
Message-ID: <688c5dc3-ad46-2dfe-e418-c1b1cba767b8@linaro.org> (raw)
In-Reply-To: <c41b8ce0-8149-911b-0c6e-f963c830ac92@linaro.org>

On 07/07/2023 02:35, Konrad Dybcio wrote:
> On 6.07.2023 23:10, Rob Clark wrote:
>> From: Rob Clark <robdclark@chromium.org>
>>
>> Sometimes it is useful to know the sub-generation (or "family").  And in
>> any case, this helps us get away from infering the generation from the
>> numerical chip-id.
>>
>> Signed-off-by: Rob Clark <robdclark@chromium.org>
>> ---
> [...]
> 
>>   		.rev   = ADRENO_REV(5, 0, 8, ANY_ID),
>> +		.family = ADRENO_5XX,
>>   		.revn = 508,
> 508 is from 530 fam
> 
>>   		.fw = {
>>   			[ADRENO_FW_PM4] = "a530_pm4.fw",
>> @@ -156,6 +168,7 @@ static const struct adreno_info gpulist[] = {
>>   		.zapfw = "a508_zap.mdt",
>>   	}, {
>>   		.rev   = ADRENO_REV(5, 0, 9, ANY_ID),
>> +		.family = ADRENO_5XX,
>>   		.revn = 509,
> 509 and 512 are from 540 fam
> 
>>   		.fw = {
>>   			[ADRENO_FW_PM4] = "a530_pm4.fw",
>> @@ -173,6 +186,7 @@ static const struct adreno_info gpulist[] = {
>>   		.zapfw = "a512_zap.mdt",
>>   	}, {
>>   		.rev   = ADRENO_REV(5, 1, 0, ANY_ID),
>> +		.family = ADRENO_5XX,
>>   		.revn = 510,
> 510 is 530ish but I think it's closer to 505 or whatever the
> 8953 gpu was called

I'd say, there were following generations here:

- a505 / a506 / a508
- a509 / a512
- a510
- a530
- a540

Indeed a50x were close to a530 in some aspects and a509/512 being closer 
to a540, but I don't think they were the same family.

> 
> [...]
> 
>> -	priv->is_a2xx = config.rev.core == 2;
>> +	priv->is_a2xx = info->family < ADRENO_3XX;
> is this variable even needed now that there are explicit family values?
> 
> Konrad
>>   	priv->has_cached_coherent =
>>   		!!(info->quirks & ADRENO_QUIRK_HAS_CACHED_COHERENT);
>>   
>> diff --git a/drivers/gpu/drm/msm/adreno/adreno_gpu.c b/drivers/gpu/drm/msm/adreno/adreno_gpu.c
>> index 2e62a7ce9f13..75ff7fb46099 100644
>> --- a/drivers/gpu/drm/msm/adreno/adreno_gpu.c
>> +++ b/drivers/gpu/drm/msm/adreno/adreno_gpu.c
>> @@ -1079,8 +1079,13 @@ int adreno_gpu_init(struct drm_device *drm, struct platform_device *pdev,
>>   	u32 speedbin;
>>   	int ret;
>>   
>> +	adreno_gpu->funcs = funcs;
>> +	adreno_gpu->info = adreno_info(config->rev);
>> +	adreno_gpu->rev = *rev;
>> +
>>   	/* Only handle the core clock when GMU is not in use (or is absent). */
>> -	if (adreno_has_gmu_wrapper(adreno_gpu) || config->rev.core < 6) {
>> +	if (adreno_has_gmu_wrapper(adreno_gpu) ||
>> +	    adreno_gpu->info->family < ADRENO_6XX_GEN1) {
>>   		/*
>>   		 * This can only be done before devm_pm_opp_of_add_table(), or
>>   		 * dev_pm_opp_set_config() will WARN_ON()
>> @@ -1096,10 +1101,6 @@ int adreno_gpu_init(struct drm_device *drm, struct platform_device *pdev,
>>   			devm_pm_opp_set_clkname(dev, "core");
>>   	}
>>   
>> -	adreno_gpu->funcs = funcs;
>> -	adreno_gpu->info = adreno_info(config->rev);
>> -	adreno_gpu->rev = *rev;
>> -
>>   	if (adreno_read_speedbin(dev, &speedbin) || !speedbin)
>>   		speedbin = 0xffff;
>>   	adreno_gpu->speedbin = (uint16_t) (0xffff & speedbin);
>> diff --git a/drivers/gpu/drm/msm/adreno/adreno_gpu.h b/drivers/gpu/drm/msm/adreno/adreno_gpu.h
>> index 6066cfaaea52..2fa14dcd4e40 100644
>> --- a/drivers/gpu/drm/msm/adreno/adreno_gpu.h
>> +++ b/drivers/gpu/drm/msm/adreno/adreno_gpu.h
>> @@ -29,6 +29,25 @@ enum {
>>   	ADRENO_FW_MAX,
>>   };
>>   
>> +/**
>> + * @enum adreno_family: identify generation and possibly sub-generation
>> + *
>> + * In some cases there are distinct sub-generations within a major revision
>> + * so it helps to be able to group the GPU devices by generation and if
>> + * necessary sub-generation.
>> + */
>> +enum adreno_family {
>> +	ADRENO_2XX_GEN1,  /* a20x */
>> +	ADRENO_2XX_GEN2,  /* a22x */
>> +	ADRENO_3XX,
>> +	ADRENO_4XX,
>> +	ADRENO_5XX,
>> +	ADRENO_6XX_GEN1,  /* a630 family */
>> +	ADRENO_6XX_GEN2,  /* a640 family */
>> +	ADRENO_6XX_GEN3,  /* a650 family */
>> +	ADRENO_6XX_GEN4,  /* a660 family */
>> +};
>> +
>>   #define ADRENO_QUIRK_TWO_PASS_USE_WFI		BIT(0)
>>   #define ADRENO_QUIRK_FAULT_DETECT_MASK		BIT(1)
>>   #define ADRENO_QUIRK_LMLOADKILL_DISABLE		BIT(2)
>> @@ -63,6 +82,7 @@ extern const struct adreno_reglist a660_hwcg[], a690_hwcg[];
>>   struct adreno_info {
>>   	const char *machine;
>>   	struct adreno_rev rev;
>> +	enum adreno_family family;
>>   	uint32_t revn;
>>   	const char *fw[ADRENO_FW_MAX];
>>   	uint32_t gmem;
>> @@ -188,14 +208,14 @@ static inline bool adreno_is_a2xx(const struct adreno_gpu *gpu)
>>   {
>>   	if (WARN_ON_ONCE(!gpu->info))
>>   		return false;
>> -	return (gpu->info->revn < 300);
>> +	return gpu->info->family < ADRENO_2XX_GEN2;
>>   }
>>   
>>   static inline bool adreno_is_a20x(const struct adreno_gpu *gpu)
>>   {
>>   	if (WARN_ON_ONCE(!gpu->info))
>>   		return false;
>> -	return (gpu->info->revn < 210);
>> +	return gpu->info->family == ADRENO_2XX_GEN1;
>>   }
>>   
>>   static inline bool adreno_is_a225(const struct adreno_gpu *gpu)
>> @@ -338,29 +358,31 @@ static inline int adreno_is_a690(const struct adreno_gpu *gpu)
>>   /* check for a615, a616, a618, a619 or any a630 derivatives */
>>   static inline int adreno_is_a630_family(const struct adreno_gpu *gpu)
>>   {
>> -	return adreno_is_revn(gpu, 630) ||
>> -		adreno_is_revn(gpu, 615) ||
>> -		adreno_is_revn(gpu, 616) ||
>> -		adreno_is_revn(gpu, 618) ||
>> -		adreno_is_revn(gpu, 619);
>> +	if (WARN_ON_ONCE(!gpu->info))
>> +		return false;
>> +	return gpu->info->family == ADRENO_6XX_GEN1;
>>   }
>>   
>>   static inline int adreno_is_a660_family(const struct adreno_gpu *gpu)
>>   {
>> -	return adreno_is_a660(gpu) || adreno_is_a690(gpu) || adreno_is_7c3(gpu);
>> +	if (WARN_ON_ONCE(!gpu->info))
>> +		return false;
>> +	return gpu->info->family == ADRENO_6XX_GEN4;
>>   }
>>   
>>   /* check for a650, a660, or any derivatives */
>>   static inline int adreno_is_a650_family(const struct adreno_gpu *gpu)
>>   {
>> -	return adreno_is_revn(gpu, 650) ||
>> -		adreno_is_revn(gpu, 620) ||
>> -		adreno_is_a660_family(gpu);
>> +	if (WARN_ON_ONCE(!gpu->info))
>> +		return false;
>> +	return gpu->info->family >= ADRENO_6XX_GEN3;
>>   }
>>   
>>   static inline int adreno_is_a640_family(const struct adreno_gpu *gpu)
>>   {
>> -	return adreno_is_a640(gpu) || adreno_is_a680(gpu);
>> +	if (WARN_ON_ONCE(!gpu->info))
>> +		return false;
>> +	return gpu->info->family == ADRENO_6XX_GEN2;
>>   }
>>   
>>   u64 adreno_private_address_space_size(struct msm_gpu *gpu);

-- 
With best wishes
Dmitry


  reply	other threads:[~2023-07-07  3:16 UTC|newest]

Thread overview: 134+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2023-07-06 21:10 [PATCH 00/12] drm/msm/adreno: Move away from legacy revision matching Rob Clark
2023-07-06 21:10 ` Rob Clark
2023-07-06 21:10 ` [PATCH 01/12] drm/msm/adreno: Remove GPU name Rob Clark
2023-07-06 21:10   ` Rob Clark
2023-07-06 23:21   ` Konrad Dybcio
2023-07-06 23:21     ` Konrad Dybcio
2023-07-07  0:04   ` [Freedreno] " Dmitry Baryshkov
2023-07-06 21:10 ` [PATCH 02/12] drm/msm/adreno: Remove redundant gmem size param Rob Clark
2023-07-06 21:10   ` Rob Clark
2023-07-06 23:22   ` Konrad Dybcio
2023-07-06 23:22     ` Konrad Dybcio
2023-07-13 19:46     ` Akhil P Oommen
2023-07-13 19:46       ` Akhil P Oommen
2023-07-07  2:23   ` [Freedreno] " Dmitry Baryshkov
2023-07-06 21:10 ` [PATCH 03/12] drm/msm/adreno: Remove redundant revn param Rob Clark
2023-07-06 21:10   ` Rob Clark
2023-07-06 23:26   ` Konrad Dybcio
2023-07-06 23:26     ` Konrad Dybcio
2023-07-07  2:24   ` [Freedreno] " Dmitry Baryshkov
2023-07-06 21:10 ` [PATCH 04/12] drm/msm/adreno: Use quirk identify hw_apriv Rob Clark
2023-07-06 21:10   ` Rob Clark
2023-07-06 23:27   ` Konrad Dybcio
2023-07-06 23:27     ` Konrad Dybcio
2023-07-07  2:25   ` [Freedreno] " Dmitry Baryshkov
2023-07-06 21:10 ` [PATCH 05/12] drm/msm/adreno: Use quirk to identify cached-coherent support Rob Clark
2023-07-06 21:10   ` Rob Clark
2023-07-06 23:29   ` Konrad Dybcio
2023-07-06 23:29     ` Konrad Dybcio
2023-07-07  2:29   ` [Freedreno] " Dmitry Baryshkov
2023-07-07 15:53     ` Rob Clark
2023-07-07 15:53       ` Rob Clark
2023-07-13 20:05   ` Akhil P Oommen
2023-07-13 20:05     ` Akhil P Oommen
2023-07-13 22:25     ` Rob Clark
2023-07-13 22:25       ` Rob Clark
2023-07-17 22:00       ` Akhil P Oommen
2023-07-17 22:00         ` Akhil P Oommen
2023-07-06 21:10 ` [PATCH 06/12] drm/msm/adreno: Allow SoC specific gpu device table entries Rob Clark
2023-07-06 21:10   ` Rob Clark
2023-07-07  0:40   ` Konrad Dybcio
2023-07-07  0:40     ` Konrad Dybcio
2023-07-13 22:15     ` [Freedreno] " Akhil P Oommen
2023-07-13 22:15       ` Akhil P Oommen
2023-07-07  2:34   ` Dmitry Baryshkov
2023-07-13 20:26     ` Akhil P Oommen
2023-07-13 20:26       ` Akhil P Oommen
2023-07-26 18:28       ` Rob Clark
2023-07-26 18:28         ` Rob Clark
2023-07-26 20:00         ` Dmitry Baryshkov
2023-07-26 20:00           ` Dmitry Baryshkov
2023-07-26 20:11           ` Rob Clark
2023-07-26 20:11             ` Rob Clark
2023-07-26 21:43             ` Dmitry Baryshkov
2023-07-26 21:43               ` Dmitry Baryshkov
2023-07-26 22:03               ` Rob Clark
2023-07-26 22:03                 ` Rob Clark
2023-07-26 22:33                 ` Dmitry Baryshkov
2023-07-26 22:33                   ` Dmitry Baryshkov
2023-07-26 22:53                   ` Rob Clark
2023-07-26 22:53                     ` Rob Clark
2023-07-27  7:51                     ` Konrad Dybcio
2023-07-27  7:51                       ` Konrad Dybcio
2023-07-27 14:52                       ` Rob Clark
2023-07-27 14:52                         ` Rob Clark
2023-07-27 21:13                   ` Rob Clark
2023-07-27 21:13                     ` Rob Clark
2023-07-27 22:02                     ` Dmitry Baryshkov
2023-07-27 22:02                       ` Dmitry Baryshkov
2023-07-28 14:43                       ` Rob Clark
2023-07-28 14:43                         ` Rob Clark
2023-07-28 14:51                         ` Dmitry Baryshkov
2023-07-28 14:51                           ` Dmitry Baryshkov
2023-07-06 21:10 ` [PATCH 07/12] drm/msm/adreno: Move speedbin mapping to device table Rob Clark
2023-07-06 21:10   ` Rob Clark
2023-07-07  2:54   ` [Freedreno] " Dmitry Baryshkov
2023-07-10 19:56     ` Rob Clark
2023-07-10 19:56       ` Rob Clark
2023-07-10 20:54       ` Dmitry Baryshkov
2023-07-10 20:54         ` Dmitry Baryshkov
2023-07-06 21:10 ` [PATCH 08/12] drm/msm/adreno: Bring the a630 family together Rob Clark
2023-07-06 21:10   ` Rob Clark
2023-07-06 23:32   ` Konrad Dybcio
2023-07-06 23:32     ` Konrad Dybcio
2023-07-06 21:10 ` [PATCH 09/12] drm/msm/adreno: Add adreno family Rob Clark
2023-07-06 21:10   ` Rob Clark
2023-07-06 23:35   ` Konrad Dybcio
2023-07-06 23:35     ` Konrad Dybcio
2023-07-07  3:16     ` Dmitry Baryshkov [this message]
2023-07-07  3:16       ` Dmitry Baryshkov
2023-07-07 23:52       ` Rob Clark
2023-07-07 23:52         ` Rob Clark
2023-07-07 23:54         ` Dmitry Baryshkov
2023-07-07 23:54           ` Dmitry Baryshkov
2023-07-07  2:49   ` [Freedreno] " Dmitry Baryshkov
2023-07-06 21:10 ` [PATCH 10/12] drm/msm/adreno: Add helper for formating chip-id Rob Clark
2023-07-06 21:10   ` Rob Clark
2023-07-06 23:36   ` Konrad Dybcio
2023-07-06 23:36     ` Konrad Dybcio
2023-07-10 20:21     ` Rob Clark
2023-07-10 20:21       ` Rob Clark
2023-07-07  2:50   ` [Freedreno] " Dmitry Baryshkov
2023-07-06 21:10 ` [PATCH 11/12] dt-bindings: drm/msm/gpu: Extend bindings for chip-id Rob Clark
2023-07-06 21:10   ` Rob Clark
2023-07-07  7:26   ` Krzysztof Kozlowski
2023-07-07 13:09     ` Rob Clark
2023-07-07 13:09       ` Rob Clark
2023-07-06 21:10 ` [PATCH 12/12] drm/msm/adreno: Switch to chip-id for identifying GPU Rob Clark
2023-07-06 21:10   ` Rob Clark
2023-07-07  0:25   ` Konrad Dybcio
2023-07-07  0:25     ` Konrad Dybcio
2023-07-07 16:08     ` Rob Clark
2023-07-07 16:08       ` Rob Clark
2023-07-15 13:38       ` Konrad Dybcio
2023-07-15 13:38         ` Konrad Dybcio
2023-07-15 14:12         ` Rob Clark
2023-07-15 14:12           ` Rob Clark
2023-07-26 21:45         ` Rob Clark
2023-07-26 21:45           ` Rob Clark
2023-07-07  3:45   ` [Freedreno] " Dmitry Baryshkov
2023-07-13 21:39     ` Akhil P Oommen
2023-07-13 21:39       ` Akhil P Oommen
2023-07-13 22:06       ` Rob Clark
2023-07-13 22:06         ` Rob Clark
2023-07-13 22:53         ` Dmitry Baryshkov
2023-07-13 22:53           ` Dmitry Baryshkov
2023-07-17 22:09         ` Akhil P Oommen
2023-07-17 22:09           ` Akhil P Oommen
2023-07-26 21:37     ` Rob Clark
2023-07-26 21:37       ` Rob Clark
2023-07-26 21:38       ` Dmitry Baryshkov
2023-07-26 21:38         ` Dmitry Baryshkov
2023-07-26 21:44         ` Rob Clark
2023-07-26 21:44           ` Rob Clark
2023-07-26 21:45           ` Dmitry Baryshkov

Reply instructions:

You may reply publicly to this message via plain-text email
using any one of the following methods:

* Save the following mbox file, import it into your mail client,
  and reply-to-all from there: mbox

  Avoid top-posting and favor interleaved quoting:
  https://en.wikipedia.org/wiki/Posting_style#Interleaved_style

* Reply using the --to, --cc, and --in-reply-to
  switches of git-send-email(1):

  git send-email \
    --in-reply-to=688c5dc3-ad46-2dfe-e418-c1b1cba767b8@linaro.org \
    --to=dmitry.baryshkov@linaro.org \
    --cc=dri-devel@lists.freedesktop.org \
    --cc=freedreno@lists.freedesktop.org \
    --cc=konrad.dybcio@linaro.org \
    --cc=linux-arm-msm@vger.kernel.org \
    --cc=robdclark@chromium.org \
    --cc=robdclark@gmail.com \
    /path/to/YOUR_REPLY

  https://kernel.org/pub/software/scm/git/docs/git-send-email.html

* If your mail client supports setting the In-Reply-To header
  via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line before the message body.
This is an external index of several public inboxes,
see mirroring instructions on how to clone and mirror
all data and code used by this external index.