[PATCH 0/3] Expand amdgpu documentation

[PATCH 0/3] Expand amdgpu documentation

[Rodrigo Siqueira]

This patchset introduces some new AMDGPU documentation. You will find:

1. A CSV table that maps which component version is part of some ASIC
   families. This can be useful to narrow down bugs;
2. Some explanation about AMD Display Pipeline;
3. An explanation of Multiple Plane Overlay, which can be useful for
   userspace applications.

Since we have some diagrams, I recommend applying these patches and
building the documentation to have a better experience.

Thanks
Siqueira

Rodrigo Siqueira (3):
  Documentation/gpu: Add info table for ASICs
  Documentation/gpu: Add an explanation about the DCN pipeline
  Documentation/gpu: Add Multiplane Overlay doc

 .../gpu/amdgpu/apu-asic-info-table.csv        |    8 +
 .../gpu/amdgpu/dgpu-asic-info-table.csv       |   24 +
 .../gpu/amdgpu/display/dcn-overview.rst       |   58 +
 Documentation/gpu/amdgpu/display/index.rst    |    1 +
 .../gpu/amdgpu/display/mpo-cursor.svg         |  435 +++++++
 .../gpu/amdgpu/display/mpo-overview.rst       |  242 ++++
 .../multi-display-hdcp-mpo-less-pipe-ex.svg   |  220 ++++
 .../amdgpu/display/multi-display-hdcp-mpo.svg |  171 +++
 .../amdgpu/display/pipeline_4k_no_split.svg   |  958 +++++++++++++++
 .../gpu/amdgpu/display/pipeline_4k_split.svg  | 1062 +++++++++++++++++
 .../single-display-mpo-multi-video.svg        |  339 ++++++
 .../gpu/amdgpu/display/single-display-mpo.svg |  266 +++++
 Documentation/gpu/amdgpu/driver-misc.rst      |   17 +
 13 files changed, 3801 insertions(+)
 create mode 100644 Documentation/gpu/amdgpu/apu-asic-info-table.csv
 create mode 100644 Documentation/gpu/amdgpu/dgpu-asic-info-table.csv
 create mode 100644 Documentation/gpu/amdgpu/display/mpo-cursor.svg
 create mode 100644 Documentation/gpu/amdgpu/display/mpo-overview.rst
 create mode 100644 Documentation/gpu/amdgpu/display/multi-display-hdcp-mpo-less-pipe-ex.svg
 create mode 100644 Documentation/gpu/amdgpu/display/multi-display-hdcp-mpo.svg
 create mode 100644 Documentation/gpu/amdgpu/display/pipeline_4k_no_split.svg
 create mode 100644 Documentation/gpu/amdgpu/display/pipeline_4k_split.svg
 create mode 100644 Documentation/gpu/amdgpu/display/single-display-mpo-multi-video.svg
 create mode 100644 Documentation/gpu/amdgpu/display/single-display-mpo.svg

-- 
2.25.1

[PATCH 1/3] Documentation/gpu: Add info table for ASICs

[Rodrigo Siqueira]

Amdgpu driver is used in an extensive range of devices, and each ASIC
has some specific configuration. As a result of this variety, sometimes
it is hard to identify the correct block that might cause the issue.
This commit expands the amdgpu kernel-doc to alleviate this issue by
introducing one ASIC table that describes dGPU and another one that
shares the APU info.

Cc: Harry Wentland <harry.wentland@amd.com>
Cc: Nicholas Kazlauskas <Nicholas.Kazlauskas@amd.com>
Cc: Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com>
Cc: Hersen Wu <hersenxs.wu@amd.com>
Cc: Alex Hung <alex.hung@amd.com>
Cc: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Cc: Leo Li <sunpeng.li@amd.com>
Cc: Simon Ser <contact@emersion.fr>
Cc: Pekka Paalanen <pekka.paalanen@collabora.com>
Cc: Sean Paul <seanpaul@chromium.org>
Cc: Mark Yacoub <markyacoub@chromium.org>
Cc: Pierre-Loup <pgriffais@valvesoftware.com>
Cc: Michel Dänzer <michel.daenzer@mailbox.org>
Signed-off-by: Rodrigo Siqueira <Rodrigo.Siqueira@amd.com>
---
 .../gpu/amdgpu/apu-asic-info-table.csv        |  8 +++++++
 .../gpu/amdgpu/dgpu-asic-info-table.csv       | 24 +++++++++++++++++++
 Documentation/gpu/amdgpu/driver-misc.rst      | 17 +++++++++++++
 3 files changed, 49 insertions(+)
 create mode 100644 Documentation/gpu/amdgpu/apu-asic-info-table.csv
 create mode 100644 Documentation/gpu/amdgpu/dgpu-asic-info-table.csv

diff --git a/Documentation/gpu/amdgpu/apu-asic-info-table.csv b/Documentation/gpu/amdgpu/apu-asic-info-table.csv
new file mode 100644
index 000000000000..98c6988e424e
--- /dev/null
+++ b/Documentation/gpu/amdgpu/apu-asic-info-table.csv
@@ -0,0 +1,8 @@
+Product Name, Code Reference, DCN/DCE version, GC version, VCE/UVD/VCN version, SDMA version
+Radeon R* Graphics, CARRIZO/STONEY, DCE 11, 8, VCE 3 / UVD 6, 3
+Ryzen 3000 series / AMD Ryzen Embedded V1*/R1* with Radeon Vega Gfx, RAVEN/PICASSO, DCN 1.0, 9.1.0, VCN 1.0, 4.1.0
+Ryzen 4000 series, RENOIR, DCN 2.1, 9.3, VCN 2.2, 4.1.2
+Ryzen 3000 series / AMD Ryzen Embedded V1*/R1* with Radeon Vega Gfx, RAVEN2, DCN 1.0, 9.2.2, VCN 1.0.1, 4.1.1
+SteamDeck, VANGOGH, DCN 3.0.1, 10.3.1, VCN 3.1.0, 5.2.1
+Ryzen 5000 series, GREEN SARDINE, DCN 2.1, 9.3, VCN 2.2, 4.1.1
+Ryzen 6000 Zen, YELLOW CARP, 3.1.2, 10.3.3, VCN 3.1.1, 5.2.3
diff --git a/Documentation/gpu/amdgpu/dgpu-asic-info-table.csv b/Documentation/gpu/amdgpu/dgpu-asic-info-table.csv
new file mode 100644
index 000000000000..84617aa35dab
--- /dev/null
+++ b/Documentation/gpu/amdgpu/dgpu-asic-info-table.csv
@@ -0,0 +1,24 @@
+Product Name, Code Reference, DCN/DCE version, GC version, VCN version, SDMA version
+AMD Radeon (TM) HD 8500M/ 8600M /M200 /M320 /M330 /M335 Series, HAINAN, --,  6, --, --
+AMD Radeon HD 7800 /7900 /FireGL Series, TAHITI, DCE 6, 6, VCE 1 / UVD 3, --
+AMD Radeon R7 (TM|HD) M265 /M370 /8500M /8600 /8700 /8700M, OLAND, DCE 6, 6, VCE 1 / UVD 3, --
+AMD Radeon (TM) (HD|R7) 7800 /7970 /8800 /8970 /370/ Series, PITCAIRN, DCE 6, 6, VCE 1 / UVD 3, --
+AMD Radeon (TM|R7|R9|HD) E8860 /M360 /7700 /7800 /8800 /9000(M) /W4100 Series, VERDE, DCE 6, 6, VCE 1 / UVD 3, --
+AMD Radeon HD M280X /M380 /7700 /8950 /W5100, BONAIRE, DCE 8, 7, VCE 2 / UVD 4.2, 1
+AMD Radeon (R9|TM) 200 /390 /W8100 /W9100 Series, HAWAII, DCE 8, 7, VCE 2 / UVD 4.2, 1
+AMD Radeon (TM) R(5|7) M315 /M340 /M360, TOPAZ, *, 8, --, 2
+AMD Radeon (TM) R9 200 /380 /W7100 /S7150 /M390 /M395 Series, TONGA, DCE 10, 8, VCE 3 / UVD 5, 3
+AMD Radeon (FirePro) (TM) R9 Fury Series, FIJI, DCE 10, 8, VCE 3 / UVD 6, 3
+Radeon RX 470 /480 /570 /580 /590 Series - AMD Radeon (TM) (Pro WX) 5100 /E9390 /E9560 /E9565 /V7350 /7100 /P30PH, POLARIS10, DCE 11.2, 8, VCE 3.4 / UVD 6.3, 3
+Radeon (TM) (RX|Pro WX) E9260 /460 /V5300X /550 /560(X) Series, POLARIS11, DCE 11.2, 8, VCE 3.4 / UVD 6.3, 3
+Radeon (RX/Pro) 500 /540(X) /550 /640 /WX2100 /WX3100 /WX200 Series, POLARIS12, DCE 11.2, 8, VCE 3.4 / UVD 6.3, 3
+Radeon (RX|TM) (PRO|WX) Vega /MI25 /V320 /V340L /8200 /9100 /SSG MxGPU, VEGA10, DCE 12, 9.0.1, VCE 4.0.0 / UVD 7.0.0, 4.0.0
+AMD Radeon (Pro) VII /MI50 /MI60, VEGA20, DCE 12, 9.4.0, VCE 4.1.0 / UVD 7.2.0, 4.2.0
+MI100, ARCTURUS, *, 9.4.1, VCN 2.5.0, 4.2.2
+MI200, ALDEBARAN, *, 9.4.2, VCN 2.6.0, 4.4.0
+AMD Radeon (RX|Pro) 5600(M|XT) /5700 (M|XT|XTB) /W5700, NAVI10, DCN 2.0.0, 10.1.10, VCN 2.0.0, 5.0.0
+AMD Radeon (Pro) 5300 /5500XTB/5500(XT|M) /W5500M /W5500, NAVI14, DCN 2.0.0, 10.1.1, VCN 2.0.2, 5.0.2
+AMD Radeon RX 6800(XT) /6900(XT) /W6800, SIENNA_CICHLID, DCN 3.0.0, 10.3.0, VCN 3.0.0, 5.2.0
+AMD Radeon RX 6700 XT / 6800M / 6700M, NAVY_FLOUNDER, DCN 3.0.0, 10.3.2, VCN 3.0.0, 5.2.2
+AMD Radeon RX 6600(XT) /6600M /W6600 /W6600M, DIMGREY_CAVEFISH, DCN 3.0.2, 10.3.4, VCN 3.0.16, 5.2.4
+AMD Radeon RX 6500M /6300M /W6500M /W6300M, BEIGE_GOBY, DCN 3.0.3, 10.3.5, VCN 3.0.33, 5.2.5
diff --git a/Documentation/gpu/amdgpu/driver-misc.rst b/Documentation/gpu/amdgpu/driver-misc.rst
index e3d6b2fa2493..1800543d45f7 100644
--- a/Documentation/gpu/amdgpu/driver-misc.rst
+++ b/Documentation/gpu/amdgpu/driver-misc.rst
@@ -32,6 +32,23 @@ unique_id
 .. kernel-doc:: drivers/gpu/drm/amd/pm/amdgpu_pm.c
    :doc: unique_id
 
+Accelerated Processing Units (APU) Info
+---------------------------------------
+
+.. csv-table::
+   :header-rows: 1
+   :widths: 3, 2, 2, 1, 1, 1
+   :file: ./apu-asic-info-table.csv
+
+Discrete GPU Info
+-----------------
+
+.. csv-table::
+   :header-rows: 1
+   :widths: 3, 2, 2, 1, 1, 1
+   :file: ./dgpu-asic-info-table.csv
+
+
 GPU Memory Usage Information
 ============================
 
-- 
2.25.1

Re: [PATCH 1/3] Documentation/gpu: Add info table for ASICs

[Simon Ser]

On Monday, June 13th, 2022 at 22:01, Rodrigo Siqueira <Rodrigo.Siqueira@amd.com> wrote:

> Amdgpu driver is used in an extensive range of devices, and each ASIC
> has some specific configuration. As a result of this variety, sometimes
> it is hard to identify the correct block that might cause the issue.
> This commit expands the amdgpu kernel-doc to alleviate this issue by
> introducing one ASIC table that describes dGPU and another one that
> shares the APU info.

Nice!

Are there plans to keep this list up-to-date?

FWIW, my go-to reference tables are [1], updated by Alex.

Would it make sense to add a "GFX Core" column?

[1]: https://www.x.org/wiki/RadeonFeature/

Re: [PATCH 1/3] Documentation/gpu: Add info table for ASICs

[Alex Deucher]

On Tue, Jun 14, 2022 at 2:16 PM Simon Ser <contact@emersion.fr> wrote:
>
> On Monday, June 13th, 2022 at 22:01, Rodrigo Siqueira <Rodrigo.Siqueira@amd.com> wrote:
>
> > Amdgpu driver is used in an extensive range of devices, and each ASIC
> > has some specific configuration. As a result of this variety, sometimes
> > it is hard to identify the correct block that might cause the issue.
> > This commit expands the amdgpu kernel-doc to alleviate this issue by
> > introducing one ASIC table that describes dGPU and another one that
> > shares the APU info.
>
> Nice!
>
> Are there plans to keep this list up-to-date?
>
> FWIW, my go-to reference tables are [1], updated by Alex.
>
> Would it make sense to add a "GFX Core" column?

That's what the GC column is for.

Alex


>
> [1]: https://www.x.org/wiki/RadeonFeature/

Re: [PATCH 1/3] Documentation/gpu: Add info table for ASICs

[Simon Ser]

On Tuesday, June 14th, 2022 at 20:30, Alex Deucher <alexdeucher@gmail.com> wrote:

> On Tue, Jun 14, 2022 at 2:16 PM Simon Ser contact@emersion.fr wrote:
>
> > On Monday, June 13th, 2022 at 22:01, Rodrigo Siqueira Rodrigo.Siqueira@amd.com wrote:
> >
> > > Amdgpu driver is used in an extensive range of devices, and each ASIC
> > > has some specific configuration. As a result of this variety, sometimes
> > > it is hard to identify the correct block that might cause the issue.
> > > This commit expands the amdgpu kernel-doc to alleviate this issue by
> > > introducing one ASIC table that describes dGPU and another one that
> > > shares the APU info.
> >
> > Nice!
> >
> > Are there plans to keep this list up-to-date?
> >
> > FWIW, my go-to reference tables are 1, updated by Alex.
> >
> > Would it make sense to add a "GFX Core" column?
>
> That's what the GC column is for.

Oh! Does this stand for "GFX Core", or for "Graphics and Compute"? The
glossary documents GC as the latter. If there is a name conflict, maybe
we can keep using the long name in the table, or document what "GC"
means in a sentence.

Re: [PATCH 1/3] Documentation/gpu: Add info table for ASICs

[Alex Deucher]

On Wed, Jun 15, 2022 at 3:47 AM Simon Ser <contact@emersion.fr> wrote:
>
> On Tuesday, June 14th, 2022 at 20:30, Alex Deucher <alexdeucher@gmail.com> wrote:
>
> > On Tue, Jun 14, 2022 at 2:16 PM Simon Ser contact@emersion.fr wrote:
> >
> > > On Monday, June 13th, 2022 at 22:01, Rodrigo Siqueira Rodrigo.Siqueira@amd.com wrote:
> > >
> > > > Amdgpu driver is used in an extensive range of devices, and each ASIC
> > > > has some specific configuration. As a result of this variety, sometimes
> > > > it is hard to identify the correct block that might cause the issue.
> > > > This commit expands the amdgpu kernel-doc to alleviate this issue by
> > > > introducing one ASIC table that describes dGPU and another one that
> > > > shares the APU info.
> > >
> > > Nice!
> > >
> > > Are there plans to keep this list up-to-date?
> > >
> > > FWIW, my go-to reference tables are 1, updated by Alex.
> > >
> > > Would it make sense to add a "GFX Core" column?
> >
> > That's what the GC column is for.
>
> Oh! Does this stand for "GFX Core", or for "Graphics and Compute"? The
> glossary documents GC as the latter. If there is a name conflict, maybe
> we can keep using the long name in the table, or document what "GC"
> means in a sentence.

Both?  The hardware block is called GC, but I think different teams
expand it to Graphics Core (as in GCN) or Graphics and Compute.  Same
hardware block either way.  I guess we should include both in the
glossary.

Alex

Re: [PATCH 1/3] Documentation/gpu: Add info table for ASICs

[Rodrigo Siqueira Jordao]

On 2022-06-15 10:13, Alex Deucher wrote:
> On Wed, Jun 15, 2022 at 3:47 AM Simon Ser <contact@emersion.fr> wrote:
>>
>> On Tuesday, June 14th, 2022 at 20:30, Alex Deucher <alexdeucher@gmail.com> wrote:
>>
>>> On Tue, Jun 14, 2022 at 2:16 PM Simon Ser contact@emersion.fr wrote:
>>>
>>>> On Monday, June 13th, 2022 at 22:01, Rodrigo Siqueira Rodrigo.Siqueira@amd.com wrote:
>>>>
>>>>> Amdgpu driver is used in an extensive range of devices, and each ASIC
>>>>> has some specific configuration. As a result of this variety, sometimes
>>>>> it is hard to identify the correct block that might cause the issue.
>>>>> This commit expands the amdgpu kernel-doc to alleviate this issue by
>>>>> introducing one ASIC table that describes dGPU and another one that
>>>>> shares the APU info.
>>>>
>>>> Nice!
>>>>
>>>> Are there plans to keep this list up-to-date?
>>>>
>>>> FWIW, my go-to reference tables are 1, updated by Alex.
>>>>
>>>> Would it make sense to add a "GFX Core" column?
>>>
>>> That's what the GC column is for.
>>
>> Oh! Does this stand for "GFX Core", or for "Graphics and Compute"? The
>> glossary documents GC as the latter. If there is a name conflict, maybe
>> we can keep using the long name in the table, or document what "GC"
>> means in a sentence.
> 
> Both?  The hardware block is called GC, but I think different teams
> expand it to Graphics Core (as in GCN) or Graphics and Compute.  Same
> hardware block either way.  I guess we should include both in the
> glossary.


How should I add it? Something like this:

GC/GFX:
  Graphics and Compute/Core

Thanks
Siqueira

> Alex

Re: [PATCH 1/3] Documentation/gpu: Add info table for ASICs

[Alex Deucher]

On Thu, Jun 16, 2022 at 5:31 PM Rodrigo Siqueira Jordao
<Rodrigo.Siqueira@amd.com> wrote:
>
>
>
> On 2022-06-15 10:13, Alex Deucher wrote:
> > On Wed, Jun 15, 2022 at 3:47 AM Simon Ser <contact@emersion.fr> wrote:
> >>
> >> On Tuesday, June 14th, 2022 at 20:30, Alex Deucher <alexdeucher@gmail.com> wrote:
> >>
> >>> On Tue, Jun 14, 2022 at 2:16 PM Simon Ser contact@emersion.fr wrote:
> >>>
> >>>> On Monday, June 13th, 2022 at 22:01, Rodrigo Siqueira Rodrigo.Siqueira@amd.com wrote:
> >>>>
> >>>>> Amdgpu driver is used in an extensive range of devices, and each ASIC
> >>>>> has some specific configuration. As a result of this variety, sometimes
> >>>>> it is hard to identify the correct block that might cause the issue.
> >>>>> This commit expands the amdgpu kernel-doc to alleviate this issue by
> >>>>> introducing one ASIC table that describes dGPU and another one that
> >>>>> shares the APU info.
> >>>>
> >>>> Nice!
> >>>>
> >>>> Are there plans to keep this list up-to-date?
> >>>>
> >>>> FWIW, my go-to reference tables are 1, updated by Alex.
> >>>>
> >>>> Would it make sense to add a "GFX Core" column?
> >>>
> >>> That's what the GC column is for.
> >>
> >> Oh! Does this stand for "GFX Core", or for "Graphics and Compute"? The
> >> glossary documents GC as the latter. If there is a name conflict, maybe
> >> we can keep using the long name in the table, or document what "GC"
> >> means in a sentence.
> >
> > Both?  The hardware block is called GC, but I think different teams
> > expand it to Graphics Core (as in GCN) or Graphics and Compute.  Same
> > hardware block either way.  I guess we should include both in the
> > glossary.
>
>
> How should I add it? Something like this:
>
> GC/GFX:
>   Graphics and Compute/Core

maybe something like

GC:
   Graphics and Compute or Graphics Core.  Refers to the graphics
hardware block on the GPU.

>
> Thanks
> Siqueira
>
> > Alex
>

Re: [PATCH 1/3] Documentation/gpu: Add info table for ASICs

[Yann Dirson]

Nice!

> diff --git a/Documentation/gpu/amdgpu/apu-asic-info-table.csv
> b/Documentation/gpu/amdgpu/apu-asic-info-table.csv
...
> +Ryzen 3000 series / AMD Ryzen Embedded V1*/R1* with Radeon Vega Gfx,
> RAVEN/PICASSO, DCN 1.0, 9.1.0, VCN 1.0, 4.1.0
...
> +Ryzen 3000 series / AMD Ryzen Embedded V1*/R1* with Radeon Vega Gfx,
> RAVEN2, DCN 1.0, 9.2.2, VCN 1.0.1, 4.1.1

Those similar-but-not-quite lines tend to confuse me :)

Best regards,
-- 
Yann

Re: [PATCH 1/3] Documentation/gpu: Add info table for ASICs

[Rodrigo Siqueira Jordao]

On 2022-06-15 10:34, Yann Dirson wrote:
> Nice!
> 
>> diff --git a/Documentation/gpu/amdgpu/apu-asic-info-table.csv
>> b/Documentation/gpu/amdgpu/apu-asic-info-table.csv
> ...
>> +Ryzen 3000 series / AMD Ryzen Embedded V1*/R1* with Radeon Vega Gfx,
>> RAVEN/PICASSO, DCN 1.0, 9.1.0, VCN 1.0, 4.1.0
> ...
>> +Ryzen 3000 series / AMD Ryzen Embedded V1*/R1* with Radeon Vega Gfx,
>> RAVEN2, DCN 1.0, 9.2.2, VCN 1.0.1, 4.1.1
> 
> Those similar-but-not-quite lines tend to confuse me :)

I guess it will be easier to visualize this data after build the kernel 
doc since the csv file will became an html table.

Thanks
Siqueira

> Best regards,

Re: [PATCH 1/3] Documentation/gpu: Add info table for ASICs

[Yann Dirson]

> 
> On 2022-06-15 10:34, Yann Dirson wrote:
> > Nice!
> > 
> >> diff --git a/Documentation/gpu/amdgpu/apu-asic-info-table.csv
> >> b/Documentation/gpu/amdgpu/apu-asic-info-table.csv
> > ...
> >> +Ryzen 3000 series / AMD Ryzen Embedded V1*/R1* with Radeon Vega
> >> Gfx,
> >> RAVEN/PICASSO, DCN 1.0, 9.1.0, VCN 1.0, 4.1.0
> > ...
> >> +Ryzen 3000 series / AMD Ryzen Embedded V1*/R1* with Radeon Vega
> >> Gfx,
> >> RAVEN2, DCN 1.0, 9.2.2, VCN 1.0.1, 4.1.1
> > 
> > Those similar-but-not-quite lines tend to confuse me :)
> 
> I guess it will be easier to visualize this data after build the
> kernel doc since the csv file will became an html table.

Possibly, though my surprise is rather that 2 different lines in the
table have the same label in their first cell.  Do RAVEN/PICASSO and
RAVEN2 really share the same product name despite different hardware
blocks ?

Re: [PATCH 1/3] Documentation/gpu: Add info table for ASICs

[Alex Deucher]

On Thu, Jun 16, 2022 at 5:48 PM Yann Dirson <ydirson@free.fr> wrote:
>
>
> >
> > On 2022-06-15 10:34, Yann Dirson wrote:
> > > Nice!
> > >
> > >> diff --git a/Documentation/gpu/amdgpu/apu-asic-info-table.csv
> > >> b/Documentation/gpu/amdgpu/apu-asic-info-table.csv
> > > ...
> > >> +Ryzen 3000 series / AMD Ryzen Embedded V1*/R1* with Radeon Vega
> > >> Gfx,
> > >> RAVEN/PICASSO, DCN 1.0, 9.1.0, VCN 1.0, 4.1.0
> > > ...
> > >> +Ryzen 3000 series / AMD Ryzen Embedded V1*/R1* with Radeon Vega
> > >> Gfx,
> > >> RAVEN2, DCN 1.0, 9.2.2, VCN 1.0.1, 4.1.1
> > >
> > > Those similar-but-not-quite lines tend to confuse me :)
> >
> > I guess it will be easier to visualize this data after build the
> > kernel doc since the csv file will became an html table.
>
> Possibly, though my surprise is rather that 2 different lines in the
> table have the same label in their first cell.  Do RAVEN/PICASSO and
> RAVEN2 really share the same product name despite different hardware
> blocks ?

Sort of, the first column is marketing names.  Various Ryzen 3000
variants are Raven or Picasso or Raven2.  There are tons of parts in
that series: Ryzen 3 3100, Ryzen 5 3500, Ryzen 7 3700X, etc.  Same
with the embedded parts: AMD Ryzen Embedded V1202B, AMD Ryzen Embedded
V1807B, etc.  I'm not sure how feasible it is to put every SKU in the
table.

Alex

[PATCH 2/3] Documentation/gpu: Add an explanation about the DCN pipeline

[Rodrigo Siqueira]

In the DCN code, we constantly talk about hardware pipeline, pipeline,
or even just pipes, which is a concept that is not obvious to everyone.
For this reason, this commit expands the DCN overview explanation by
adding a new section that describes what a pipeline is from the DCN
perspective.

Cc: Harry Wentland <harry.wentland@amd.com>
Cc: Nicholas Kazlauskas <Nicholas.Kazlauskas@amd.com>
Cc: Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com>
Cc: Hersen Wu <hersenxs.wu@amd.com>
Cc: Alex Hung <alex.hung@amd.com>
Cc: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Cc: Leo Li <sunpeng.li@amd.com>
Cc: Simon Ser <contact@emersion.fr>
Cc: Pekka Paalanen <pekka.paalanen@collabora.com>
Cc: Sean Paul <seanpaul@chromium.org>
Cc: Mark Yacoub <markyacoub@chromium.org>
Cc: Pierre-Loup <pgriffais@valvesoftware.com>
Cc: Michel Dänzer <michel.daenzer@mailbox.org>
Signed-off-by: Rodrigo Siqueira <Rodrigo.Siqueira@amd.com>
---
 .../gpu/amdgpu/display/dcn-overview.rst       |   58 +
 .../amdgpu/display/pipeline_4k_no_split.svg   |  958 +++++++++++++++
 .../gpu/amdgpu/display/pipeline_4k_split.svg  | 1062 +++++++++++++++++
 3 files changed, 2078 insertions(+)
 create mode 100644 Documentation/gpu/amdgpu/display/pipeline_4k_no_split.svg
 create mode 100644 Documentation/gpu/amdgpu/display/pipeline_4k_split.svg

diff --git a/Documentation/gpu/amdgpu/display/dcn-overview.rst b/Documentation/gpu/amdgpu/display/dcn-overview.rst
index f98624d7828e..430e363fccae 100644
--- a/Documentation/gpu/amdgpu/display/dcn-overview.rst
+++ b/Documentation/gpu/amdgpu/display/dcn-overview.rst
@@ -124,6 +124,64 @@ depth format), bit-depth reduction/dithering would kick in. In OPP, we would
 also apply a regamma function to introduce the gamma removed earlier back.
 Eventually, we output data in integer format at DIO.
 
+AMD Hardware Pipeline
+---------------------
+
+When discussing graphics on Linux, the **pipeline** term is often overloaded
+with multiple meanings, and DCN adds another context to this word. In the DCN
+driver, we use the term **hardware pipeline** or  **pipeline** or just **pipe**
+to indicate how many DCN blocks we are instantiating to address some specific
+configuration. DCN composes those pipelines together when the data reach the
+end of the OPTC block before sending it to the display. We have this pipeline
+concept for trying to save energy and optimize bandwidth utilization while
+providing the maximum performance per watt. It is easier to discuss it if we
+dive into this topic by taking the example of a 4k display in the below
+example:
+
+.. kernel-figure:: pipeline_4k_no_split.svg
+
+Additionally, let's take a look at parts of the DTN log (see
+'Documentation/gpu/amdgpu/display/dc-debug.rst' for more information) since
+this log can help us to see part of this pipeline behavior in real-time::
+
+ HUBP:  format  addr_hi  width  height ...
+ [ 0]:      8h      81h   3840    2160
+ [ 1]:      0h       0h      0       0
+ [ 2]:      0h       0h      0       0
+ [ 3]:      0h       0h      0       0
+ [ 4]:      0h       0h      0       0
+ ...
+ MPCC:  OPP  DPP ...
+ [ 0]:   0h   0h ...
+
+The first thing to notice from the diagram and DTN log it is the fact that we
+have different clock domains for each part of the DCN blocks. In this example,
+we have just a single **pipeline** where the data flows from DCHUB to DIO, as
+we intuitively expect. Nonetheless, DCN is flexible, as mentioned before, and
+we can split this single pipe differently, as described in the below diagram:
+
+.. kernel-figure:: pipeline_4k_split.svg
+
+Now, if we inspect the DTN log again we can see some interesting changes::
+
+ HUBP:  format  addr_hi  width  height ...
+ [ 0]:      8h      81h   1920    2160 ...
+ ...
+ [ 4]:      0h       0h      0       0 ...
+ [ 5]:      8h      81h   1920    2160 ...
+ ...
+ MPCC:  OPP  DPP ...
+ [ 0]:   0h   0h ...
+ [ 5]:   0h   5h ...
+
+From the above example, we now split the display pipeline into two vertical
+parts of 1920x2160 (i.e., 3440x2160), and as a result, we could reduce the
+clock frequency in the DPP part. This is not only useful for saving power but
+also to better handle the required throughput. The idea to keep in mind here is
+that the pipe configuration can vary a lot according to the display
+configuration, and it is the DML's responsibility to set up all required
+configuration parameters for multiple scenarios supported by our hardware.
+
 Global Sync
 -----------
 
diff --git a/Documentation/gpu/amdgpu/display/pipeline_4k_no_split.svg b/Documentation/gpu/amdgpu/display/pipeline_4k_no_split.svg
new file mode 100644
index 000000000000..5fa289d99fcd
--- /dev/null
+++ b/Documentation/gpu/amdgpu/display/pipeline_4k_no_split.svg
@@ -0,0 +1,958 @@
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-- 
2.25.1

Re: [PATCH 2/3] Documentation/gpu: Add an explanation about the DCN pipeline

[Pekka Paalanen]

On Mon, 13 Jun 2022 16:01:11 -0400
Rodrigo Siqueira <Rodrigo.Siqueira@amd.com> wrote:

> In the DCN code, we constantly talk about hardware pipeline, pipeline,
> or even just pipes, which is a concept that is not obvious to everyone.
> For this reason, this commit expands the DCN overview explanation by
> adding a new section that describes what a pipeline is from the DCN
> perspective.
> 
> Cc: Harry Wentland <harry.wentland@amd.com>
> Cc: Nicholas Kazlauskas <Nicholas.Kazlauskas@amd.com>
> Cc: Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com>
> Cc: Hersen Wu <hersenxs.wu@amd.com>
> Cc: Alex Hung <alex.hung@amd.com>
> Cc: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
> Cc: Leo Li <sunpeng.li@amd.com>
> Cc: Simon Ser <contact@emersion.fr>
> Cc: Pekka Paalanen <pekka.paalanen@collabora.com>
> Cc: Sean Paul <seanpaul@chromium.org>
> Cc: Mark Yacoub <markyacoub@chromium.org>
> Cc: Pierre-Loup <pgriffais@valvesoftware.com>
> Cc: Michel Dänzer <michel.daenzer@mailbox.org>
> Signed-off-by: Rodrigo Siqueira <Rodrigo.Siqueira@amd.com>
> ---
>  .../gpu/amdgpu/display/dcn-overview.rst       |   58 +
>  .../amdgpu/display/pipeline_4k_no_split.svg   |  958 +++++++++++++++
>  .../gpu/amdgpu/display/pipeline_4k_split.svg  | 1062 +++++++++++++++++
>  3 files changed, 2078 insertions(+)
>  create mode 100644 Documentation/gpu/amdgpu/display/pipeline_4k_no_split.svg
>  create mode 100644 Documentation/gpu/amdgpu/display/pipeline_4k_split.svg
> 
> diff --git a/Documentation/gpu/amdgpu/display/dcn-overview.rst b/Documentation/gpu/amdgpu/display/dcn-overview.rst
> index f98624d7828e..430e363fccae 100644
> --- a/Documentation/gpu/amdgpu/display/dcn-overview.rst
> +++ b/Documentation/gpu/amdgpu/display/dcn-overview.rst
> @@ -124,6 +124,64 @@ depth format), bit-depth reduction/dithering would kick in. In OPP, we would
>  also apply a regamma function to introduce the gamma removed earlier back.
>  Eventually, we output data in integer format at DIO.
>  

Hi,

always nice to see more docs!

> +AMD Hardware Pipeline
> +---------------------
> +
> +When discussing graphics on Linux, the **pipeline** term is often overloaded
> +with multiple meanings, and DCN adds another context to this word. In the DCN
> +driver, we use the term **hardware pipeline** or  **pipeline** or just **pipe**
> +to indicate how many DCN blocks we are instantiating to address some specific

This seems to say that a "pipeline" is a number, a count (how many).

> +configuration. DCN composes those pipelines together when the data reach the

This seems to imply that each "DCN block" is "a pipeline".

Is either true? Is a pipeline not a sequence of selected DCN blocks
instead?

> +end of the OPTC block before sending it to the display. We have this pipeline
> +concept for trying to save energy and optimize bandwidth utilization while
> +providing the maximum performance per watt. It is easier to discuss it if we
> +dive into this topic by taking the example of a 4k display in the below
> +example:
> +
> +.. kernel-figure:: pipeline_4k_no_split.svg

A bit too hard for me to look at SVGs from email patches, sorry.

You wouldn't happen to have a git branch available in Gitlab or Github
or even cgit somewhere I could visit with my browser?


Thanks,
pq

> +
> +Additionally, let's take a look at parts of the DTN log (see
> +'Documentation/gpu/amdgpu/display/dc-debug.rst' for more information) since
> +this log can help us to see part of this pipeline behavior in real-time::
> +
> + HUBP:  format  addr_hi  width  height ...
> + [ 0]:      8h      81h   3840    2160
> + [ 1]:      0h       0h      0       0
> + [ 2]:      0h       0h      0       0
> + [ 3]:      0h       0h      0       0
> + [ 4]:      0h       0h      0       0
> + ...
> + MPCC:  OPP  DPP ...
> + [ 0]:   0h   0h ...
> +
> +The first thing to notice from the diagram and DTN log it is the fact that we
> +have different clock domains for each part of the DCN blocks. In this example,
> +we have just a single **pipeline** where the data flows from DCHUB to DIO, as
> +we intuitively expect. Nonetheless, DCN is flexible, as mentioned before, and
> +we can split this single pipe differently, as described in the below diagram:
> +
> +.. kernel-figure:: pipeline_4k_split.svg
> +
> +Now, if we inspect the DTN log again we can see some interesting changes::
> +
> + HUBP:  format  addr_hi  width  height ...
> + [ 0]:      8h      81h   1920    2160 ...
> + ...
> + [ 4]:      0h       0h      0       0 ...
> + [ 5]:      8h      81h   1920    2160 ...
> + ...
> + MPCC:  OPP  DPP ...
> + [ 0]:   0h   0h ...
> + [ 5]:   0h   5h ...
> +
> +From the above example, we now split the display pipeline into two vertical
> +parts of 1920x2160 (i.e., 3440x2160), and as a result, we could reduce the
> +clock frequency in the DPP part. This is not only useful for saving power but
> +also to better handle the required throughput. The idea to keep in mind here is
> +that the pipe configuration can vary a lot according to the display
> +configuration, and it is the DML's responsibility to set up all required
> +configuration parameters for multiple scenarios supported by our hardware.
> +
>  Global Sync
>  -----------
>  

Re: [PATCH 2/3] Documentation/gpu: Add an explanation about the DCN pipeline

[Rodrigo Siqueira Jordao]

On 2022-06-15 07:12, Pekka Paalanen wrote:
> On Mon, 13 Jun 2022 16:01:11 -0400
> Rodrigo Siqueira <Rodrigo.Siqueira@amd.com> wrote:
> 
>> In the DCN code, we constantly talk about hardware pipeline, pipeline,
>> or even just pipes, which is a concept that is not obvious to everyone.
>> For this reason, this commit expands the DCN overview explanation by
>> adding a new section that describes what a pipeline is from the DCN
>> perspective.
>>
>> Cc: Harry Wentland <harry.wentland@amd.com>
>> Cc: Nicholas Kazlauskas <Nicholas.Kazlauskas@amd.com>
>> Cc: Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com>
>> Cc: Hersen Wu <hersenxs.wu@amd.com>
>> Cc: Alex Hung <alex.hung@amd.com>
>> Cc: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
>> Cc: Leo Li <sunpeng.li@amd.com>
>> Cc: Simon Ser <contact@emersion.fr>
>> Cc: Pekka Paalanen <pekka.paalanen@collabora.com>
>> Cc: Sean Paul <seanpaul@chromium.org>
>> Cc: Mark Yacoub <markyacoub@chromium.org>
>> Cc: Pierre-Loup <pgriffais@valvesoftware.com>
>> Cc: Michel Dänzer <michel.daenzer@mailbox.org>
>> Signed-off-by: Rodrigo Siqueira <Rodrigo.Siqueira@amd.com>
>> ---
>>   .../gpu/amdgpu/display/dcn-overview.rst       |   58 +
>>   .../amdgpu/display/pipeline_4k_no_split.svg   |  958 +++++++++++++++
>>   .../gpu/amdgpu/display/pipeline_4k_split.svg  | 1062 +++++++++++++++++
>>   3 files changed, 2078 insertions(+)
>>   create mode 100644 Documentation/gpu/amdgpu/display/pipeline_4k_no_split.svg
>>   create mode 100644 Documentation/gpu/amdgpu/display/pipeline_4k_split.svg
>>
>> diff --git a/Documentation/gpu/amdgpu/display/dcn-overview.rst b/Documentation/gpu/amdgpu/display/dcn-overview.rst
>> index f98624d7828e..430e363fccae 100644
>> --- a/Documentation/gpu/amdgpu/display/dcn-overview.rst
>> +++ b/Documentation/gpu/amdgpu/display/dcn-overview.rst
>> @@ -124,6 +124,64 @@ depth format), bit-depth reduction/dithering would kick in. In OPP, we would
>>   also apply a regamma function to introduce the gamma removed earlier back.
>>   Eventually, we output data in integer format at DIO.
>>   
> 
> Hi,
> 
> always nice to see more docs!

Hi Pekka,

First of all, thanks for your review.

> 
>> +AMD Hardware Pipeline
>> +---------------------
>> +
>> +When discussing graphics on Linux, the **pipeline** term is often overloaded
>> +with multiple meanings, and DCN adds another context to this word. In the DCN
>> +driver, we use the term **hardware pipeline** or  **pipeline** or just **pipe**
>> +to indicate how many DCN blocks we are instantiating to address some specific
> 
> This seems to say that a "pipeline" is a number, a count (how many).
> 
>> +configuration. DCN composes those pipelines together when the data reach the
> 
> This seems to imply that each "DCN block" is "a pipeline".
> 
> Is either true? Is a pipeline not a sequence of selected DCN blocks
> instead?

In the DCN we can have different pipeline configurations. For example, 
see the below picture:

 
https://www.kernel.org/doc/html/latest/gpu/amdgpu/display/dcn-overview.html

Let's say that our pipeline policy does not allow pipe split, in that 
case we will have just one instance of each component. However, if we 
decided to split our pipe, we will have more instance of the other 
components (e.g., 2 DPP). I added some examples about it a little bit 
below in this patch.

Try to apply my series in your local kernel [1]. That way you will be 
able to open the svg files at Documentation/gpu/amdgpu/display/.

Maybe I can rephrase it, do you have some suggestions?

1. https://patchwork.freedesktop.org/series/105071/

Thanks
Siqueira

>> +end of the OPTC block before sending it to the display. We have this pipeline
>> +concept for trying to save energy and optimize bandwidth utilization while
>> +providing the maximum performance per watt. It is easier to discuss it if we
>> +dive into this topic by taking the example of a 4k display in the below
>> +example:
>> +
>> +.. kernel-figure:: pipeline_4k_no_split.svg
> 
> A bit too hard for me to look at SVGs from email patches, sorry.
> 
> You wouldn't happen to have a git branch available in Gitlab or Github
> or even cgit somewhere I could visit with my browser?
> 
> 
> Thanks,
> pq
> 
>> +
>> +Additionally, let's take a look at parts of the DTN log (see
>> +'Documentation/gpu/amdgpu/display/dc-debug.rst' for more information) since
>> +this log can help us to see part of this pipeline behavior in real-time::
>> +
>> + HUBP:  format  addr_hi  width  height ...
>> + [ 0]:      8h      81h   3840    2160
>> + [ 1]:      0h       0h      0       0
>> + [ 2]:      0h       0h      0       0
>> + [ 3]:      0h       0h      0       0
>> + [ 4]:      0h       0h      0       0
>> + ...
>> + MPCC:  OPP  DPP ...
>> + [ 0]:   0h   0h ...
>> +
>> +The first thing to notice from the diagram and DTN log it is the fact that we
>> +have different clock domains for each part of the DCN blocks. In this example,
>> +we have just a single **pipeline** where the data flows from DCHUB to DIO, as
>> +we intuitively expect. Nonetheless, DCN is flexible, as mentioned before, and
>> +we can split this single pipe differently, as described in the below diagram:
>> +
>> +.. kernel-figure:: pipeline_4k_split.svg
>> +
>> +Now, if we inspect the DTN log again we can see some interesting changes::
>> +
>> + HUBP:  format  addr_hi  width  height ...
>> + [ 0]:      8h      81h   1920    2160 ...
>> + ...
>> + [ 4]:      0h       0h      0       0 ...
>> + [ 5]:      8h      81h   1920    2160 ...
>> + ...
>> + MPCC:  OPP  DPP ...
>> + [ 0]:   0h   0h ...
>> + [ 5]:   0h   5h ...
>> +
>> +From the above example, we now split the display pipeline into two vertical
>> +parts of 1920x2160 (i.e., 3440x2160), and as a result, we could reduce the
>> +clock frequency in the DPP part. This is not only useful for saving power but
>> +also to better handle the required throughput. The idea to keep in mind here is
>> +that the pipe configuration can vary a lot according to the display
>> +configuration, and it is the DML's responsibility to set up all required
>> +configuration parameters for multiple scenarios supported by our hardware.
>> +
>>   Global Sync
>>   -----------
>>   

Re: [PATCH 2/3] Documentation/gpu: Add an explanation about the DCN pipeline

[Pekka Paalanen]

On Thu, 16 Jun 2022 17:59:21 -0400
Rodrigo Siqueira Jordao <Rodrigo.Siqueira@amd.com> wrote:

> On 2022-06-15 07:12, Pekka Paalanen wrote:
> > On Mon, 13 Jun 2022 16:01:11 -0400
> > Rodrigo Siqueira <Rodrigo.Siqueira@amd.com> wrote:
> >   
> >> In the DCN code, we constantly talk about hardware pipeline, pipeline,
> >> or even just pipes, which is a concept that is not obvious to everyone.
> >> For this reason, this commit expands the DCN overview explanation by
> >> adding a new section that describes what a pipeline is from the DCN
> >> perspective.
> >>
> >> Cc: Harry Wentland <harry.wentland@amd.com>
> >> Cc: Nicholas Kazlauskas <Nicholas.Kazlauskas@amd.com>
> >> Cc: Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com>
> >> Cc: Hersen Wu <hersenxs.wu@amd.com>
> >> Cc: Alex Hung <alex.hung@amd.com>
> >> Cc: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
> >> Cc: Leo Li <sunpeng.li@amd.com>
> >> Cc: Simon Ser <contact@emersion.fr>
> >> Cc: Pekka Paalanen <pekka.paalanen@collabora.com>
> >> Cc: Sean Paul <seanpaul@chromium.org>
> >> Cc: Mark Yacoub <markyacoub@chromium.org>
> >> Cc: Pierre-Loup <pgriffais@valvesoftware.com>
> >> Cc: Michel Dänzer <michel.daenzer@mailbox.org>
> >> Signed-off-by: Rodrigo Siqueira <Rodrigo.Siqueira@amd.com>
> >> ---
> >>   .../gpu/amdgpu/display/dcn-overview.rst       |   58 +
> >>   .../amdgpu/display/pipeline_4k_no_split.svg   |  958 +++++++++++++++
> >>   .../gpu/amdgpu/display/pipeline_4k_split.svg  | 1062 +++++++++++++++++
> >>   3 files changed, 2078 insertions(+)
> >>   create mode 100644 Documentation/gpu/amdgpu/display/pipeline_4k_no_split.svg
> >>   create mode 100644 Documentation/gpu/amdgpu/display/pipeline_4k_split.svg
> >>
> >> diff --git a/Documentation/gpu/amdgpu/display/dcn-overview.rst b/Documentation/gpu/amdgpu/display/dcn-overview.rst
> >> index f98624d7828e..430e363fccae 100644
> >> --- a/Documentation/gpu/amdgpu/display/dcn-overview.rst
> >> +++ b/Documentation/gpu/amdgpu/display/dcn-overview.rst
> >> @@ -124,6 +124,64 @@ depth format), bit-depth reduction/dithering would kick in. In OPP, we would
> >>   also apply a regamma function to introduce the gamma removed earlier back.
> >>   Eventually, we output data in integer format at DIO.
> >>     
> > 
> > Hi,
> > 
> > always nice to see more docs!  
> 
> Hi Pekka,
> 
> First of all, thanks for your review.
> 
> >   
> >> +AMD Hardware Pipeline
> >> +---------------------
> >> +
> >> +When discussing graphics on Linux, the **pipeline** term is often overloaded
> >> +with multiple meanings, and DCN adds another context to this word. In the DCN
> >> +driver, we use the term **hardware pipeline** or  **pipeline** or just **pipe**
> >> +to indicate how many DCN blocks we are instantiating to address some specific  
> > 
> > This seems to say that a "pipeline" is a number, a count (how many).
> >   
> >> +configuration. DCN composes those pipelines together when the data reach the  
> > 
> > This seems to imply that each "DCN block" is "a pipeline".
> > 
> > Is either true? Is a pipeline not a sequence of selected DCN blocks
> > instead?  
> 
> In the DCN we can have different pipeline configurations. For example, 
> see the below picture:
> 
>  
> https://www.kernel.org/doc/html/latest/gpu/amdgpu/display/dcn-overview.html
> 
> Let's say that our pipeline policy does not allow pipe split, in that 
> case we will have just one instance of each component. However, if we 
> decided to split our pipe, we will have more instance of the other 
> components (e.g., 2 DPP). I added some examples about it a little bit 
> below in this patch.
> 
> Try to apply my series in your local kernel [1]. That way you will be 
> able to open the svg files at Documentation/gpu/amdgpu/display/.

Sorry, that's too much to ask for patch review on a project I don't
work on.

> Maybe I can rephrase it, do you have some suggestions?

I'm not sure what your definition of a pipeline is. If you have split
blocks, does that mean you have one pipeline or multiple pipelines?
Does block splitting allow to create multiple pipelines in the sense
that they do not all contain the exact same blocks?

The only thing I could suggest is to not say that a pipeline is a
count. That would be done by replacing "to indicate how many DCN
blocks" by "to indicate which DCN blocks".


Thanks,
pq

> 1. https://patchwork.freedesktop.org/series/105071/
> 
> Thanks
> Siqueira
> 
> >> +end of the OPTC block before sending it to the display. We have this pipeline
> >> +concept for trying to save energy and optimize bandwidth utilization while
> >> +providing the maximum performance per watt. It is easier to discuss it if we
> >> +dive into this topic by taking the example of a 4k display in the below
> >> +example:
> >> +
> >> +.. kernel-figure:: pipeline_4k_no_split.svg  
> > 
> > A bit too hard for me to look at SVGs from email patches, sorry.
> > 
> > You wouldn't happen to have a git branch available in Gitlab or Github
> > or even cgit somewhere I could visit with my browser?
> > 
> > 
> > Thanks,
> > pq

Re: [PATCH 2/3] Documentation/gpu: Add an explanation about the DCN pipeline

[Harry Wentland]

On 6/17/22 03:35, Pekka Paalanen wrote:
> On Thu, 16 Jun 2022 17:59:21 -0400
> Rodrigo Siqueira Jordao <Rodrigo.Siqueira@amd.com> wrote:
> 
>> On 2022-06-15 07:12, Pekka Paalanen wrote:
>>> On Mon, 13 Jun 2022 16:01:11 -0400
>>> Rodrigo Siqueira <Rodrigo.Siqueira@amd.com> wrote:
>>>   
>>>> In the DCN code, we constantly talk about hardware pipeline, pipeline,
>>>> or even just pipes, which is a concept that is not obvious to everyone.
>>>> For this reason, this commit expands the DCN overview explanation by
>>>> adding a new section that describes what a pipeline is from the DCN
>>>> perspective.
>>>>
>>>> Cc: Harry Wentland <harry.wentland@amd.com>
>>>> Cc: Nicholas Kazlauskas <Nicholas.Kazlauskas@amd.com>
>>>> Cc: Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com>
>>>> Cc: Hersen Wu <hersenxs.wu@amd.com>
>>>> Cc: Alex Hung <alex.hung@amd.com>
>>>> Cc: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
>>>> Cc: Leo Li <sunpeng.li@amd.com>
>>>> Cc: Simon Ser <contact@emersion.fr>
>>>> Cc: Pekka Paalanen <pekka.paalanen@collabora.com>
>>>> Cc: Sean Paul <seanpaul@chromium.org>
>>>> Cc: Mark Yacoub <markyacoub@chromium.org>
>>>> Cc: Pierre-Loup <pgriffais@valvesoftware.com>
>>>> Cc: Michel Dänzer <michel.daenzer@mailbox.org>
>>>> Signed-off-by: Rodrigo Siqueira <Rodrigo.Siqueira@amd.com>
>>>> ---
>>>>   .../gpu/amdgpu/display/dcn-overview.rst       |   58 +
>>>>   .../amdgpu/display/pipeline_4k_no_split.svg   |  958 +++++++++++++++
>>>>   .../gpu/amdgpu/display/pipeline_4k_split.svg  | 1062 +++++++++++++++++
>>>>   3 files changed, 2078 insertions(+)
>>>>   create mode 100644 Documentation/gpu/amdgpu/display/pipeline_4k_no_split.svg
>>>>   create mode 100644 Documentation/gpu/amdgpu/display/pipeline_4k_split.svg
>>>>
>>>> diff --git a/Documentation/gpu/amdgpu/display/dcn-overview.rst b/Documentation/gpu/amdgpu/display/dcn-overview.rst
>>>> index f98624d7828e..430e363fccae 100644
>>>> --- a/Documentation/gpu/amdgpu/display/dcn-overview.rst
>>>> +++ b/Documentation/gpu/amdgpu/display/dcn-overview.rst
>>>> @@ -124,6 +124,64 @@ depth format), bit-depth reduction/dithering would kick in. In OPP, we would
>>>>   also apply a regamma function to introduce the gamma removed earlier back.
>>>>   Eventually, we output data in integer format at DIO.
>>>>     
>>>
>>> Hi,
>>>
>>> always nice to see more docs!  
>>
>> Hi Pekka,
>>
>> First of all, thanks for your review.
>>
>>>   
>>>> +AMD Hardware Pipeline
>>>> +---------------------
>>>> +
>>>> +When discussing graphics on Linux, the **pipeline** term is often overloaded
>>>> +with multiple meanings, and DCN adds another context to this word. In the DCN
>>>> +driver, we use the term **hardware pipeline** or  **pipeline** or just **pipe**
>>>> +to indicate how many DCN blocks we are instantiating to address some specific  
>>>
>>> This seems to say that a "pipeline" is a number, a count (how many).
>>>   
>>>> +configuration. DCN composes those pipelines together when the data reach the  
>>>
>>> This seems to imply that each "DCN block" is "a pipeline".
>>>
>>> Is either true? Is a pipeline not a sequence of selected DCN blocks
>>> instead?  
>>


I think the confusion stems from unfortunate phrasing.

Siqueira, you seem to be saying that a **pipeline** is indicating
how many DCN blocks we're instantiating. This is incorrect and
confusing. We have a number of pipelines for each SoC, e.g. 4 for
many APUs and 6 for many dGPUs.

A pipeline is a sequence of HW blocks:
HUBP > DPP > MPC > OPP > etc.

DC treats those as individual resources, so we build a pipeline
conceptually by taking resources for all individual HW blocks
to compose one pipeline but in actuality (in HW) these blocks are
not arbitrarily configurable. What we can do is combine pipes at
the MPC as such

HUBP > DPP > MPC > OPP > output
HUBP > DPP > MPC ^

In addition the DSC block can be assigned to pipelines as needed.

So, in short we have a number of pipelines per SoC. If we have 4 pipes
we have 4 HUBPs, 4 DPPs, 4 MPCc, etc. There are few exceptions to that,
like the DSC block.

On the output side we have a number of different encoders that are attached
to our output connectors. Each pipe is routed to the appropriate encoder
for the display output.

Harry

>> In the DCN we can have different pipeline configurations. For example, 
>> see the below picture:
>>
>>  
>> https://nam11.safelinks.protection.outlook.com/?url=https%3A%2F%2Fwww.kernel.org%2Fdoc%2Fhtml%2Flatest%2Fgpu%2Famdgpu%2Fdisplay%2Fdcn-overview.html&amp;data=05%7C01%7Charry.wentland%40amd.com%7C5c60cfb7c2e5483e1b0d08da5033f013%7C3dd8961fe4884e608e11a82d994e183d%7C0%7C0%7C637910481695853125%7CUnknown%7CTWFpbGZsb3d8eyJWIjoiMC4wLjAwMDAiLCJQIjoiV2luMzIiLCJBTiI6Ik1haWwiLCJXVCI6Mn0%3D%7C2000%7C%7C%7C&amp;sdata=TX6JmSkn2ybJSqtOz7DRl4q745qzsCLYSkQ0RvAXsrk%3D&amp;reserved=0
>>
>> Let's say that our pipeline policy does not allow pipe split, in that 
>> case we will have just one instance of each component. However, if we 
>> decided to split our pipe, we will have more instance of the other 
>> components (e.g., 2 DPP). I added some examples about it a little bit 
>> below in this patch.
>>
>> Try to apply my series in your local kernel [1]. That way you will be 
>> able to open the svg files at Documentation/gpu/amdgpu/display/.
> 
> Sorry, that's too much to ask for patch review on a project I don't
> work on.
> 
>> Maybe I can rephrase it, do you have some suggestions?
> 
> I'm not sure what your definition of a pipeline is. If you have split
> blocks, does that mean you have one pipeline or multiple pipelines?
> Does block splitting allow to create multiple pipelines in the sense
> that they do not all contain the exact same blocks?
> 
> The only thing I could suggest is to not say that a pipeline is a
> count. That would be done by replacing "to indicate how many DCN
> blocks" by "to indicate which DCN blocks".
> 
> 
> Thanks,
> pq
> 
>> 1. https://nam11.safelinks.protection.outlook.com/?url=https%3A%2F%2Fpatchwork.freedesktop.org%2Fseries%2F105071%2F&amp;data=05%7C01%7Charry.wentland%40amd.com%7C5c60cfb7c2e5483e1b0d08da5033f013%7C3dd8961fe4884e608e11a82d994e183d%7C0%7C0%7C637910481695853125%7CUnknown%7CTWFpbGZsb3d8eyJWIjoiMC4wLjAwMDAiLCJQIjoiV2luMzIiLCJBTiI6Ik1haWwiLCJXVCI6Mn0%3D%7C2000%7C%7C%7C&amp;sdata=MYx6R8tIvFu6f46Rj7GWH4MIfa7bjYjdYitFnc6wNZs%3D&amp;reserved=0
>>
>> Thanks
>> Siqueira
>>
>>>> +end of the OPTC block before sending it to the display. We have this pipeline
>>>> +concept for trying to save energy and optimize bandwidth utilization while
>>>> +providing the maximum performance per watt. It is easier to discuss it if we
>>>> +dive into this topic by taking the example of a 4k display in the below
>>>> +example:
>>>> +
>>>> +.. kernel-figure:: pipeline_4k_no_split.svg  
>>>
>>> A bit too hard for me to look at SVGs from email patches, sorry.
>>>
>>> You wouldn't happen to have a git branch available in Gitlab or Github
>>> or even cgit somewhere I could visit with my browser?
>>>
>>>
>>> Thanks,
>>> pq

[PATCH 3/3] Documentation/gpu: Add Multiplane Overlay doc

[Rodrigo Siqueira]

Multiple plane overlay is a feature supported by AMD hardware, but it
has specific details that deserve proper documentation. This commit
introduces a documentation that describes some of the features,
limitations, and use cases for this feature. Part of this documentation
came from some discussion in the public upstream [1][2].

[1]. https://lore.kernel.org/amd-gfx/3qY-QeukF_Q_MJeIXAuBjO4szbS4jRtqkTifXnbnN3bp88SxVodFQRpah3mIIVJq24DUkF6g0rOGdCmSqTvVxx9LCGEItmzLw8uWU44jtXE=@emersion.fr/
[2]. https://lore.kernel.org/amd-gfx/864e45d0-c14b-3b12-0f5b-9d26a9cb41bd@amd.com/

Cc: Harry Wentland <harry.wentland@amd.com>
Cc: Nicholas Kazlauskas <Nicholas.Kazlauskas@amd.com>
Cc: Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com>
Cc: Hersen Wu <hersenxs.wu@amd.com>
Cc: Alex Hung <alex.hung@amd.com>
Cc: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Cc: Simon Ser <contact@emersion.fr>
Cc: Pekka Paalanen <pekka.paalanen@collabora.com>
Cc: Sean Paul <seanpaul@chromium.org>
Cc: Mark Yacoub <markyacoub@chromium.org>
Cc: Leo Li <sunpeng.li@amd.com>
Cc: Pierre-Loup <pgriffais@valvesoftware.com>
Cc: Michel Dänzer <michel.daenzer@mailbox.org>
Signed-off-by: Rodrigo Siqueira <Rodrigo.Siqueira@amd.com>
---
 Documentation/gpu/amdgpu/display/index.rst    |   1 +
 .../gpu/amdgpu/display/mpo-cursor.svg         | 435 ++++++++++++++++++
 .../gpu/amdgpu/display/mpo-overview.rst       | 242 ++++++++++
 .../multi-display-hdcp-mpo-less-pipe-ex.svg   | 220 +++++++++
 .../amdgpu/display/multi-display-hdcp-mpo.svg | 171 +++++++
 .../single-display-mpo-multi-video.svg        | 339 ++++++++++++++
 .../gpu/amdgpu/display/single-display-mpo.svg | 266 +++++++++++
 7 files changed, 1674 insertions(+)
 create mode 100644 Documentation/gpu/amdgpu/display/mpo-cursor.svg
 create mode 100644 Documentation/gpu/amdgpu/display/mpo-overview.rst
 create mode 100644 Documentation/gpu/amdgpu/display/multi-display-hdcp-mpo-less-pipe-ex.svg
 create mode 100644 Documentation/gpu/amdgpu/display/multi-display-hdcp-mpo.svg
 create mode 100644 Documentation/gpu/amdgpu/display/single-display-mpo-multi-video.svg
 create mode 100644 Documentation/gpu/amdgpu/display/single-display-mpo.svg

diff --git a/Documentation/gpu/amdgpu/display/index.rst b/Documentation/gpu/amdgpu/display/index.rst
index c1fb2fb3c710..f8a4f53d70d8 100644
--- a/Documentation/gpu/amdgpu/display/index.rst
+++ b/Documentation/gpu/amdgpu/display/index.rst
@@ -28,4 +28,5 @@ table of content:
    display-manager.rst
    dc-debug.rst
    dcn-overview.rst
+   mpo-overview.rst
    dc-glossary.rst
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diff --git a/Documentation/gpu/amdgpu/display/mpo-overview.rst b/Documentation/gpu/amdgpu/display/mpo-overview.rst
new file mode 100644
index 000000000000..0499aa92d08d
--- /dev/null
+++ b/Documentation/gpu/amdgpu/display/mpo-overview.rst
@@ -0,0 +1,242 @@
+========================
+Multiplane Overlay (MPO)
+========================
+
+.. note:: You will get more from this page if you have already read the
+   'Documentation/gpu/amdgpu/display/dcn-overview.rst'.
+
+
+Multiplane Overlay (MPO) allows for multiple framebuffers to be composited via
+fixed-function hardware in the display controller rather than using graphics or
+compute shaders for composition. This can yield some power savings if it means
+the graphics/compute pipelines can be put into low-power states. In summary,
+MPO can bring the following benefits:
+
+* Decreased GPU and CPU workload - no composition shaders needed, no extra
+  buffer copy needed, GPU can remain idle.
+* Plane independent page flips - No need to be tied to global compositor
+  page-flip present rate, reduced latency, independent timing.
+
+.. note:: Keep in mind that MPO is all about power-saving; if you want to learn
+   more about power-save in the display context, check the link:
+   `Power <https://gitlab.freedesktop.org/pq/color-and-hdr/-/blob/main/doc/power.rst>`__.
+
+Multiplane Overlay is only available using the DRM atomic model. The atomic
+model only uses a single userspace IOCTL for configuring the display hardware
+(modesetting, page-flipping, etc) - drmModeAtomicCommit. To query hardware
+resources and limitations userspace also calls into drmModeGetResources which
+reports back the number of planes, CRTCs, and connectors. There are three types
+of DRM planes that the driver can register and work with:
+
+* ``DRM_PLANE_TYPE_PRIMARY``: Primary planes represent a "main" plane for a
+  CRTC, primary planes are the planes operated upon by CRTC modesetting and
+  flipping operations.
+* ``DRM_PLANE_TYPE_CURSOR``: Cursor planes represent a "cursor" plane for a
+  CRTC. Cursor planes are the planes operated upon by the cursor IOCTLs
+* ``DRM_PLANE_TYPE_OVERLAY``: Overlay planes represent all non-primary,
+  non-cursor planes. Some drivers refer to these types of planes as "sprites"
+  internally.
+
+To illustrate how it works, let's take a look at a device that exposes the
+following planes to userspace:
+
+* 4 Primary planes (1 per CRTC).
+* 4 Cursor planes (1 per CRTC).
+* 1 Overlay plane (shared among CRTCs).
+
+.. note:: Keep in mind that different ASICs might expose other numbers of
+   planes.
+
+For this hardware example, we have 4 pipes (if you don't know what AMD pipe
+means, look at 'Documentation/gpu/amdgpu/display/dcn-overview.rst', section
+"AMD Hardware Pipeline"). Typically most AMD devices operate in a pipe-split
+configuration for optimal single display output (e.g., 2 pipes per plane).
+
+A typical MPO configuration from userspace - 1 primary + 1 overlay on a single
+display - will see 4 pipes in use, 2 per plane.
+
+At least 1 pipe must be used per plane (primary and overlay), so for this
+hypothetical hardware that we are using as an example, we have an absolute
+limit of 4 planes across all CRTCs. Atomic commits will be rejected for display
+configurations using more than 4 planes. Again, it is important to stress that
+every DCN has different restrictions; here, we are just trying to provide the
+concept idea.
+
+Plane Restrictions
+==================
+
+AMDGPU imposes restrictions on the use of DRM planes in the driver.
+
+Atomic commits will be rejected for commits which do not follow these
+restrictions:
+
+* Overlay planes must be in ARGB8888 or XRGB8888 format
+* Planes cannot be placed outside of the CRTC destination rectangle
+* Planes cannot be downscaled more than 1/4x of their original size
+* Planes cannot be upscaled more than 16x of their original size
+
+Not every property is available on every plane:
+
+* Only primary planes have color-space and non-RGB format support
+* Only overlay planes have alpha blending support
+
+Cursor Restrictions
+===================
+
+Before we start to describe some restrictions around cursor and MPO, see the
+below image:
+
+.. kernel-figure:: mpo-cursor.svg
+
+The image on the left side represents how DRM expects the cursor and planes to
+be blended. However, AMD hardware handles cursors differently, as you can see
+on the right side; basically, our cursor cannot be drawn outside its associated
+plane as it is being treated as part of the plane. Another consequence of that
+is that cursors inherit the color and scale from the plane.
+
+As a result of the above behavior, do not use legacy API to set up the cursor
+plane when working with MPO; otherwise, you might encounter unexpected
+behavior.
+
+In short, AMD HW has no dedicated cursor planes. A cursor is attached to
+another plane and therefore inherits any scaling or color processing from its
+parent plane.
+
+Use Cases
+=========
+
+Picture-in-Picture (PIP) playback - Underlay strategy
+-----------------------------------------------------
+
+Video playback should be done using the "primary plane as underlay" MPO
+strategy. This is a 2 planes configuration:
+
+* 1 YUV DRM Primary Plane (e.g. NV12 Video)
+* 1 RGBA DRM Overlay Plane (e.g. ARGB8888 desktop). The compositor should
+  prepare the framebuffers for the planes as follows:
+  - The overlay plane contains general desktop UI, video player controls, and video subtitles
+  - Primary plane contains one or more videos
+
+.. note:: Keep in mind that we could extend this configuration to more planes,
+   but that is currently not supported by our driver yet (maybe if we have a
+   userspace request in the future, we can change that).
+
+See below a single-video example:
+
+.. kernel-figure:: single-display-mpo.svg
+
+.. note:: We could extend this behavior to more planes, but that is currently
+   not supported by our driver.
+
+The video buffer should be used directly for the primary plane. The video can
+be scaled and positioned for the desktop using the properties: CRTC_X, CRTC_Y,
+CRTC_W, and CRTC_H. The primary plane should also have the color encoding and
+color range properties set based on the source content:
+
+* ``COLOR_RANGE``, ``COLOR_ENCODING``
+
+The overlay plane should be the native size of the CRTC. The compositor must
+draw a transparent cutout for where the video should be placed on the desktop
+(i.e., set the alpha to zero). The primary plane video will be visible through
+the underlay. The overlay plane's buffer may remain static while the primary
+plane's framebuffer is used for standard double-buffered playback.
+
+The compositor should create a YUV buffer matching the native size of the CRTC.
+Each video buffer should be composited onto this YUV buffer for direct YUV
+scanout. The primary plane should have the color encoding and color range
+properties set based on the source content: ``COLOR_RANGE``,
+``COLOR_ENCODING``. However, be mindful that the source color space and
+encoding match for each video since it affect the entire plane.
+
+The overlay plane should be the native size of the CRTC. The compositor must
+draw a transparent cutout for where each video should be placed on the desktop
+(i.e., set the alpha to zero). The primary plane videos will be visible through
+the underlay. The overlay plane's buffer may remain static while compositing
+operations for video playback will be done on the video buffer.
+
+This kernel interface is validated using IGT GPU Tools. The following tests can
+be run to validate positioning, blending, scaling under a variety of sequences
+and interactions with operations such as DPMS and S3:
+
+- ``kms_plane@plane-panning-bottom-right-pipe-*-planes``
+- ``kms_plane@plane-panning-bottom-right-suspend-pipe-*-``
+- ``kms_plane@plane-panning-top-left-pipe-*-``
+- ``kms_plane@plane-position-covered-pipe-*-``
+- ``kms_plane@plane-position-hole-dpms-pipe-*-``
+- ``kms_plane@plane-position-hole-pipe-*-``
+- ``kms_plane_multiple@atomic-pipe-*-tiling-``
+- ``kms_plane_scaling@pipe-*-plane-scaling``
+- ``kms_plane_alpha_blend@pipe-*-alpha-basic``
+- ``kms_plane_alpha_blend@pipe-*-alpha-transparant-fb``
+- ``kms_plane_alpha_blend@pipe-*-alpha-opaque-fb``
+- ``kms_plane_alpha_blend@pipe-*-constant-alpha-min``
+- ``kms_plane_alpha_blend@pipe-*-constant-alpha-mid``
+- ``kms_plane_alpha_blend@pipe-*-constant-alpha-max``
+
+Multiple Display MPO
+--------------------
+
+AMDGPU supports display MPO when using multiple displays; however, this feature
+behavior heavily relies on the compositor implementation. Keep in mind that
+usespace can define different policies. For example, some OSes can use MPO to
+protect the plane that handles the video playback; notice that we don't have
+many limitations for a single display. Nonetheless, this manipulation can have
+many more restrictions for a multi-display scenario. The below example shows a
+video playback in the middle of two displays, and it is up to the compositor to
+define a policy on how to handle it:
+
+.. kernel-figure:: multi-display-hdcp-mpo.svg
+
+Let's discuss some of the hardware limitations we have when dealing with
+multi-display with MPO.
+
+Limitations
+~~~~~~~~~~~
+
+For simplicity's sake, for discussing the hardware limitation, this
+documentation supposes an example where we have two displays and video playback
+that will be moved around different displays.
+
+* **Hardware limitations**
+
+From the DCN overview page, each display requires at least one pipe and each
+MPO plane needs another pipe. As a result, when the video is in the middle of
+the two displays, we need to use 2 pipes. See the example below where we avoid
+pipe split:
+
+- 1 display (1 pipe) + MPO (1 pipe), we will use two pipes
+- 2 displays (2 pipes) + MPO (1-2 pipes); we will use 4 pipes. MPO in the
+  middle of both displays needs 2 pipes.
+- 3 Displays (3 pipes) + MPO (1-2 pipes), we need 5 pipes.
+
+If we use MPO with multiple displays, the userspace has to decide to enable
+multiple MPO by the price of limiting the number of external displays supported
+or disable it in favor of multiple displays; it is a policy decision. For
+example:
+
+* When ASIC has 3 pipes, AMD hardware can NOT support 2 displays with MPO
+* When ASIC has 4 pipes, AMD hardware can NOT support 3 displays with MPO
+
+Let's briefly explore how userspace can handle these two display configurations
+on an ASIC that only supports three pipes. We can have:
+
+.. kernel-figure:: multi-display-hdcp-mpo-less-pipe-ex.svg
+
+- Total pipes are 3
+- User lights up 2 displays (2 out of 3 pipes are used)
+- User launches video (1 pipe used for MPO)
+- Now, if the user moves the video in the middle of 2 displays, one part of the
+  video won't be MPO since we have used 3/3 pipes.
+
+* **Scaling limitation**
+
+MPO cannot handle scaling less than 0.25 and more than x16. For example:
+
+If 4k video (3840x2160) is playing in windowed mode, the physical size of the
+window cannot be smaller than (960x540).
+
+.. note:: These scaling limitations might vary from ASIC to ASIC.
+
+* **Size Limitation**
+
+The minimum MPO size is 12px.
diff --git a/Documentation/gpu/amdgpu/display/multi-display-hdcp-mpo-less-pipe-ex.svg b/Documentation/gpu/amdgpu/display/multi-display-hdcp-mpo-less-pipe-ex.svg
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