From: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
To: Max Chou <max.chou@sifive.com>,
qemu-devel@nongnu.org, qemu-riscv@nongnu.org
Cc: Palmer Dabbelt <palmer@dabbelt.com>,
Alistair Francis <alistair.francis@wdc.com>,
Weiwei Li <liwei1518@gmail.com>,
Liu Zhiwei <zhiwei_liu@linux.alibaba.com>,
antonb@tenstorrent.com
Subject: Re: [PATCH v2 12/12] target/riscv: Fix the rvv reserved encoding of unmasked instructions
Date: Sat, 5 Apr 2025 06:21:20 -0300 [thread overview]
Message-ID: <6c3b3613-00a2-4d94-9502-5f87b61d2bd6@ventanamicro.com> (raw)
In-Reply-To: <20250329144446.2619306-13-max.chou@sifive.com>
On 3/29/25 11:44 AM, Max Chou wrote:
> According to the v spec, the encodings of vcomoress.vm and vector
> mask-register logical instructions with vm=0 are reserved.
>
> Signed-off-by: Max Chou <max.chou@sifive.com>
> ---
Reviewed-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
> target/riscv/insn32.decode | 18 +++++++++---------
> 1 file changed, 9 insertions(+), 9 deletions(-)
>
> diff --git a/target/riscv/insn32.decode b/target/riscv/insn32.decode
> index 6d1a13c8260..cd23b1f3a9b 100644
> --- a/target/riscv/insn32.decode
> +++ b/target/riscv/insn32.decode
> @@ -703,14 +703,14 @@ vfredmax_vs 000111 . ..... ..... 001 ..... 1010111 @r_vm
> # Vector widening ordered and unordered float reduction sum
> vfwredusum_vs 110001 . ..... ..... 001 ..... 1010111 @r_vm
> vfwredosum_vs 110011 . ..... ..... 001 ..... 1010111 @r_vm
> -vmand_mm 011001 - ..... ..... 010 ..... 1010111 @r
> -vmnand_mm 011101 - ..... ..... 010 ..... 1010111 @r
> -vmandn_mm 011000 - ..... ..... 010 ..... 1010111 @r
> -vmxor_mm 011011 - ..... ..... 010 ..... 1010111 @r
> -vmor_mm 011010 - ..... ..... 010 ..... 1010111 @r
> -vmnor_mm 011110 - ..... ..... 010 ..... 1010111 @r
> -vmorn_mm 011100 - ..... ..... 010 ..... 1010111 @r
> -vmxnor_mm 011111 - ..... ..... 010 ..... 1010111 @r
> +vmand_mm 011001 1 ..... ..... 010 ..... 1010111 @r
> +vmnand_mm 011101 1 ..... ..... 010 ..... 1010111 @r
> +vmandn_mm 011000 1 ..... ..... 010 ..... 1010111 @r
> +vmxor_mm 011011 1 ..... ..... 010 ..... 1010111 @r
> +vmor_mm 011010 1 ..... ..... 010 ..... 1010111 @r
> +vmnor_mm 011110 1 ..... ..... 010 ..... 1010111 @r
> +vmorn_mm 011100 1 ..... ..... 010 ..... 1010111 @r
> +vmxnor_mm 011111 1 ..... ..... 010 ..... 1010111 @r
> vcpop_m 010000 . ..... 10000 010 ..... 1010111 @r2_vm
> vfirst_m 010000 . ..... 10001 010 ..... 1010111 @r2_vm
> vmsbf_m 010100 . ..... 00001 010 ..... 1010111 @r2_vm
> @@ -732,7 +732,7 @@ vrgather_vv 001100 . ..... ..... 000 ..... 1010111 @r_vm
> vrgatherei16_vv 001110 . ..... ..... 000 ..... 1010111 @r_vm
> vrgather_vx 001100 . ..... ..... 100 ..... 1010111 @r_vm
> vrgather_vi 001100 . ..... ..... 011 ..... 1010111 @r_vm
> -vcompress_vm 010111 - ..... ..... 010 ..... 1010111 @r
> +vcompress_vm 010111 1 ..... ..... 010 ..... 1010111 @r
> vmv1r_v 100111 1 ..... 00000 011 ..... 1010111 @r2rd
> vmv2r_v 100111 1 ..... 00001 011 ..... 1010111 @r2rd
> vmv4r_v 100111 1 ..... 00011 011 ..... 1010111 @r2rd
prev parent reply other threads:[~2025-04-05 9:21 UTC|newest]
Thread overview: 28+ messages / expand[flat|nested] mbox.gz Atom feed top
2025-03-29 14:44 [PATCH v2 00/12] Fix RVV encoding corner cases Max Chou
2025-03-29 14:44 ` [PATCH v2 01/12] target/riscv: rvv: Source vector registers cannot overlap mask register Max Chou
2025-04-05 8:58 ` Daniel Henrique Barboza
2025-03-29 14:44 ` [PATCH v2 02/12] target/riscv: rvv: Add CHECK arg to GEN_OPFVF_WIDEN_TRANS Max Chou
2025-04-05 8:58 ` Daniel Henrique Barboza
2025-03-29 14:44 ` [PATCH v2 03/12] target/riscv: Add vext_check_input_eew to check mismatched input EEWs encoding constraint Max Chou
2025-04-05 9:09 ` Daniel Henrique Barboza
2025-04-07 8:32 ` Max Chou
2025-03-29 14:44 ` [PATCH v2 04/12] target/riscv: rvv: Apply vext_check_input_eew to vector register gather instructions Max Chou
2025-04-05 9:14 ` Daniel Henrique Barboza
2025-04-07 8:34 ` Max Chou
2025-03-29 14:44 ` [PATCH v2 05/12] target/riscv: rvv: Apply vext_check_input_eew to OPIVI/OPIVX/OPFVF(vext_check_ss) instructions Max Chou
2025-04-05 9:17 ` Daniel Henrique Barboza
2025-04-07 8:35 ` Max Chou
2025-03-29 14:44 ` [PATCH v2 06/12] target/riscv: rvv: Apply vext_check_input_eew to OPIVV/OPFVV(vext_check_sss) instructions Max Chou
2025-04-05 9:18 ` Daniel Henrique Barboza
2025-03-29 14:44 ` [PATCH v2 07/12] target/riscv: rvv: Apply vext_check_input_eew to vector slide instructions(OPIVI/OPIVX) Max Chou
2025-04-05 9:18 ` Daniel Henrique Barboza
2025-03-29 14:44 ` [PATCH v2 08/12] target/riscv: rvv: Apply vext_check_input_eew to vector integer extension instructions(OPMVV) Max Chou
2025-04-05 9:18 ` Daniel Henrique Barboza
2025-03-29 14:44 ` [PATCH v2 09/12] target/riscv: rvv: Apply vext_check_input_eew to vector widen instructions(OPMVV/OPMVX/etc.) Max Chou
2025-04-05 9:20 ` Daniel Henrique Barboza
2025-03-29 14:44 ` [PATCH v2 10/12] target/riscv: rvv: Apply vext_check_input_eew to vector narrow instructions Max Chou
2025-04-05 9:20 ` Daniel Henrique Barboza
2025-03-29 14:44 ` [PATCH v2 11/12] target/riscv: rvv: Apply vext_check_input_eew to vector indexed load/store instructions Max Chou
2025-04-05 9:20 ` Daniel Henrique Barboza
2025-03-29 14:44 ` [PATCH v2 12/12] target/riscv: Fix the rvv reserved encoding of unmasked instructions Max Chou
2025-04-05 9:21 ` Daniel Henrique Barboza [this message]
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