From: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
To: Max Chou <max.chou@sifive.com>,
qemu-devel@nongnu.org, qemu-riscv@nongnu.org
Cc: Palmer Dabbelt <palmer@dabbelt.com>,
Alistair Francis <alistair.francis@wdc.com>,
Weiwei Li <liwei1518@gmail.com>,
Liu Zhiwei <zhiwei_liu@linux.alibaba.com>,
antonb@tenstorrent.com
Subject: Re: [PATCH v2 02/12] target/riscv: rvv: Add CHECK arg to GEN_OPFVF_WIDEN_TRANS
Date: Sat, 5 Apr 2025 05:58:49 -0300 [thread overview]
Message-ID: <ff0aea2c-82dc-4b56-beb5-59decd3f4e4a@ventanamicro.com> (raw)
In-Reply-To: <20250329144446.2619306-3-max.chou@sifive.com>
On 3/29/25 11:44 AM, Max Chou wrote:
> From: Anton Blanchard <antonb@tenstorrent.com>
>
> Signed-off-by: Anton Blanchard <antonb@tenstorrent.com>
> Signed-off-by: Max Chou <max.chou@sifive.com>
> ---
Reviewed-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
> target/riscv/insn_trans/trans_rvv.c.inc | 18 +++++++++---------
> 1 file changed, 9 insertions(+), 9 deletions(-)
>
> diff --git a/target/riscv/insn_trans/trans_rvv.c.inc b/target/riscv/insn_trans/trans_rvv.c.inc
> index 20b1cb127b4..e630f8661e1 100644
> --- a/target/riscv/insn_trans/trans_rvv.c.inc
> +++ b/target/riscv/insn_trans/trans_rvv.c.inc
> @@ -2403,10 +2403,10 @@ static bool opfvf_widen_check(DisasContext *s, arg_rmrr *a)
> }
>
> /* OPFVF with WIDEN */
> -#define GEN_OPFVF_WIDEN_TRANS(NAME) \
> +#define GEN_OPFVF_WIDEN_TRANS(NAME, CHECK) \
> static bool trans_##NAME(DisasContext *s, arg_rmrr *a) \
> { \
> - if (opfvf_widen_check(s, a)) { \
> + if (CHECK(s, a)) { \
> uint32_t data = 0; \
> static gen_helper_opfvf *const fns[2] = { \
> gen_helper_##NAME##_h, gen_helper_##NAME##_w, \
> @@ -2422,8 +2422,8 @@ static bool trans_##NAME(DisasContext *s, arg_rmrr *a) \
> return false; \
> }
>
> -GEN_OPFVF_WIDEN_TRANS(vfwadd_vf)
> -GEN_OPFVF_WIDEN_TRANS(vfwsub_vf)
> +GEN_OPFVF_WIDEN_TRANS(vfwadd_vf, opfvf_widen_check)
> +GEN_OPFVF_WIDEN_TRANS(vfwsub_vf, opfvf_widen_check)
>
> static bool opfwv_widen_check(DisasContext *s, arg_rmrr *a)
> {
> @@ -2505,7 +2505,7 @@ GEN_OPFVF_TRANS(vfrdiv_vf, opfvf_check)
>
> /* Vector Widening Floating-Point Multiply */
> GEN_OPFVV_WIDEN_TRANS(vfwmul_vv, opfvv_widen_check)
> -GEN_OPFVF_WIDEN_TRANS(vfwmul_vf)
> +GEN_OPFVF_WIDEN_TRANS(vfwmul_vf, opfvf_widen_check)
>
> /* Vector Single-Width Floating-Point Fused Multiply-Add Instructions */
> GEN_OPFVV_TRANS(vfmacc_vv, opfvv_check)
> @@ -2530,10 +2530,10 @@ GEN_OPFVV_WIDEN_TRANS(vfwmacc_vv, opfvv_widen_check)
> GEN_OPFVV_WIDEN_TRANS(vfwnmacc_vv, opfvv_widen_check)
> GEN_OPFVV_WIDEN_TRANS(vfwmsac_vv, opfvv_widen_check)
> GEN_OPFVV_WIDEN_TRANS(vfwnmsac_vv, opfvv_widen_check)
> -GEN_OPFVF_WIDEN_TRANS(vfwmacc_vf)
> -GEN_OPFVF_WIDEN_TRANS(vfwnmacc_vf)
> -GEN_OPFVF_WIDEN_TRANS(vfwmsac_vf)
> -GEN_OPFVF_WIDEN_TRANS(vfwnmsac_vf)
> +GEN_OPFVF_WIDEN_TRANS(vfwmacc_vf, opfvf_widen_check)
> +GEN_OPFVF_WIDEN_TRANS(vfwnmacc_vf, opfvf_widen_check)
> +GEN_OPFVF_WIDEN_TRANS(vfwmsac_vf, opfvf_widen_check)
> +GEN_OPFVF_WIDEN_TRANS(vfwnmsac_vf, opfvf_widen_check)
>
> /* Vector Floating-Point Square-Root Instruction */
>
next prev parent reply other threads:[~2025-04-05 8:59 UTC|newest]
Thread overview: 28+ messages / expand[flat|nested] mbox.gz Atom feed top
2025-03-29 14:44 [PATCH v2 00/12] Fix RVV encoding corner cases Max Chou
2025-03-29 14:44 ` [PATCH v2 01/12] target/riscv: rvv: Source vector registers cannot overlap mask register Max Chou
2025-04-05 8:58 ` Daniel Henrique Barboza
2025-03-29 14:44 ` [PATCH v2 02/12] target/riscv: rvv: Add CHECK arg to GEN_OPFVF_WIDEN_TRANS Max Chou
2025-04-05 8:58 ` Daniel Henrique Barboza [this message]
2025-03-29 14:44 ` [PATCH v2 03/12] target/riscv: Add vext_check_input_eew to check mismatched input EEWs encoding constraint Max Chou
2025-04-05 9:09 ` Daniel Henrique Barboza
2025-04-07 8:32 ` Max Chou
2025-03-29 14:44 ` [PATCH v2 04/12] target/riscv: rvv: Apply vext_check_input_eew to vector register gather instructions Max Chou
2025-04-05 9:14 ` Daniel Henrique Barboza
2025-04-07 8:34 ` Max Chou
2025-03-29 14:44 ` [PATCH v2 05/12] target/riscv: rvv: Apply vext_check_input_eew to OPIVI/OPIVX/OPFVF(vext_check_ss) instructions Max Chou
2025-04-05 9:17 ` Daniel Henrique Barboza
2025-04-07 8:35 ` Max Chou
2025-03-29 14:44 ` [PATCH v2 06/12] target/riscv: rvv: Apply vext_check_input_eew to OPIVV/OPFVV(vext_check_sss) instructions Max Chou
2025-04-05 9:18 ` Daniel Henrique Barboza
2025-03-29 14:44 ` [PATCH v2 07/12] target/riscv: rvv: Apply vext_check_input_eew to vector slide instructions(OPIVI/OPIVX) Max Chou
2025-04-05 9:18 ` Daniel Henrique Barboza
2025-03-29 14:44 ` [PATCH v2 08/12] target/riscv: rvv: Apply vext_check_input_eew to vector integer extension instructions(OPMVV) Max Chou
2025-04-05 9:18 ` Daniel Henrique Barboza
2025-03-29 14:44 ` [PATCH v2 09/12] target/riscv: rvv: Apply vext_check_input_eew to vector widen instructions(OPMVV/OPMVX/etc.) Max Chou
2025-04-05 9:20 ` Daniel Henrique Barboza
2025-03-29 14:44 ` [PATCH v2 10/12] target/riscv: rvv: Apply vext_check_input_eew to vector narrow instructions Max Chou
2025-04-05 9:20 ` Daniel Henrique Barboza
2025-03-29 14:44 ` [PATCH v2 11/12] target/riscv: rvv: Apply vext_check_input_eew to vector indexed load/store instructions Max Chou
2025-04-05 9:20 ` Daniel Henrique Barboza
2025-03-29 14:44 ` [PATCH v2 12/12] target/riscv: Fix the rvv reserved encoding of unmasked instructions Max Chou
2025-04-05 9:21 ` Daniel Henrique Barboza
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