Re: [PATCH v2 08/12] target/riscv: rvv: Apply vext_check_input_eew to vector integer extension instructions(OPMVV)

[Daniel Henrique Barboza <dbarboza@ventanamicro.com>]

On 3/29/25 11:44 AM, Max Chou wrote:
> Handle the overlap of source registers with different EEWs.
> 
> Co-authored-by: Anton Blanchard <antonb@tenstorrent.com>
> Co-authored-by: Max Chou <max.chou@sifive.com>
> Signed-off-by: Max Chou <max.chou@sifive.com>
> ---


With your co-authored-by tag removed:

Reviewed-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>

>   target/riscv/insn_trans/trans_rvv.c.inc | 4 +++-
>   1 file changed, 3 insertions(+), 1 deletion(-)
> 
> diff --git a/target/riscv/insn_trans/trans_rvv.c.inc b/target/riscv/insn_trans/trans_rvv.c.inc
> index f397ae46446..728912fc1f2 100644
> --- a/target/riscv/insn_trans/trans_rvv.c.inc
> +++ b/target/riscv/insn_trans/trans_rvv.c.inc
> @@ -3660,7 +3660,9 @@ static bool int_ext_check(DisasContext *s, arg_rmr *a, uint8_t div)
>           require_align(a->rd, s->lmul) &&
>           require_align(a->rs2, s->lmul - div) &&
>           require_vm(a->vm, a->rd) &&
> -        require_noover(a->rd, s->lmul, a->rs2, s->lmul - div);
> +        require_noover(a->rd, s->lmul, a->rs2, s->lmul - div) &&
> +        vext_check_input_eew(s, -1, 0, a->rs2, s->sew, a->vm);
> +
>       return ret;
>   }
>