[PATCH v2 0/4] drm/amd/pm: smu_v14_0_0: fix pp_dpm_* clock reporting on SMU v14.0.0/v14.0.1 APUs

[PATCH v2 0/4] drm/amd/pm: smu_v14_0_0: fix pp_dpm_* clock reporting on SMU v14.0.0/v14.0.1 APUs

[Priya Hosur]

This series fixes multiple pp_dpm_* sysfs clocks reporting N/A or missing
the * current-level marker on SMU v14.0.0/v14.0.1 APUs (GC 11.5.1).

Background
----------
On GC 11.5.1 APUs, amd-smi reports N/A for VCLK, DCLK, and DCEFCLK
clocks. Additionally, MCLK and FCLK show DPM levels but lack the *
marker indicating the current level.

Fix
---
1. Merge METRICS_AVERAGE_VCLK and METRICS_AVERAGE_DCLK into a single
   fall-through case mapping both to VclkFrequency (SmuMetrics_t has no
   DclkFrequency field; DCLK tracks VCLK on VCN).

2. Add IP_VERSION(11,5,1) to pp_dpm_vclk, pp_dpm_dclk, pp_dpm_vclk1
   and pp_dpm_dclk1 whitelists. The target APU has two VCN instances.

3. Add SMU_DCEFCLK to get_dpm_freq_by_index and get_dpm_level_count
   using DcfClocks[]/NumDcfClkLevelsEnabled. Add DCEFCLK case in
   emit_clk_levels.

4. Add closest-match fallback in emit_clk_levels: on exact match, set
   closest_idx and break immediately; otherwise track the DPM level
   with the smallest absolute frequency difference, with early exit
   when the diff starts increasing. Reverse DPM index for SMU_MCLK
   since MemPstateTable stores levels high-to-low.

Validation
----------
Tested on GC 11.5.1, SMU 14.0.1 APU. All pp_dpm_* clocks now report
correct DPM levels with * markers via both sysfs and amd-smi.

Changes since v1:
- Patch 1: Dropped VCLK1/DCLK1 metric handlers; let them fall through
  to default UINT_MAX (N/A) as suggested by Lijo.
- Patch 4: On exact match, set closest_idx and break instead of
  continuing the loop. Added early exit when diff starts increasing
  (monotonic DPM levels), as suggested by Lijo.

Priya Hosur (4):
  drm/amd/pm: smu_v14_0_0: add DCLK metric handler via VCLK fall-through
  drm/amd/pm: add IP_VERSION(11,5,1) to vclk/dclk DPM sysfs whitelists
  drm/amd/pm: smu_v14_0_0: add SMU_DCEFCLK support in DPM frequency
    queries
  drm/amd/pm: smu_v14_0_0: add closest-match fallback for DPM level
    marking

 drivers/gpu/drm/amd/pm/amdgpu_pm.c            |  8 +-
 .../drm/amd/pm/swsmu/smu14/smu_v14_0_0_ppt.c  | 82 +++++++++++++++++--
 2 files changed, 80 insertions(+), 10 deletions(-)

-- 
2.43.0

[PATCH v2 1/4] drm/amd/pm: smu_v14_0_0: add DCLK metric handler via VCLK fall-through

[Priya Hosur]

Merge METRICS_AVERAGE_VCLK and METRICS_AVERAGE_DCLK into a single
fall-through case mapping both to VclkFrequency, since SmuMetrics_t
has no DclkFrequency field and DCLK tracks VCLK on VCN.

Signed-off-by: Priya Hosur <Priya.Hosur@amd.com>
---
 drivers/gpu/drm/amd/pm/swsmu/smu14/smu_v14_0_0_ppt.c | 5 ++---
 1 file changed, 2 insertions(+), 3 deletions(-)

diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu14/smu_v14_0_0_ppt.c b/drivers/gpu/drm/amd/pm/swsmu/smu14/smu_v14_0_0_ppt.c
index 2fe006de927a..79e0e2fca602 100644
--- a/drivers/gpu/drm/amd/pm/swsmu/smu14/smu_v14_0_0_ppt.c
+++ b/drivers/gpu/drm/amd/pm/swsmu/smu14/smu_v14_0_0_ppt.c
@@ -281,10 +281,9 @@ static int smu_v14_0_0_get_smu_metrics_data(struct smu_context *smu,
 		*value = metrics->SocclkFrequency;
 		break;
 	case METRICS_AVERAGE_VCLK:
-		*value = metrics->VclkFrequency;
-		break;
 	case METRICS_AVERAGE_DCLK:
-		*value = 0;
+		/* No DclkFrequency in SmuMetrics_t; DCLK tracks VCLK on VCN */
+		*value = metrics->VclkFrequency;
 		break;
 	case METRICS_AVERAGE_UCLK:
 		*value = metrics->MemclkFrequency;
-- 
2.43.0

Re: [PATCH v2 1/4] drm/amd/pm: smu_v14_0_0: add DCLK metric handler via VCLK fall-through

[Lazar, Lijo]

On 10-Jun-26 11:53 PM, Priya Hosur wrote:
> Merge METRICS_AVERAGE_VCLK and METRICS_AVERAGE_DCLK into a single
> fall-through case mapping both to VclkFrequency, since SmuMetrics_t
> has no DclkFrequency field and DCLK tracks VCLK on VCN.
> 
> Signed-off-by: Priya Hosur <Priya.Hosur@amd.com>
> ---
>   drivers/gpu/drm/amd/pm/swsmu/smu14/smu_v14_0_0_ppt.c | 5 ++---
>   1 file changed, 2 insertions(+), 3 deletions(-)
> 
> diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu14/smu_v14_0_0_ppt.c b/drivers/gpu/drm/amd/pm/swsmu/smu14/smu_v14_0_0_ppt.c
> index 2fe006de927a..79e0e2fca602 100644
> --- a/drivers/gpu/drm/amd/pm/swsmu/smu14/smu_v14_0_0_ppt.c
> +++ b/drivers/gpu/drm/amd/pm/swsmu/smu14/smu_v14_0_0_ppt.c
> @@ -281,10 +281,9 @@ static int smu_v14_0_0_get_smu_metrics_data(struct smu_context *smu,
>   		*value = metrics->SocclkFrequency;
>   		break;
>   	case METRICS_AVERAGE_VCLK:
> -		*value = metrics->VclkFrequency;
> -		break;
>   	case METRICS_AVERAGE_DCLK:
> -		*value = 0;
> +		/* No DclkFrequency in SmuMetrics_t; DCLK tracks VCLK on VCN */
> +		*value = metrics->VclkFrequency;

The code refers to separate clock tables for DCLK and VCLK. As per this 
they are identical, but still fetched separately.

Thanks,
Lijo

>   		break;
>   	case METRICS_AVERAGE_UCLK:
>   		*value = metrics->MemclkFrequency;

[PATCH v2 2/4] drm/amd/pm: add IP_VERSION(11, 5, 1) to vclk/dclk DPM sysfs whitelists

[Priya Hosur]

Add IP_VERSION(11,5,1) to pp_dpm_vclk and pp_dpm_dclk visibility
whitelists so these sysfs entries are exposed on Strix Halo (GC
11.5.1). Add IP_VERSION(11,5,1) to pp_dpm_vclk1 and pp_dpm_dclk1
whitelists with the existing num_vcn_inst >= 2 guard since Strix
Halo has two VCN instances.

Without this, amd-smi reports N/A for VCLK0, VCLK1, DCLK0 and
DCLK1 clocks.

Signed-off-by: Priya Hosur <Priya.Hosur@amd.com>
---
 drivers/gpu/drm/amd/pm/amdgpu_pm.c | 8 ++++++--
 1 file changed, 6 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/amd/pm/amdgpu_pm.c b/drivers/gpu/drm/amd/pm/amdgpu_pm.c
index dfebe67c164d..305852f5b153 100644
--- a/drivers/gpu/drm/amd/pm/amdgpu_pm.c
+++ b/drivers/gpu/drm/amd/pm/amdgpu_pm.c
@@ -2027,6 +2027,7 @@ static int pp_dpm_clk_default_attr_update(struct amdgpu_device *adev, struct amd
 		      gc_ver == IP_VERSION(11, 0, 1) ||
 		      gc_ver == IP_VERSION(11, 0, 4) ||
 		      gc_ver == IP_VERSION(11, 5, 0) ||
+		      gc_ver == IP_VERSION(11, 5, 1) ||
 		      gc_ver == IP_VERSION(11, 0, 2) ||
 		      gc_ver == IP_VERSION(11, 0, 3) ||
 		      amdgpu_is_multi_aid(adev)))
@@ -2035,7 +2036,8 @@ static int pp_dpm_clk_default_attr_update(struct amdgpu_device *adev, struct amd
 		if (!((gc_ver == IP_VERSION(10, 3, 1) ||
 		       gc_ver == IP_VERSION(10, 3, 0) ||
 		       gc_ver == IP_VERSION(11, 0, 2) ||
-		       gc_ver == IP_VERSION(11, 0, 3)) && adev->vcn.num_vcn_inst >= 2))
+		       gc_ver == IP_VERSION(11, 0, 3) ||
+		       gc_ver == IP_VERSION(11, 5, 1)) && adev->vcn.num_vcn_inst >= 2))
 			*states = ATTR_STATE_UNSUPPORTED;
 	} else if (DEVICE_ATTR_IS(pp_dpm_dclk)) {
 		if (!(gc_ver == IP_VERSION(10, 3, 1) ||
@@ -2048,6 +2050,7 @@ static int pp_dpm_clk_default_attr_update(struct amdgpu_device *adev, struct amd
 		      gc_ver == IP_VERSION(11, 0, 1) ||
 		      gc_ver == IP_VERSION(11, 0, 4) ||
 		      gc_ver == IP_VERSION(11, 5, 0) ||
+		      gc_ver == IP_VERSION(11, 5, 1) ||
 		      gc_ver == IP_VERSION(11, 0, 2) ||
 		      gc_ver == IP_VERSION(11, 0, 3) ||
 		      amdgpu_is_multi_aid(adev)))
@@ -2056,7 +2059,8 @@ static int pp_dpm_clk_default_attr_update(struct amdgpu_device *adev, struct amd
 		if (!((gc_ver == IP_VERSION(10, 3, 1) ||
 		       gc_ver == IP_VERSION(10, 3, 0) ||
 		       gc_ver == IP_VERSION(11, 0, 2) ||
-		       gc_ver == IP_VERSION(11, 0, 3)) && adev->vcn.num_vcn_inst >= 2))
+		       gc_ver == IP_VERSION(11, 0, 3) ||
+		       gc_ver == IP_VERSION(11, 5, 1)) && adev->vcn.num_vcn_inst >= 2))
 			*states = ATTR_STATE_UNSUPPORTED;
 	} else if (DEVICE_ATTR_IS(pp_dpm_pcie)) {
 		if (amdgpu_is_multi_aid(adev))
-- 
2.43.0

[PATCH v2 3/4] drm/amd/pm: smu_v14_0_0: add SMU_DCEFCLK support in DPM frequency queries

[Priya Hosur]

Add SMU_DCEFCLK case to smu_v14_0_1_get_dpm_freq_by_index and
smu_v14_0_0_get_dpm_freq_by_index using DcfClocks[] with
NumDcfClkLevelsEnabled bounds check. Add matching case in both
get_dpm_level_count functions.

Add SMU_DCEFCLK case in emit_clk_levels to list DCEF DPM levels.
No * marker is emitted since SmuMetrics_t has no DcfclkFrequency
field (same firmware limitation as Phoenix).

Without this, pp_dpm_dcefclk reports N/A on Strix Halo.

Signed-off-by: Priya Hosur <Priya.Hosur@amd.com>
---
 .../drm/amd/pm/swsmu/smu14/smu_v14_0_0_ppt.c  | 28 +++++++++++++++++++
 1 file changed, 28 insertions(+)

diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu14/smu_v14_0_0_ppt.c b/drivers/gpu/drm/amd/pm/swsmu/smu14/smu_v14_0_0_ppt.c
index 79e0e2fca602..1be8d1a8da19 100644
--- a/drivers/gpu/drm/amd/pm/swsmu/smu14/smu_v14_0_0_ppt.c
+++ b/drivers/gpu/drm/amd/pm/swsmu/smu14/smu_v14_0_0_ppt.c
@@ -682,6 +682,11 @@ static int smu_v14_0_1_get_dpm_freq_by_index(struct smu_context *smu,
 			return -EINVAL;
 		*freq = clk_table->FclkClocks_Freq[dpm_level];
 		break;
+	case SMU_DCEFCLK:
+		if (dpm_level >= clk_table->NumDcfClkLevelsEnabled)
+			return -EINVAL;
+		*freq = clk_table->DcfClocks[dpm_level];
+		break;
 	default:
 		return -EINVAL;
 	}
@@ -726,6 +731,11 @@ static int smu_v14_0_0_get_dpm_freq_by_index(struct smu_context *smu,
 			return -EINVAL;
 		*freq = clk_table->FclkClocks_Freq[dpm_level];
 		break;
+	case SMU_DCEFCLK:
+		if (dpm_level >= clk_table->NumDcfClkLevelsEnabled)
+			return -EINVAL;
+		*freq = clk_table->DcfClocks[dpm_level];
+		break;
 	default:
 		return -EINVAL;
 	}
@@ -1089,6 +1099,9 @@ static int smu_v14_0_1_get_dpm_level_count(struct smu_context *smu,
 	case SMU_FCLK:
 		*count = clk_table->NumFclkLevelsEnabled;
 		break;
+	case SMU_DCEFCLK:
+		*count = clk_table->NumDcfClkLevelsEnabled;
+		break;
 	default:
 		break;
 	}
@@ -1118,6 +1131,9 @@ static int smu_v14_0_0_get_dpm_level_count(struct smu_context *smu,
 	case SMU_FCLK:
 		*count = clk_table->NumFclkLevelsEnabled;
 		break;
+	case SMU_DCEFCLK:
+		*count = clk_table->NumDcfClkLevelsEnabled;
+		break;
 	default:
 		break;
 	}
@@ -1184,6 +1200,18 @@ static int smu_v14_0_0_emit_clk_levels(struct smu_context *smu,
 					      cur_value == value ? "*" : "");
 		}
 		break;
+	case SMU_DCEFCLK:
+		ret = smu_v14_0_common_get_dpm_level_count(smu, clk_type, &count);
+		if (ret)
+			return ret;
+
+		for (i = 0; i < count; i++) {
+			ret = smu_v14_0_common_get_dpm_freq_by_index(smu, clk_type, i, &value);
+			if (ret)
+				return ret;
+			size += sysfs_emit_at(buf, size, "%d: %uMhz\n", i, value);
+		}
+		break;
 	case SMU_GFXCLK:
 	case SMU_SCLK:
 		ret = smu_v14_0_0_get_current_clk_freq(smu, clk_type, &cur_value);
-- 
2.43.0

[PATCH v2 4/4] drm/amd/pm: smu_v14_0_0: add closest-match fallback for DPM level marking

[Priya Hosur]

Replace the simple exact-match loop in emit_clk_levels with a
two-pass approach: the first pass checks whether the current
frequency matches any DPM level exactly and also tracks the closest
level by absolute frequency difference. The second pass emits the
levels, marking the exact match if found, otherwise the closest
level.

The SMU reports time-filtered average frequencies that often do not
match any DPM table entry exactly. Without this fallback, MCLK,
FCLK and other clocks show DPM levels but never display the *
marker, breaking userspace tools that rely on it to identify the
active frequency.

Also uses reverse DPM index for SMU_MCLK since MemPstateTable
stores levels high-to-low.

Signed-off-by: Priya Hosur <Priya.Hosur@amd.com>
---
 .../drm/amd/pm/swsmu/smu14/smu_v14_0_0_ppt.c  | 53 ++++++++++++++++---
 1 file changed, 46 insertions(+), 7 deletions(-)

diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu14/smu_v14_0_0_ppt.c b/drivers/gpu/drm/amd/pm/swsmu/smu14/smu_v14_0_0_ppt.c
index 1be8d1a8da19..c01c71acbe3f 100644
--- a/drivers/gpu/drm/amd/pm/swsmu/smu14/smu_v14_0_0_ppt.c
+++ b/drivers/gpu/drm/amd/pm/swsmu/smu14/smu_v14_0_0_ppt.c
@@ -1190,14 +1190,53 @@ static int smu_v14_0_0_emit_clk_levels(struct smu_context *smu,
 		if (ret)
 			return ret;
 
-		for (i = 0; i < count; i++) {
-			idx = (clk_type == SMU_MCLK) ? (count - i - 1) : i;
-			ret = smu_v14_0_common_get_dpm_freq_by_index(smu, clk_type, idx, &value);
-			if (ret)
-				return ret;
+		/*
+		 * Try exact match first. If the SMU reports a time-averaged
+		 * frequency that doesn't match any DPM level exactly, fall
+		 * back to marking the closest DPM level.
+		 */
+		{
+			int closest_idx = 0;
+			uint32_t closest_diff = U32_MAX;
+			uint32_t diff;
+			bool exact_match = false;
+
+			for (i = 0; i < count; i++) {
+				idx = (clk_type == SMU_MCLK) ? (count - i - 1) : i;
+				ret = smu_v14_0_common_get_dpm_freq_by_index(smu, clk_type, idx, &value);
+				if (ret)
+					return ret;
+
+				if (cur_value == value) {
+					closest_idx = i;
+					exact_match = true;
+					break;
+				}
+
+				diff = abs((int)cur_value - (int)value);
+				if (diff < closest_diff) {
+					closest_diff = diff;
+					closest_idx = i;
+				} else if (diff > closest_diff) {
+					break;
+				}
+			}
 
-			size += sysfs_emit_at(buf, size, "%d: %uMhz %s\n", i, value,
-					      cur_value == value ? "*" : "");
+			for (i = 0; i < count; i++) {
+				idx = (clk_type == SMU_MCLK) ? (count - i - 1) : i;
+				ret = smu_v14_0_common_get_dpm_freq_by_index(smu, clk_type, idx, &value);
+				if (ret)
+					return ret;
+
+				if (exact_match)
+					size += sysfs_emit_at(buf, size, "%d: %uMhz %s\n",
+							      i, value,
+							      cur_value == value ? "*" : "");
+				else
+					size += sysfs_emit_at(buf, size, "%d: %uMhz %s\n",
+							      i, value,
+							      i == closest_idx ? "*" : "");
+			}
 		}
 		break;
 	case SMU_DCEFCLK:
-- 
2.43.0

Re: [PATCH v2 4/4] drm/amd/pm: smu_v14_0_0: add closest-match fallback for DPM level marking

[Lazar, Lijo]

On 10-Jun-26 11:53 PM, Priya Hosur wrote:
> Replace the simple exact-match loop in emit_clk_levels with a
> two-pass approach: the first pass checks whether the current
> frequency matches any DPM level exactly and also tracks the closest
> level by absolute frequency difference. The second pass emits the
> levels, marking the exact match if found, otherwise the closest
> level.
> 
> The SMU reports time-filtered average frequencies that often do not
> match any DPM table entry exactly. Without this fallback, MCLK,
> FCLK and other clocks show DPM levels but never display the *
> marker, breaking userspace tools that rely on it to identify the
> active frequency.
> 
> Also uses reverse DPM index for SMU_MCLK since MemPstateTable
> stores levels high-to-low.
> 
> Signed-off-by: Priya Hosur <Priya.Hosur@amd.com>
> ---
>   .../drm/amd/pm/swsmu/smu14/smu_v14_0_0_ppt.c  | 53 ++++++++++++++++---
>   1 file changed, 46 insertions(+), 7 deletions(-)
> 
> diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu14/smu_v14_0_0_ppt.c b/drivers/gpu/drm/amd/pm/swsmu/smu14/smu_v14_0_0_ppt.c
> index 1be8d1a8da19..c01c71acbe3f 100644
> --- a/drivers/gpu/drm/amd/pm/swsmu/smu14/smu_v14_0_0_ppt.c
> +++ b/drivers/gpu/drm/amd/pm/swsmu/smu14/smu_v14_0_0_ppt.c
> @@ -1190,14 +1190,53 @@ static int smu_v14_0_0_emit_clk_levels(struct smu_context *smu,
>   		if (ret)
>   			return ret;
>   
> -		for (i = 0; i < count; i++) {
> -			idx = (clk_type == SMU_MCLK) ? (count - i - 1) : i;
> -			ret = smu_v14_0_common_get_dpm_freq_by_index(smu, clk_type, idx, &value);
> -			if (ret)
> -				return ret;
> +		/*
> +		 * Try exact match first. If the SMU reports a time-averaged
> +		 * frequency that doesn't match any DPM level exactly, fall
> +		 * back to marking the closest DPM level.
> +		 */
> +		{
> +			int closest_idx = 0;
> +			uint32_t closest_diff = U32_MAX;
> +			uint32_t diff;
> +			bool exact_match = false;
> +
> +			for (i = 0; i < count; i++) {
> +				idx = (clk_type == SMU_MCLK) ? (count - i - 1) : i;
> +				ret = smu_v14_0_common_get_dpm_freq_by_index(smu, clk_type, idx, &value);
> +				if (ret)
> +					return ret;
> +
> +				if (cur_value == value) {
> +					closest_idx = i;
> +					exact_match = true;
> +					break;
> +				}
> +
> +				diff = abs((int)cur_value - (int)value);
> +				if (diff < closest_diff) {
> +					closest_diff = diff;
> +					closest_idx = i;
> +				} else if (diff > closest_diff) {
> +					break;
> +				}
> +			}
>   
> -			size += sysfs_emit_at(buf, size, "%d: %uMhz %s\n", i, value,
> -					      cur_value == value ? "*" : "");
> +			for (i = 0; i < count; i++) {
> +				idx = (clk_type == SMU_MCLK) ? (count - i - 1) : i;
> +				ret = smu_v14_0_common_get_dpm_freq_by_index(smu, clk_type, idx, &value);
> +				if (ret)
> +					return ret;
> +
> +				if (exact_match)

exact_match is redundant now. It only needs closest_idx check.

Thanks,
Lijo

> +					size += sysfs_emit_at(buf, size, "%d: %uMhz %s\n",
> +							      i, value,
> +							      cur_value == value ? "*" : "");
> +				else
> +					size += sysfs_emit_at(buf, size, "%d: %uMhz %s\n",
> +							      i, value,
> +							      i == closest_idx ? "*" : "");
> +			}
>   		}
>   		break;
>   	case SMU_DCEFCLK: