From: "Siegmund, Jan" <jan.siegmund0@hm.edu>
To: "u-boot@lists.denx.de" <u-boot@lists.denx.de>
Cc: "linux-fpga@vger.kernel.org" <linux-fpga@vger.kernel.org>
Subject: WG: Linux hang
Date: Thu, 7 Dec 2017 11:00:45 +0000 [thread overview]
Message-ID: <71bcb4759caa437dba81be27fc611239@hm.edu> (raw)
In-Reply-To: <4d6911ffa53349b0881ff4d4845bc101@hm.edu>
Hi all,
does anybody have an idea for the following problem?
* FPGA is programmed using an overlay
* FPGA writes to SDRAM via the FPGA2SDRAM-bridge
* Linux hangs and the watchdog resets the board (the FPGA stays programmed)
* After the reset and boot, the FPGA is reprogrammed using the same overlay
* Now, the FPGA can write to the SDRAM without a problem
The environment:
*Board:�� DE0-NANO-SoC
*U-Boot: 2017.11
*Kernel:� 4.14.0-rc7 (review-v4.14-rc7-non-dt-support-v5.1 branch)
The overlay:
/dts-v1/;
/plugin/;
/ {
������� fragment@0 {
��������������� target-path = "/soc/base_fpga_region";
��������������� #address-cells = <1>;
��������������� #size-cells = <1>;
��������������� __overlay__ {
����������������������� #address-cells = <1>;
����������������������� #size-cells = <1>;
����������������������� fpga-bridges = <&fpga_bridge0 &fpga_bridge1>;
����������������������� firmware-name = "foo_base.rbf";
����������������������� fpga-bridge@ffc25080 {
������������������������������� compatible = "altr,socfpga-fpga2sdram-bridge";
������������������������������� reg = <0xffc25080 0x4>;
������������������������������� bridge-enable = <1>;
����������������������� };
����������������������� foo@ff200000 {
������������������������������� compatible= "altr,bar";
������������������������������� interrupt-parent = <&intc>;
������������������������������� interrupts = <0 40 4>;
����������������������� };
��������������� };
������� };
};
Thanks
WARNING: multiple messages have this Message-ID (diff)
From: Siegmund, Jan <jan.siegmund0@hm.edu>
To: u-boot@lists.denx.de
Subject: [U-Boot] WG: Linux hang
Date: Thu, 7 Dec 2017 11:00:45 +0000 [thread overview]
Message-ID: <71bcb4759caa437dba81be27fc611239@hm.edu> (raw)
In-Reply-To: <4d6911ffa53349b0881ff4d4845bc101@hm.edu>
Hi all,
does anybody have an idea for the following problem?
* FPGA is programmed using an overlay
* FPGA writes to SDRAM via the FPGA2SDRAM-bridge
* Linux hangs and the watchdog resets the board (the FPGA stays programmed)
* After the reset and boot, the FPGA is reprogrammed using the same overlay
* Now, the FPGA can write to the SDRAM without a problem
The environment:
*Board: DE0-NANO-SoC
*U-Boot: 2017.11
*Kernel: 4.14.0-rc7 (review-v4.14-rc7-non-dt-support-v5.1 branch)
The overlay:
/dts-v1/;
/plugin/;
/ {
fragment at 0 {
target-path = "/soc/base_fpga_region";
#address-cells = <1>;
#size-cells = <1>;
__overlay__ {
#address-cells = <1>;
#size-cells = <1>;
fpga-bridges = <&fpga_bridge0 &fpga_bridge1>;
firmware-name = "foo_base.rbf";
fpga-bridge at ffc25080 {
compatible = "altr,socfpga-fpga2sdram-bridge";
reg = <0xffc25080 0x4>;
bridge-enable = <1>;
};
foo at ff200000 {
compatible= "altr,bar";
interrupt-parent = <&intc>;
interrupts = <0 40 4>;
};
};
};
};
Thanks
next prev parent reply other threads:[~2017-12-07 11:00 UTC|newest]
Thread overview: 14+ messages / expand[flat|nested] mbox.gz Atom feed top
2017-12-06 17:02 Linux hang Siegmund, Jan
2017-12-07 11:00 ` Siegmund, Jan [this message]
2017-12-07 11:00 ` [U-Boot] WG: " Siegmund, Jan
2017-12-07 14:01 ` AW: " Goldschmidt Simon
2017-12-07 14:01 ` [U-Boot] " Goldschmidt Simon
2017-12-07 19:58 ` Jan Siegmund
2017-12-07 19:58 ` Jan Siegmund
2017-12-07 19:19 ` Alan Tull
2017-12-07 19:19 ` [U-Boot] " Alan Tull
2017-12-07 20:14 ` Jan Siegmund
2017-12-07 20:14 ` [U-Boot] " Jan Siegmund
2017-12-08 13:52 ` Anatolij Gustschin
2017-12-11 16:23 ` Jan Siegmund
2017-12-11 16:23 ` [U-Boot] " Jan Siegmund
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