From: Yi Liu <yi.l.liu@intel.com>
To: Zhenzhong Duan <zhenzhong.duan@intel.com>, <qemu-devel@nongnu.org>
Cc: <alex@shazbot.org>, <clg@redhat.com>, <eric.auger@redhat.com>,
<mst@redhat.com>, <jasowang@redhat.com>, <jgg@nvidia.com>,
<nicolinc@nvidia.com>, <skolothumtho@nvidia.com>,
<joao.m.martins@oracle.com>, <clement.mathieu--drif@bull.com>,
<kevin.tian@intel.com>, <xudong.hao@intel.com>
Subject: Re: [PATCH v5 15/15] intel_iommu: Expose flag VIOMMU_FLAG_PASID_SUPPORTED and VIOMMU_FLAG_WANT_PASID_ATTACH
Date: Thu, 14 May 2026 19:25:48 +0800 [thread overview]
Message-ID: <72d631cf-bc98-414c-826b-a39f947d0efc@intel.com> (raw)
In-Reply-To: <20260509040819.1044702-16-zhenzhong.duan@intel.com>
On 5/9/26 12:08, Zhenzhong Duan wrote:
> VFIO device will check flag VIOMMU_FLAG_PASID_SUPPORTED and expose PASID
> capability, also check VIOMMU_FLAG_WANT_PASID_ATTACH to enable pasid
> attachment, without those guest could not enable PASID of this device even
> if vIOMMU's pasid is configured.
>
> We don't expose the two flags when first stage is not configured as we
nit: s/first stage/fist stage translation/
> don't support shadow page table on a PASID.
>
> This is the final knob to enable PASID.
>
> Signed-off-by: Zhenzhong Duan <zhenzhong.duan@intel.com>
> Tested-by: Xudong Hao <xudong.hao@intel.com>
> ---
> hw/i386/intel_iommu.c | 5 +++++
> 1 file changed, 5 insertions(+)
>
> diff --git a/hw/i386/intel_iommu.c b/hw/i386/intel_iommu.c
> index 6067069e02..70546e91d4 100644
> --- a/hw/i386/intel_iommu.c
> +++ b/hw/i386/intel_iommu.c
> @@ -4788,6 +4788,11 @@ static uint64_t vtd_get_viommu_flags(void *opaque)
> if (s->fsts) {
> flags = VIOMMU_FLAG_WANT_NESTING_PARENT |
> VIOMMU_FLAG_WANT_NESTING_DIRTY_TRACKING;
> +
> + if (s->pasid) {
> + flags |= VIOMMU_FLAG_PASID_SUPPORTED |
> + VIOMMU_FLAG_WANT_PASID_ATTACH;
> + }
> }
>
> return flags;
Reviewed-by: Yi Liu <yi.l.liu@intel.com>
prev parent reply other threads:[~2026-05-14 11:18 UTC|newest]
Thread overview: 24+ messages / expand[flat|nested] mbox.gz Atom feed top
2026-05-09 4:07 [PATCH v5 00/15] intel_iommu: Enable PASID support for passthrough device Zhenzhong Duan
2026-05-09 4:07 ` [PATCH v5 01/15] vfio/iommufd: Extend attach/detach_hwpt callback implementations with pasid Zhenzhong Duan
2026-05-09 4:07 ` [PATCH v5 02/15] iommufd: Extend attach/detach_hwpt callbacks to support pasid Zhenzhong Duan
2026-05-09 4:07 ` [PATCH v5 03/15] vfio/iommufd: Create nesting parent hwpt with IOMMU_HWPT_ALLOC_PASID flag Zhenzhong Duan
2026-05-09 4:07 ` [PATCH v5 04/15] intel_iommu: Create the nested " Zhenzhong Duan
2026-05-09 4:07 ` [PATCH v5 05/15] intel_iommu: Rename pasid property to "pasid-bits" and define it as type uint8 Zhenzhong Duan
2026-05-14 11:30 ` Yi Liu
2026-05-09 4:07 ` [PATCH v5 06/15] intel_iommu: Export some functions Zhenzhong Duan
2026-05-09 4:08 ` [PATCH v5 07/15] intel_iommu: Use IOMMU_NO_PASID and delete PASID_0 Zhenzhong Duan
2026-05-14 11:24 ` Yi Liu
2026-05-09 4:08 ` [PATCH v5 08/15] intel_iommu: Refactor PASID processing to use IOMMU_NO_PASID internally Zhenzhong Duan
2026-05-14 11:25 ` Yi Liu
2026-05-09 4:08 ` [PATCH v5 09/15] intel_iommu_accel: Handle PASID entry addition for pc_inv_dsc request Zhenzhong Duan
2026-05-14 11:25 ` Yi Liu
2026-05-09 4:08 ` [PATCH v5 10/15] intel_iommu_accel: Handle PASID entry removal " Zhenzhong Duan
2026-05-14 11:25 ` Yi Liu
2026-05-09 4:08 ` [PATCH v5 11/15] intel_iommu_accel: Bypass PASID entry addition for just deleted entry Zhenzhong Duan
2026-05-14 11:28 ` Yi Liu
2026-05-09 4:08 ` [PATCH v5 12/15] intel_iommu_accel: Handle PASID entry removal for system reset Zhenzhong Duan
2026-05-09 4:08 ` [PATCH v5 13/15] intel_iommu_accel: Switch to VTDAccelPASIDCacheEntry for PASID bind/unbind and PIOTLB invalidation Zhenzhong Duan
2026-05-09 4:08 ` [PATCH v5 14/15] intel_iommu_accel: Add pasid bits size check Zhenzhong Duan
2026-05-14 11:25 ` Yi Liu
2026-05-09 4:08 ` [PATCH v5 15/15] intel_iommu: Expose flag VIOMMU_FLAG_PASID_SUPPORTED and VIOMMU_FLAG_WANT_PASID_ATTACH Zhenzhong Duan
2026-05-14 11:25 ` Yi Liu [this message]
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