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From: Yi Liu <yi.l.liu@intel.com>
To: Zhenzhong Duan <zhenzhong.duan@intel.com>, <qemu-devel@nongnu.org>
Cc: <alex@shazbot.org>, <clg@redhat.com>, <eric.auger@redhat.com>,
	<mst@redhat.com>, <jasowang@redhat.com>, <jgg@nvidia.com>,
	<nicolinc@nvidia.com>, <skolothumtho@nvidia.com>,
	<joao.m.martins@oracle.com>, <clement.mathieu--drif@bull.com>,
	<kevin.tian@intel.com>, <xudong.hao@intel.com>
Subject: Re: [PATCH v5 07/15] intel_iommu: Use IOMMU_NO_PASID and delete PASID_0
Date: Thu, 14 May 2026 19:24:58 +0800	[thread overview]
Message-ID: <dd52f20e-16db-4f7d-a8f0-12672953ccf2@intel.com> (raw)
In-Reply-To: <20260509040819.1044702-8-zhenzhong.duan@intel.com>

On 5/9/26 12:08, Zhenzhong Duan wrote:
> In previous patch we introduced a global macro IOMMU_NO_PASID(0) for
> the RID attachment, this makes the local macro PASID_0 redundant.
> Delete it and use IOMMU_NO_PASID instead.
> 
> No functional changes intended.
> 
> Suggested-by: Yi Liu <yi.l.liu@intel.com>
> Signed-off-by: Zhenzhong Duan <zhenzhong.duan@intel.com>
> Tested-by: Xudong Hao <xudong.hao@intel.com>
> ---
>   hw/i386/intel_iommu_internal.h |  1 -
>   hw/i386/intel_iommu.c          | 22 +++++++++++-----------
>   hw/i386/intel_iommu_accel.c    |  2 +-
>   3 files changed, 12 insertions(+), 13 deletions(-)

Reviewed-by: Yi Liu <yi.l.liu@intel.com>

> diff --git a/hw/i386/intel_iommu_internal.h b/hw/i386/intel_iommu_internal.h
> index c7e107fe87..0141316f83 100644
> --- a/hw/i386/intel_iommu_internal.h
> +++ b/hw/i386/intel_iommu_internal.h
> @@ -615,7 +615,6 @@ typedef struct VTDRootEntry VTDRootEntry;
>   #define VTD_CTX_ENTRY_LEGACY_SIZE     16
>   #define VTD_CTX_ENTRY_SCALABLE_SIZE   32
>   
> -#define PASID_0                             0
>   #define VTD_SM_CONTEXT_ENTRY_RSVD_VAL0(aw)  (0x1e0ULL | ~VTD_HAW_MASK(aw))
>   #define VTD_SM_CONTEXT_ENTRY_RSVD_VAL1      0xffffffffffe00000ULL
>   #define VTD_SM_CONTEXT_ENTRY_PRE            0x10ULL
> diff --git a/hw/i386/intel_iommu.c b/hw/i386/intel_iommu.c
> index 36af13cee3..5e5dcdc274 100644
> --- a/hw/i386/intel_iommu.c
> +++ b/hw/i386/intel_iommu.c
> @@ -941,7 +941,7 @@ int vtd_ce_get_pasid_entry(IntelIOMMUState *s, VTDContextEntry *ce,
>       dma_addr_t pasid_dir_base;
>   
>       if (pasid == PCI_NO_PASID) {
> -        pasid = PASID_0;
> +        pasid = IOMMU_NO_PASID;
>       }
>       pasid_dir_base = VTD_CE_GET_PASID_DIR_TABLE(ce);
>       return vtd_get_pe_from_pasid_table(s, pasid_dir_base, pasid, pe);
> @@ -958,7 +958,7 @@ static int vtd_ce_get_pasid_fpd(IntelIOMMUState *s,
>       VTDPASIDEntry pe;
>   
>       if (pasid == PCI_NO_PASID) {
> -        pasid = PASID_0;
> +        pasid = IOMMU_NO_PASID;
>       }
>       pasid_dir_base = VTD_CE_GET_PASID_DIR_TABLE(ce);
>   
> @@ -1501,9 +1501,9 @@ static int vtd_ce_pasid_0_check(IntelIOMMUState *s, VTDContextEntry *ce)
>   
>       /*
>        * Make sure in Scalable Mode, a present context entry
> -     * has valid pasid entry setting at PASID_0.
> +     * has valid pasid entry setting at IOMMU_NO_PASID.
>        */
> -    return vtd_ce_get_pasid_entry(s, ce, &pe, PASID_0);
> +    return vtd_ce_get_pasid_entry(s, ce, &pe, IOMMU_NO_PASID);
>   }
>   
>   /* Map a device to its corresponding domain (context-entry) */
> @@ -1564,7 +1564,7 @@ int vtd_dev_to_context_entry(IntelIOMMUState *s, uint8_t bus_num,
>           }
>       } else {
>           /*
> -         * Check if the programming of pasid setting of PASID_0
> +         * Check if the programming of pasid setting of IOMMU_NO_PASID
>            * is valid, and thus avoids to check pasid entry fetching
>            * result in future helper function calling.
>            */
> @@ -2122,7 +2122,7 @@ static bool vtd_do_iommu_translate(VTDAddressSpace *vtd_as, PCIBus *bus,
>       vtd_iommu_lock(s);
>   
>       if (pasid == PCI_NO_PASID && s->root_scalable) {
> -        pasid = PASID_0;
> +        pasid = IOMMU_NO_PASID;
>       }
>   
>       /* Try to fetch pte from IOTLB */
> @@ -2487,7 +2487,7 @@ static void vtd_iotlb_domain_invalidate(IntelIOMMUState *s, uint16_t domain_id)
>   }
>   
>   /*
> - * There is no pasid field in iotlb invalidation descriptor, so PCI_NO_PASID
> + * There is no pasid field in iotlb invalidation descriptor, so IOMMU_NO_PASID
>    * is passed as parameter. Piotlb invalidation supports pasid, pasid in its
>    * descriptor is passed which should not be PCI_NO_PASID.
>    */
> @@ -2508,10 +2508,10 @@ static void vtd_iotlb_page_invalidate_notify(IntelIOMMUState *s,
>                * In legacy mode, vtd_as->pasid == pasid is always true.
>                * In scalable mode, for vtd address space backing a PCI
>                * device without pasid, needs to compare pasid with
> -             * PASID_0 of this device.
> +             * IOMMU_NO_PASID of this device.
>                */
>               if (!(vtd_as->pasid == pasid ||
> -                  (vtd_as->pasid == PCI_NO_PASID && pasid == PASID_0))) {
> +                  (vtd_as->pasid == PCI_NO_PASID && pasid == IOMMU_NO_PASID))) {
>                   continue;
>               }
>   
> @@ -2563,7 +2563,7 @@ static void vtd_iotlb_page_invalidate(IntelIOMMUState *s, uint16_t domain_id,
>       vtd_iommu_lock(s);
>       g_hash_table_foreach_remove(s->iotlb, vtd_hash_remove_by_page, &info);
>       vtd_iommu_unlock(s);
> -    vtd_iotlb_page_invalidate_notify(s, domain_id, addr, am, PCI_NO_PASID);
> +    vtd_iotlb_page_invalidate_notify(s, domain_id, addr, am, IOMMU_NO_PASID);
>   }
>   
>   /* Flush IOTLB
> @@ -3022,7 +3022,7 @@ static void vtd_piotlb_pasid_invalidate(IntelIOMMUState *s,
>           if (!vtd_dev_to_context_entry(s, pci_bus_num(vtd_as->bus),
>                                         vtd_as->devfn, &ce) &&
>               domain_id == vtd_get_domain_id(s, &ce, vtd_as->pasid)) {
> -            if ((vtd_as->pasid != PCI_NO_PASID || pasid != PASID_0) &&
> +            if ((vtd_as->pasid != PCI_NO_PASID || pasid != IOMMU_NO_PASID) &&
>                   vtd_as->pasid != pasid) {
>                   continue;
>               }
> diff --git a/hw/i386/intel_iommu_accel.c b/hw/i386/intel_iommu_accel.c
> index bd1236c070..8940d240a1 100644
> --- a/hw/i386/intel_iommu_accel.c
> +++ b/hw/i386/intel_iommu_accel.c
> @@ -217,7 +217,7 @@ static void vtd_flush_host_piotlb_locked(gpointer key, gpointer value,
>   
>       did = VTD_SM_PASID_ENTRY_DID(&pc_entry->pasid_entry);
>   
> -    if (piotlb_info->domain_id == did && piotlb_info->pasid == PASID_0) {
> +    if (piotlb_info->domain_id == did && piotlb_info->pasid == IOMMU_NO_PASID) {
>           HostIOMMUDeviceIOMMUFD *hiodi =
>               HOST_IOMMU_DEVICE_IOMMUFD(vtd_hiod->hiod);
>           uint32_t entry_num = 1; /* Only implement one request for simplicity */



  reply	other threads:[~2026-05-14 11:17 UTC|newest]

Thread overview: 24+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2026-05-09  4:07 [PATCH v5 00/15] intel_iommu: Enable PASID support for passthrough device Zhenzhong Duan
2026-05-09  4:07 ` [PATCH v5 01/15] vfio/iommufd: Extend attach/detach_hwpt callback implementations with pasid Zhenzhong Duan
2026-05-09  4:07 ` [PATCH v5 02/15] iommufd: Extend attach/detach_hwpt callbacks to support pasid Zhenzhong Duan
2026-05-09  4:07 ` [PATCH v5 03/15] vfio/iommufd: Create nesting parent hwpt with IOMMU_HWPT_ALLOC_PASID flag Zhenzhong Duan
2026-05-09  4:07 ` [PATCH v5 04/15] intel_iommu: Create the nested " Zhenzhong Duan
2026-05-09  4:07 ` [PATCH v5 05/15] intel_iommu: Rename pasid property to "pasid-bits" and define it as type uint8 Zhenzhong Duan
2026-05-14 11:30   ` Yi Liu
2026-05-09  4:07 ` [PATCH v5 06/15] intel_iommu: Export some functions Zhenzhong Duan
2026-05-09  4:08 ` [PATCH v5 07/15] intel_iommu: Use IOMMU_NO_PASID and delete PASID_0 Zhenzhong Duan
2026-05-14 11:24   ` Yi Liu [this message]
2026-05-09  4:08 ` [PATCH v5 08/15] intel_iommu: Refactor PASID processing to use IOMMU_NO_PASID internally Zhenzhong Duan
2026-05-14 11:25   ` Yi Liu
2026-05-09  4:08 ` [PATCH v5 09/15] intel_iommu_accel: Handle PASID entry addition for pc_inv_dsc request Zhenzhong Duan
2026-05-14 11:25   ` Yi Liu
2026-05-09  4:08 ` [PATCH v5 10/15] intel_iommu_accel: Handle PASID entry removal " Zhenzhong Duan
2026-05-14 11:25   ` Yi Liu
2026-05-09  4:08 ` [PATCH v5 11/15] intel_iommu_accel: Bypass PASID entry addition for just deleted entry Zhenzhong Duan
2026-05-14 11:28   ` Yi Liu
2026-05-09  4:08 ` [PATCH v5 12/15] intel_iommu_accel: Handle PASID entry removal for system reset Zhenzhong Duan
2026-05-09  4:08 ` [PATCH v5 13/15] intel_iommu_accel: Switch to VTDAccelPASIDCacheEntry for PASID bind/unbind and PIOTLB invalidation Zhenzhong Duan
2026-05-09  4:08 ` [PATCH v5 14/15] intel_iommu_accel: Add pasid bits size check Zhenzhong Duan
2026-05-14 11:25   ` Yi Liu
2026-05-09  4:08 ` [PATCH v5 15/15] intel_iommu: Expose flag VIOMMU_FLAG_PASID_SUPPORTED and VIOMMU_FLAG_WANT_PASID_ATTACH Zhenzhong Duan
2026-05-14 11:25   ` Yi Liu

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