SMP on virtually indexed/tagged cache

SMP on virtually indexed/tagged cache

[Konrad Eisele]

I trying to get sparc32-smp run on a Leon3 sparc,
it uses a  virtually indexed/tagged cache. Is it possible
to run smp on such a processor? Can cache coherence 
be maintained my the linux kernel only and is there a 
architecture that does that? 
Maybe I have to add a vhdl hardware mechanism to Leon3,
but it would be easier if it could be done in software.
-- Thanks Konrad 

Re: SMP on virtually indexed/tagged cache

[David S. Miller]

On Tue, 12 Apr 2005 14:50:54 +0200
"Konrad Eisele" <eiselekd@web.de> wrote:

> I trying to get sparc32-smp run on a Leon3 sparc,
> it uses a  virtually indexed/tagged cache. Is it possible
> to run smp on such a processor?

Yes, it's just painful.  Model your cache flushing on the
sun4c code.

Re: SMP on virtually indexed/tagged cache

[Konrad Eisele]

"David S. Miller" <davem@davemloft.net> schrieb am 12.04.05 21:28:47:
> 
> On Tue, 12 Apr 2005 14:50:54 +0200
> "Konrad Eisele" <eiselekd@web.de> wrote:
> 
> > I trying to get sparc32-smp run on a Leon3 sparc,
> > it uses a  virtually indexed/tagged cache. Is it possible
> > to run smp on such a processor?
> 
> Yes, it's just painful.  Model your cache flushing on the
> sun4c code.
> -

It's difficult to understand how smp works when cache coherency isn't
done by hardware. 
Have all the the kernel structures to be in nocache memory? Or does
the kernel issue a flush to all processors when modifying them. On a 
Leon I can use a special asi to force a dcache miss, so spinlocks I can
make work, but how are all the other data structures synchronized? By
issuing a flush on every unlock? I'm not so familiar with sun4c and what 
kind of architecture that was. Does it run with SMP and which are the
smp sources for sun4c?, I only find ones for 4d and 4m. There are so
many machine variants and for none I can find out what kind of cache it 
runs with.

-- Konrad

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Re: SMP on virtually indexed/tagged cache

[David S. Miller]

On Wed, 13 Apr 2005 11:26:33 +0200
"Konrad Eisele" <eiselekd@web.de> wrote:

> "David S. Miller" <davem@davemloft.net> schrieb am 12.04.05 21:28:47:
> > 
> > On Tue, 12 Apr 2005 14:50:54 +0200
> > "Konrad Eisele" <eiselekd@web.de> wrote:
> > 
> > > I trying to get sparc32-smp run on a Leon3 sparc,
> > > it uses a  virtually indexed/tagged cache. Is it possible
> > > to run smp on such a processor?
> > 
> > Yes, it's just painful.  Model your cache flushing on the
> > sun4c code.
> > -
> 
> It's difficult to understand how smp works when cache coherency isn't
> done by hardware. 

Oh nevermind, yes that is next to impossible.  If the cpus aren't
doing any cache coherency protocol on the system bus, you're basically
out of luck.

I forgot that physical indexing was necessary for a cache coherency
protocol since the system bus works with physical addresses.