* [PATCH v2] target/riscv/tcg: svinval instructions raise virtual instruction
@ 2026-09-11 19:14 Christian S. Lima
2026-09-11 19:22 ` Christian
0 siblings, 1 reply; 3+ messages in thread
From: Christian S. Lima @ 2026-09-11 19:14 UTC (permalink / raw)
To: qemu-riscv, qemu-devel, Palmer Dabbelt, Alistair Francis,
Weiwei Li, Daniel Henrique Barboza, Liu Zhiwei, Chao Liu
The risc v privileged specification requires hinval.vvma, hinval.gvma,
sfence.w.inval and sfence.inval.ir should raise a virtual instruction
exception when executed in the vu-mode. This patch add the check to
raise the virtual instruction exception when is in the vu-mode.
changes in v2:
- Remove the wrong `return true;` from macro
Resolves: https://gitlab.com/qemu-project/qemu/-/work_items/3621
Signed-off-by: Christian S. Lima <christianslima@proton.me>
---
target/riscv/tcg/insn_trans/trans_svinval.c.inc | 3 +++
target/riscv/tcg/insn_trans/trans_xthead.c.inc | 12 +++++++-----
2 files changed, 10 insertions(+), 5 deletions(-)
diff --git a/target/riscv/tcg/insn_trans/trans_svinval.c.inc b/target/riscv/tcg/insn_trans/trans_svinval.c.inc
index 4614c1489c..5b1172672e 100644
--- a/target/riscv/tcg/insn_trans/trans_svinval.c.inc
+++ b/target/riscv/tcg/insn_trans/trans_svinval.c.inc
@@ -25,6 +25,9 @@
/* Test if priv level is M or S. */
#define REQUIRE_PRIV_MS(ctx) do { \
if (ctx->priv == PRV_U) { \
+ if (ctx->virt_enabled) { \
+ ctx->virt_inst_excp = true \
+ } \
return false; \
} \
} while (0)
diff --git a/target/riscv/tcg/insn_trans/trans_xthead.c.inc b/target/riscv/tcg/insn_trans/trans_xthead.c.inc
index f4e3051000..4bf6594747 100644
--- a/target/riscv/tcg/insn_trans/trans_xthead.c.inc
+++ b/target/riscv/tcg/insn_trans/trans_xthead.c.inc
@@ -267,11 +267,13 @@ static bool trans_th_tst(DisasContext *ctx, arg_th_tst *a)
#define REQUIRE_PRIV_MSU(ctx)
/* Test if priv level is M or S. */
-#define REQUIRE_PRIV_MS(ctx) \
-do { \
- if (ctx->priv == PRV_U) { \
- return false; \
- } \
+#define REQUIRE_PRIV_MS(ctx) do { \
+ if (ctx->priv == PRV_U) { \
+ if (ctx->virt_enabled) { \
+ ctx->virt_inst_excp = true \
+ } \
+ return false; \
+ } \
} while (0)
#define NOP_PRIVCHECK(insn, extcheck, privcheck) \
--
2.55.0
^ permalink raw reply related [flat|nested] 3+ messages in thread* Re: [PATCH v2] target/riscv/tcg: svinval instructions raise virtual instruction
2026-09-11 19:14 [PATCH v2] target/riscv/tcg: svinval instructions raise virtual instruction Christian S. Lima
@ 2026-09-11 19:22 ` Christian
2026-09-11 20:03 ` Daniel Henrique Barboza
0 siblings, 1 reply; 3+ messages in thread
From: Christian @ 2026-09-11 19:22 UTC (permalink / raw)
To: qemu-riscv, qemu-devel, Palmer Dabbelt, Alistair Francis,
Weiwei Li, Daniel Henrique Barboza, Liu Zhiwei, Chao Liu
Hi,
> The risc v privileged specification requires hinval.vvma, hinval.gvma,
> sfence.w.inval and sfence.inval.ir should raise a virtual instruction
> exception when executed in the vu-mode. This patch add the check to
> raise the virtual instruction exception when is in the vu-mode.
>
> changes in v2:
> - Remove the wrong `return true;` from macro
>
> Resolves: https://gitlab.com/qemu-project/qemu/-/work_items/3621
>
> Signed-off-by: Christian S. Lima <christianslima@proton.me>
> ---
> target/riscv/tcg/insn_trans/trans_svinval.c.inc | 3 +++
> target/riscv/tcg/insn_trans/trans_xthead.c.inc | 12 +++++++-----
> 2 files changed, 10 insertions(+), 5 deletions(-)
>
> diff --git a/target/riscv/tcg/insn_trans/trans_svinval.c.inc b/target/riscv/tcg/insn_trans/trans_svinval.c.inc
> index 4614c1489c..5b1172672e 100644
> --- a/target/riscv/tcg/insn_trans/trans_svinval.c.inc
> +++ b/target/riscv/tcg/insn_trans/trans_svinval.c.inc
> @@ -25,6 +25,9 @@
> /* Test if priv level is M or S. */
> #define REQUIRE_PRIV_MS(ctx) do { \
> if (ctx->priv == PRV_U) { \
> + if (ctx->virt_enabled) { \
> + ctx->virt_inst_excp = true \
I missed a `;` here and below, should I resend a v3?
> + } \
> return false; \
> } \
> } while (0)
> diff --git a/target/riscv/tcg/insn_trans/trans_xthead.c.inc b/target/riscv/tcg/insn_trans/trans_xthead.c.inc
> index f4e3051000..4bf6594747 100644
> --- a/target/riscv/tcg/insn_trans/trans_xthead.c.inc
> +++ b/target/riscv/tcg/insn_trans/trans_xthead.c.inc
> @@ -267,11 +267,13 @@ static bool trans_th_tst(DisasContext *ctx, arg_th_tst *a)
> #define REQUIRE_PRIV_MSU(ctx)
>
> /* Test if priv level is M or S. */
> -#define REQUIRE_PRIV_MS(ctx) \
> -do { \
> - if (ctx->priv == PRV_U) { \
> - return false; \
> - } \
> +#define REQUIRE_PRIV_MS(ctx) do { \
> + if (ctx->priv == PRV_U) { \
> + if (ctx->virt_enabled) { \
> + ctx->virt_inst_excp = true \
> + } \
> + return false; \
> + } \
> } while (0)
>
> #define NOP_PRIVCHECK(insn, extcheck, privcheck) \
> --
> 2.55.0
>
>
Thanks,
Christian
^ permalink raw reply [flat|nested] 3+ messages in thread* Re: [PATCH v2] target/riscv/tcg: svinval instructions raise virtual instruction
2026-09-11 19:22 ` Christian
@ 2026-09-11 20:03 ` Daniel Henrique Barboza
0 siblings, 0 replies; 3+ messages in thread
From: Daniel Henrique Barboza @ 2026-09-11 20:03 UTC (permalink / raw)
To: Christian, qemu-riscv, qemu-devel, Palmer Dabbelt,
Alistair Francis, Weiwei Li, Liu Zhiwei, Chao Liu
Hey,
On 9/11/2026 4:22 PM, Christian wrote:
>
> Hi,
>
>> The risc v privileged specification requires hinval.vvma, hinval.gvma,
>> sfence.w.inval and sfence.inval.ir should raise a virtual instruction
>> exception when executed in the vu-mode. This patch add the check to
>> raise the virtual instruction exception when is in the vu-mode.
>>
>> changes in v2:
>> - Remove the wrong `return true;` from macro
>>
>> Resolves: https://gitlab.com/qemu-project/qemu/-/work_items/3621
>>
>> Signed-off-by: Christian S. Lima <christianslima@proton.me>
>> ---
>> target/riscv/tcg/insn_trans/trans_svinval.c.inc | 3 +++
>> target/riscv/tcg/insn_trans/trans_xthead.c.inc | 12 +++++++-----
>> 2 files changed, 10 insertions(+), 5 deletions(-)
>>
>> diff --git a/target/riscv/tcg/insn_trans/trans_svinval.c.inc b/target/riscv/tcg/insn_trans/trans_svinval.c.inc
>> index 4614c1489c..5b1172672e 100644
>> --- a/target/riscv/tcg/insn_trans/trans_svinval.c.inc
>> +++ b/target/riscv/tcg/insn_trans/trans_svinval.c.inc
>> @@ -25,6 +25,9 @@
>> /* Test if priv level is M or S. */
>> #define REQUIRE_PRIV_MS(ctx) do { \
>> if (ctx->priv == PRV_U) { \
>> + if (ctx->virt_enabled) { \
>> + ctx->virt_inst_excp = true \
>
> I missed a `;` here and below, should I resend a v3?
Yes, please send a v3. I believe the patch as is will not compile.
Thanks,
Daniel
>> + } \
>> return false; \
>> } \
>> } while (0)
>> diff --git a/target/riscv/tcg/insn_trans/trans_xthead.c.inc b/target/riscv/tcg/insn_trans/trans_xthead.c.inc
>> index f4e3051000..4bf6594747 100644
>> --- a/target/riscv/tcg/insn_trans/trans_xthead.c.inc
>> +++ b/target/riscv/tcg/insn_trans/trans_xthead.c.inc
>> @@ -267,11 +267,13 @@ static bool trans_th_tst(DisasContext *ctx, arg_th_tst *a)
>> #define REQUIRE_PRIV_MSU(ctx)
>>
>> /* Test if priv level is M or S. */
>> -#define REQUIRE_PRIV_MS(ctx) \
>> -do { \
>> - if (ctx->priv == PRV_U) { \
>> - return false; \
>> - } \
>> +#define REQUIRE_PRIV_MS(ctx) do { \
>> + if (ctx->priv == PRV_U) { \
>> + if (ctx->virt_enabled) { \
>> + ctx->virt_inst_excp = true \
>> + } \
>> + return false; \
>> + } \
>> } while (0)
>>
>> #define NOP_PRIVCHECK(insn, extcheck, privcheck) \
>> --
>> 2.55.0
>>
>>
>
> Thanks,
> Christian
^ permalink raw reply [flat|nested] 3+ messages in thread
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2026-09-11 19:14 [PATCH v2] target/riscv/tcg: svinval instructions raise virtual instruction Christian S. Lima
2026-09-11 19:22 ` Christian
2026-09-11 20:03 ` Daniel Henrique Barboza
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