[PATCH 0/2] fix clock controller register size on Meson8/Meson8b

[PATCH 0/2] fix clock controller register size on Meson8/Meson8b

[Martin Blumenstingl]

While working on some clock controller changes I found that the
register size cannot be correct as it overlaps with the reset
controller.
Amlogic's GPL kernel sources confirm this, as well as a discussion
I had (privately) with Yixun Lan a while ago:
> I think 0x460 is too big, and we could narrow it down (to a small
> size) but I haven't looked at the meson8 datasheet for what the
> exact size of this

The clock controller itself doesn't have a dedicated size because
(just like on GXBB/GXL/GXM) the clock controller is part of a
register area called "HHI". On GXBB this is 0x400 wide, which
matches Meson8/Meson8b/Meson8m2 because the reset controller
begins at CBUS + 0x4404 (0x4400 is some kind of version register),
so "HHI" starting at 0x4000 and ending at 0x4400 sounds reasonable.

I will follow up with more patches which also introduce the HHI
register area on Meson8 and Meson8b (due to the same reasons it
exists on GXBB/GXL/GXM).


Martin Blumenstingl (2):
  ARM: dts: meson8: fix the clock controller register size
  ARM: dts: meson8b: fix the clock controller register size

 arch/arm/boot/dts/meson8.dtsi  | 2 +-
 arch/arm/boot/dts/meson8b.dtsi | 2 +-
 2 files changed, 2 insertions(+), 2 deletions(-)

-- 
2.18.0

[PATCH 1/2] ARM: dts: meson8: fix the clock controller register size

[Martin Blumenstingl]

The clock controller registers are not 0x460 wide because the reset
controller starts at CBUS 0x4404. This currently overlaps with the
clock controller (which is at CBUS 0x4000).

There is no public documentation available on the actual size of the
clock controller's register area (also called "HHI"). However, in
Amlogic's GPL kernel sources the last "HHI" register is
HHI_HDMI_PHY_CNTL2 at CBUS + 0x43a8. 0x400 was chosen because that size
doesn't seem unlikely.

Fixes: 2c323c43a3d619 ("ARM: dts: meson8: add and use the real clock controller")
Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com>
---
 arch/arm/boot/dts/meson8.dtsi | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/arch/arm/boot/dts/meson8.dtsi b/arch/arm/boot/dts/meson8.dtsi
index d77dcf890cfc..7162e0ca05b0 100644
--- a/arch/arm/boot/dts/meson8.dtsi
+++ b/arch/arm/boot/dts/meson8.dtsi
@@ -194,7 +194,7 @@
 		#clock-cells = <1>;
 		#reset-cells = <1>;
 		compatible = "amlogic,meson8-clkc";
-		reg = <0x8000 0x4>, <0x4000 0x460>;
+		reg = <0x8000 0x4>, <0x4000 0x400>;
 	};
 
 	reset: reset-controller at 4404 {
-- 
2.18.0

[PATCH 2/2] ARM: dts: meson8b: fix the clock controller register size

[Martin Blumenstingl]

The clock controller registers are not 0x460 wide because the reset
controller starts at CBUS 0x4404. This currently overlaps with the
clock controller (which is at CBUS 0x4000).

There is no public documentation available on the actual size of the
clock controller's register area (also called "HHI"). However, in
Amlogic's GPL kernel sources the last "HHI" register is
HHI_HDMI_PHY_CNTL2 at CBUS + 0x43a8. 0x400 was chosen because that size
doesn't seem unlikely.

Fixes: 4a69fcd3a10803 ("ARM: meson: Add DTS for Odroid-C1 and Tronfy MXQ boards")
Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com>
---
 arch/arm/boot/dts/meson8b.dtsi | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/arch/arm/boot/dts/meson8b.dtsi b/arch/arm/boot/dts/meson8b.dtsi
index 08f7f6be7254..f77e419c1c65 100644
--- a/arch/arm/boot/dts/meson8b.dtsi
+++ b/arch/arm/boot/dts/meson8b.dtsi
@@ -163,7 +163,7 @@
 		#clock-cells = <1>;
 		#reset-cells = <1>;
 		compatible = "amlogic,meson8b-clkc";
-		reg = <0x8000 0x4>, <0x4000 0x460>;
+		reg = <0x8000 0x4>, <0x4000 0x400>;
 	};
 
 	reset: reset-controller at 4404 {
-- 
2.18.0

[PATCH 1/2] ARM: dts: meson8: fix the clock controller register size

[Neil Armstrong]

On 21/07/2018 21:05, Martin Blumenstingl wrote:
> The clock controller registers are not 0x460 wide because the reset
> controller starts at CBUS 0x4404. This currently overlaps with the
> clock controller (which is at CBUS 0x4000).
> 
> There is no public documentation available on the actual size of the
> clock controller's register area (also called "HHI"). However, in
> Amlogic's GPL kernel sources the last "HHI" register is
> HHI_HDMI_PHY_CNTL2 at CBUS + 0x43a8. 0x400 was chosen because that size
> doesn't seem unlikely.
> 
> Fixes: 2c323c43a3d619 ("ARM: dts: meson8: add and use the real clock controller")
> Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com>
> ---
>  arch/arm/boot/dts/meson8.dtsi | 2 +-
>  1 file changed, 1 insertion(+), 1 deletion(-)
> 
> diff --git a/arch/arm/boot/dts/meson8.dtsi b/arch/arm/boot/dts/meson8.dtsi
> index d77dcf890cfc..7162e0ca05b0 100644
> --- a/arch/arm/boot/dts/meson8.dtsi
> +++ b/arch/arm/boot/dts/meson8.dtsi
> @@ -194,7 +194,7 @@
>  		#clock-cells = <1>;
>  		#reset-cells = <1>;
>  		compatible = "amlogic,meson8-clkc";
> -		reg = <0x8000 0x4>, <0x4000 0x460>;
> +		reg = <0x8000 0x4>, <0x4000 0x400>;
>  	};
>  
>  	reset: reset-controller at 4404 {
> 


Reviewed-by: Neil Armstrong <narmstrong@baylibre.com>

[PATCH 2/2] ARM: dts: meson8b: fix the clock controller register size

[Neil Armstrong]

On 21/07/2018 21:05, Martin Blumenstingl wrote:
> The clock controller registers are not 0x460 wide because the reset
> controller starts at CBUS 0x4404. This currently overlaps with the
> clock controller (which is at CBUS 0x4000).
> 
> There is no public documentation available on the actual size of the
> clock controller's register area (also called "HHI"). However, in
> Amlogic's GPL kernel sources the last "HHI" register is
> HHI_HDMI_PHY_CNTL2 at CBUS + 0x43a8. 0x400 was chosen because that size
> doesn't seem unlikely.
> 
> Fixes: 4a69fcd3a10803 ("ARM: meson: Add DTS for Odroid-C1 and Tronfy MXQ boards")
> Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com>
> ---
>  arch/arm/boot/dts/meson8b.dtsi | 2 +-
>  1 file changed, 1 insertion(+), 1 deletion(-)
> 
> diff --git a/arch/arm/boot/dts/meson8b.dtsi b/arch/arm/boot/dts/meson8b.dtsi
> index 08f7f6be7254..f77e419c1c65 100644
> --- a/arch/arm/boot/dts/meson8b.dtsi
> +++ b/arch/arm/boot/dts/meson8b.dtsi
> @@ -163,7 +163,7 @@
>  		#clock-cells = <1>;
>  		#reset-cells = <1>;
>  		compatible = "amlogic,meson8b-clkc";
> -		reg = <0x8000 0x4>, <0x4000 0x460>;
> +		reg = <0x8000 0x4>, <0x4000 0x400>;
>  	};
>  
>  	reset: reset-controller at 4404 {
> 

Reviewed-by: Neil Armstrong <narmstrong@baylibre.com>

[PATCH 0/2] fix clock controller register size on Meson8/Meson8b

[Kevin Hilman]

Martin Blumenstingl <martin.blumenstingl@googlemail.com> writes:

> While working on some clock controller changes I found that the
> register size cannot be correct as it overlaps with the reset
> controller.
> Amlogic's GPL kernel sources confirm this, as well as a discussion
> I had (privately) with Yixun Lan a while ago:
>> I think 0x460 is too big, and we could narrow it down (to a small
>> size) but I haven't looked at the meson8 datasheet for what the
>> exact size of this
>
> The clock controller itself doesn't have a dedicated size because
> (just like on GXBB/GXL/GXM) the clock controller is part of a
> register area called "HHI". On GXBB this is 0x400 wide, which
> matches Meson8/Meson8b/Meson8m2 because the reset controller
> begins at CBUS + 0x4404 (0x4400 is some kind of version register),
> so "HHI" starting at 0x4000 and ending at 0x4400 sounds reasonable.

Agreed.

Applied to v4.19/dt.  Not sure if I'll get another PR out for the v4.19
merge window, but if not, I'll queue with fixes v4.19-rc.

Thanks for the fixes,

Kevin