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From: "Heiko Stübner" <heiko@sntech.de>
To: krzk+dt@kernel.org, palmer@dabbelt.com, robh+dt@kernel.org,
	Conor Dooley <mail@conchuod.ie>
Cc: conor.dooley@microchip.com, Cyril.Jean@microchip.com,
	daire.mcnamara@microchip.com, paul.walmsley@sifive.com,
	aou@eecs.berkeley.edu, palmer@rivosinc.com, arnd@arndb.de,
	devicetree@vger.kernel.org, linux-kernel@vger.kernel.org,
	linux-riscv@lists.infradead.org
Subject: Re: [PATCH v4 8/8] riscv: dts: microchip: add the sundance polarberry
Date: Mon, 09 May 2022 13:10:12 +0200	[thread overview]
Message-ID: <8060906.T7Z3S40VBb@diego> (raw)
In-Reply-To: <20220504203051.1210355-9-mail@conchuod.ie>

Am Mittwoch, 4. Mai 2022, 22:30:52 CEST schrieb Conor Dooley:
> From: Conor Dooley <conor.dooley@microchip.com>
> 
> Add a minimal device tree for the PolarFire SoC based Sundance
> PolarBerry.
> 
> Signed-off-by: Conor Dooley <conor.dooley@microchip.com>
> ---
>  arch/riscv/boot/dts/microchip/Makefile        |  1 +
>  .../dts/microchip/mpfs-polarberry-fabric.dtsi | 16 +++
>  .../boot/dts/microchip/mpfs-polarberry.dts    | 97 +++++++++++++++++++
>  3 files changed, 114 insertions(+)
>  create mode 100644 arch/riscv/boot/dts/microchip/mpfs-polarberry-fabric.dtsi
>  create mode 100644 arch/riscv/boot/dts/microchip/mpfs-polarberry.dts
> 
> diff --git a/arch/riscv/boot/dts/microchip/Makefile b/arch/riscv/boot/dts/microchip/Makefile
> index af3a5059b350..39aae7b04f1c 100644
> --- a/arch/riscv/boot/dts/microchip/Makefile
> +++ b/arch/riscv/boot/dts/microchip/Makefile
> @@ -1,3 +1,4 @@
>  # SPDX-License-Identifier: GPL-2.0
>  dtb-$(CONFIG_SOC_MICROCHIP_POLARFIRE) += mpfs-icicle-kit.dtb
> +dtb-$(CONFIG_SOC_MICROCHIP_POLARFIRE) += mpfs-polarberry.dtb
>  obj-$(CONFIG_BUILTIN_DTB) += $(addsuffix .o, $(dtb-y))
> diff --git a/arch/riscv/boot/dts/microchip/mpfs-polarberry-fabric.dtsi b/arch/riscv/boot/dts/microchip/mpfs-polarberry-fabric.dtsi
> new file mode 100644
> index 000000000000..49380c428ec9
> --- /dev/null
> +++ b/arch/riscv/boot/dts/microchip/mpfs-polarberry-fabric.dtsi
> @@ -0,0 +1,16 @@
> +// SPDX-License-Identifier: (GPL-2.0 OR MIT)
> +/* Copyright (c) 2020-2022 Microchip Technology Inc */
> +
> +/ {
> +	fabric_clk3: fabric-clk3 {
> +		compatible = "fixed-clock";
> +		#clock-cells = <0>;
> +		clock-frequency = <62500000>;
> +	};
> +
> +	fabric_clk1: fabric-clk1 {
> +		compatible = "fixed-clock";
> +		#clock-cells = <0>;
> +		clock-frequency = <125000000>;
> +	};
> +};
> diff --git a/arch/riscv/boot/dts/microchip/mpfs-polarberry.dts b/arch/riscv/boot/dts/microchip/mpfs-polarberry.dts
> new file mode 100644
> index 000000000000..1cad5b0d42e1
> --- /dev/null
> +++ b/arch/riscv/boot/dts/microchip/mpfs-polarberry.dts
> @@ -0,0 +1,97 @@
> +// SPDX-License-Identifier: (GPL-2.0 OR MIT)
> +/* Copyright (c) 2020-2022 Microchip Technology Inc */
> +
> +/dts-v1/;
> +
> +#include "mpfs.dtsi"
> +#include "mpfs-polarberry-fabric.dtsi"
> +
> +/* Clock frequency (in Hz) of the rtcclk */
> +#define MTIMER_FREQ	1000000
> +
> +/ {
> +	model = "Sundance PolarBerry";
> +	compatible = "sundance,polarberry", "microchip,mpfs";
> +
> +	aliases {
> +		ethernet0 = &mac1;
> +		serial0 = &mmuart0;
> +	};
> +
> +	chosen {
> +		stdout-path = "serial0:115200n8";
> +	};
> +
> +	cpus {
> +		timebase-frequency = <MTIMER_FREQ>;
> +	};
> +
> +	ddrc_cache_lo: memory@80000000 {
> +		device_type = "memory";
> +		reg = <0x0 0x80000000 0x0 0x2e000000>;
> +	};
> +
> +	ddrc_cache_hi: memory@1000000000 {
> +		device_type = "memory";
> +		reg = <0x10 0x00000000 0x0 0xC0000000>;
> +	};
> +};
> +
> +/*
> + * phy0 is connected to mac0, but the port itself is on the (optional) carrier
> + * board.
> + */
> +&mac0 {
> +	status = "disabled";
> +	phy-mode = "sgmii";
> +	phy-handle = <&phy0>;

nit: it makes it was easier recognizing the status if it's in the
same place all the time (for example as the last property)
like in &mmc below.

Though that may just be my preference ;-) .
The other option would be to adhere to stricter sorting
because right now status is neither in one place nor sorted.


> +};
> +
> +&mac1 {
> +	status = "okay";
> +	phy-mode = "sgmii";
> +	phy-handle = <&phy1>;

nit (1): same as above
nit (2): blank line between properties and subnodes makes
  everything more readable.

> +	phy1: ethernet-phy@5 {
> +		reg = <5>;
> +		ti,fifo-depth = <0x01>;
> +	};

nit: blank line?

Otherwise:
Reviewed-by: Heiko Stuebner <heiko@sntech.de>

> +	phy0: ethernet-phy@4 {
> +		reg = <4>;
> +		ti,fifo-depth = <0x01>;
> +	};
> +};
> +
> +&mbox {
> +	status = "okay";
> +};
> +
> +&mmc {
> +	bus-width = <4>;
> +	disable-wp;
> +	cap-sd-highspeed;
> +	cap-mmc-highspeed;
> +	card-detect-delay = <200>;
> +	mmc-ddr-1_8v;
> +	mmc-hs200-1_8v;
> +	sd-uhs-sdr12;
> +	sd-uhs-sdr25;
> +	sd-uhs-sdr50;
> +	sd-uhs-sdr104;
> +	status = "okay";
> +};
> +
> +&mmuart0 {
> +	status = "okay";
> +};
> +
> +&refclk {
> +	clock-frequency = <125000000>;
> +};
> +
> +&rtc {
> +	status = "okay";
> +};
> +
> +&syscontroller {
> +	status = "okay";
> +};
> 





_______________________________________________
linux-riscv mailing list
linux-riscv@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-riscv

WARNING: multiple messages have this Message-ID (diff)
From: "Heiko Stübner" <heiko@sntech.de>
To: krzk+dt@kernel.org, palmer@dabbelt.com, robh+dt@kernel.org,
	Conor Dooley <mail@conchuod.ie>
Cc: conor.dooley@microchip.com, Cyril.Jean@microchip.com,
	daire.mcnamara@microchip.com, paul.walmsley@sifive.com,
	aou@eecs.berkeley.edu, palmer@rivosinc.com, arnd@arndb.de,
	devicetree@vger.kernel.org, linux-kernel@vger.kernel.org,
	linux-riscv@lists.infradead.org
Subject: Re: [PATCH v4 8/8] riscv: dts: microchip: add the sundance polarberry
Date: Mon, 09 May 2022 13:10:12 +0200	[thread overview]
Message-ID: <8060906.T7Z3S40VBb@diego> (raw)
In-Reply-To: <20220504203051.1210355-9-mail@conchuod.ie>

Am Mittwoch, 4. Mai 2022, 22:30:52 CEST schrieb Conor Dooley:
> From: Conor Dooley <conor.dooley@microchip.com>
> 
> Add a minimal device tree for the PolarFire SoC based Sundance
> PolarBerry.
> 
> Signed-off-by: Conor Dooley <conor.dooley@microchip.com>
> ---
>  arch/riscv/boot/dts/microchip/Makefile        |  1 +
>  .../dts/microchip/mpfs-polarberry-fabric.dtsi | 16 +++
>  .../boot/dts/microchip/mpfs-polarberry.dts    | 97 +++++++++++++++++++
>  3 files changed, 114 insertions(+)
>  create mode 100644 arch/riscv/boot/dts/microchip/mpfs-polarberry-fabric.dtsi
>  create mode 100644 arch/riscv/boot/dts/microchip/mpfs-polarberry.dts
> 
> diff --git a/arch/riscv/boot/dts/microchip/Makefile b/arch/riscv/boot/dts/microchip/Makefile
> index af3a5059b350..39aae7b04f1c 100644
> --- a/arch/riscv/boot/dts/microchip/Makefile
> +++ b/arch/riscv/boot/dts/microchip/Makefile
> @@ -1,3 +1,4 @@
>  # SPDX-License-Identifier: GPL-2.0
>  dtb-$(CONFIG_SOC_MICROCHIP_POLARFIRE) += mpfs-icicle-kit.dtb
> +dtb-$(CONFIG_SOC_MICROCHIP_POLARFIRE) += mpfs-polarberry.dtb
>  obj-$(CONFIG_BUILTIN_DTB) += $(addsuffix .o, $(dtb-y))
> diff --git a/arch/riscv/boot/dts/microchip/mpfs-polarberry-fabric.dtsi b/arch/riscv/boot/dts/microchip/mpfs-polarberry-fabric.dtsi
> new file mode 100644
> index 000000000000..49380c428ec9
> --- /dev/null
> +++ b/arch/riscv/boot/dts/microchip/mpfs-polarberry-fabric.dtsi
> @@ -0,0 +1,16 @@
> +// SPDX-License-Identifier: (GPL-2.0 OR MIT)
> +/* Copyright (c) 2020-2022 Microchip Technology Inc */
> +
> +/ {
> +	fabric_clk3: fabric-clk3 {
> +		compatible = "fixed-clock";
> +		#clock-cells = <0>;
> +		clock-frequency = <62500000>;
> +	};
> +
> +	fabric_clk1: fabric-clk1 {
> +		compatible = "fixed-clock";
> +		#clock-cells = <0>;
> +		clock-frequency = <125000000>;
> +	};
> +};
> diff --git a/arch/riscv/boot/dts/microchip/mpfs-polarberry.dts b/arch/riscv/boot/dts/microchip/mpfs-polarberry.dts
> new file mode 100644
> index 000000000000..1cad5b0d42e1
> --- /dev/null
> +++ b/arch/riscv/boot/dts/microchip/mpfs-polarberry.dts
> @@ -0,0 +1,97 @@
> +// SPDX-License-Identifier: (GPL-2.0 OR MIT)
> +/* Copyright (c) 2020-2022 Microchip Technology Inc */
> +
> +/dts-v1/;
> +
> +#include "mpfs.dtsi"
> +#include "mpfs-polarberry-fabric.dtsi"
> +
> +/* Clock frequency (in Hz) of the rtcclk */
> +#define MTIMER_FREQ	1000000
> +
> +/ {
> +	model = "Sundance PolarBerry";
> +	compatible = "sundance,polarberry", "microchip,mpfs";
> +
> +	aliases {
> +		ethernet0 = &mac1;
> +		serial0 = &mmuart0;
> +	};
> +
> +	chosen {
> +		stdout-path = "serial0:115200n8";
> +	};
> +
> +	cpus {
> +		timebase-frequency = <MTIMER_FREQ>;
> +	};
> +
> +	ddrc_cache_lo: memory@80000000 {
> +		device_type = "memory";
> +		reg = <0x0 0x80000000 0x0 0x2e000000>;
> +	};
> +
> +	ddrc_cache_hi: memory@1000000000 {
> +		device_type = "memory";
> +		reg = <0x10 0x00000000 0x0 0xC0000000>;
> +	};
> +};
> +
> +/*
> + * phy0 is connected to mac0, but the port itself is on the (optional) carrier
> + * board.
> + */
> +&mac0 {
> +	status = "disabled";
> +	phy-mode = "sgmii";
> +	phy-handle = <&phy0>;

nit: it makes it was easier recognizing the status if it's in the
same place all the time (for example as the last property)
like in &mmc below.

Though that may just be my preference ;-) .
The other option would be to adhere to stricter sorting
because right now status is neither in one place nor sorted.


> +};
> +
> +&mac1 {
> +	status = "okay";
> +	phy-mode = "sgmii";
> +	phy-handle = <&phy1>;

nit (1): same as above
nit (2): blank line between properties and subnodes makes
  everything more readable.

> +	phy1: ethernet-phy@5 {
> +		reg = <5>;
> +		ti,fifo-depth = <0x01>;
> +	};

nit: blank line?

Otherwise:
Reviewed-by: Heiko Stuebner <heiko@sntech.de>

> +	phy0: ethernet-phy@4 {
> +		reg = <4>;
> +		ti,fifo-depth = <0x01>;
> +	};
> +};
> +
> +&mbox {
> +	status = "okay";
> +};
> +
> +&mmc {
> +	bus-width = <4>;
> +	disable-wp;
> +	cap-sd-highspeed;
> +	cap-mmc-highspeed;
> +	card-detect-delay = <200>;
> +	mmc-ddr-1_8v;
> +	mmc-hs200-1_8v;
> +	sd-uhs-sdr12;
> +	sd-uhs-sdr25;
> +	sd-uhs-sdr50;
> +	sd-uhs-sdr104;
> +	status = "okay";
> +};
> +
> +&mmuart0 {
> +	status = "okay";
> +};
> +
> +&refclk {
> +	clock-frequency = <125000000>;
> +};
> +
> +&rtc {
> +	status = "okay";
> +};
> +
> +&syscontroller {
> +	status = "okay";
> +};
> 





  reply	other threads:[~2022-05-09 11:10 UTC|newest]

Thread overview: 28+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2022-05-04 20:30 [PATCH v4 0/8] PolarFire SoC dt for 5.19 Conor Dooley
2022-05-04 20:30 ` Conor Dooley
2022-05-04 20:30 ` [PATCH v4 1/8] riscv: dts: microchip: remove icicle memory clocks Conor Dooley
2022-05-04 20:30   ` Conor Dooley
2022-05-04 20:30 ` [PATCH v4 2/8] riscv: dts: microchip: move sysctrlr out of soc bus Conor Dooley
2022-05-04 20:30   ` Conor Dooley
2022-05-09 11:04   ` Heiko Stübner
2022-05-09 11:04     ` Heiko Stübner
2022-05-04 20:30 ` [PATCH v4 3/8] riscv: dts: microchip: remove soc vendor from filenames Conor Dooley
2022-05-04 20:30   ` Conor Dooley
2022-05-04 20:30 ` [PATCH v4 4/8] dt-bindings: riscv: microchip: document icicle reference design Conor Dooley
2022-05-04 20:30   ` Conor Dooley
2022-05-04 20:30 ` [PATCH v4 5/8] riscv: dts: microchip: make the fabric dtsi board specific Conor Dooley
2022-05-04 20:30   ` Conor Dooley
2022-05-04 20:30 ` [PATCH v4 6/8] dt-bindings: vendor-prefixes: add Sundance DSP Conor Dooley
2022-05-04 20:30   ` Conor Dooley
2022-05-04 20:30 ` [PATCH v4 7/8] dt-bindings: riscv: microchip: add polarberry compatible string Conor Dooley
2022-05-04 20:30   ` Conor Dooley
2022-05-04 20:30 ` [PATCH v4 8/8] riscv: dts: microchip: add the sundance polarberry Conor Dooley
2022-05-04 20:30   ` Conor Dooley
2022-05-09 11:10   ` Heiko Stübner [this message]
2022-05-09 11:10     ` Heiko Stübner
2022-05-09 11:24     ` Conor.Dooley
2022-05-09 11:24       ` Conor.Dooley
2022-05-09 13:07       ` Heiko Stübner
2022-05-09 13:07         ` Heiko Stübner
2022-05-09 13:23         ` Conor.Dooley
2022-05-09 13:23           ` Conor.Dooley

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